xref: /dpdk/drivers/common/cnxk/roc_se.h (revision 759b5e65)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #ifndef __ROC_SE_H__
6 #define __ROC_SE_H__
7 
8 /* SE opcodes */
9 #define ROC_SE_MAJOR_OP_FC	      0x33
10 #define ROC_SE_FC_MINOR_OP_ENCRYPT    0x0
11 #define ROC_SE_FC_MINOR_OP_DECRYPT    0x1
12 #define ROC_SE_FC_MINOR_OP_HMAC_FIRST 0x10
13 
14 #define ROC_SE_MAJOR_OP_HASH   0x34
15 #define ROC_SE_MAJOR_OP_HMAC   0x35
16 #define ROC_SE_MAJOR_OP_PDCP   0x37
17 #define ROC_SE_MAJOR_OP_KASUMI 0x38
18 
19 #define ROC_SE_MAJOR_OP_MISC		 0x01
20 #define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03
21 #define ROC_SE_MISC_MINOR_OP_DUMMY	 0x04
22 #define ROC_SE_MISC_MINOR_OP_HW_SUPPORT	 0x08
23 
24 #define ROC_SE_MAX_AAD_SIZE 64
25 #define ROC_SE_MAX_MAC_LEN  64
26 
27 #define ROC_SE_OFF_CTRL_LEN 8
28 #define ROC_SE_DMA_MODE	    (1 << 7)
29 
30 #define ROC_SE_MAX_SG_IN_OUT_CNT 32
31 #define ROC_SE_MAX_SG_CNT	 (ROC_SE_MAX_SG_IN_OUT_CNT / 2)
32 
33 #define ROC_SE_SG_LIST_HDR_SIZE (8u)
34 #define ROC_SE_SG_ENTRY_SIZE	sizeof(struct roc_se_sglist_comp)
35 
36 #define ROC_SE_ZS_EA 0x1
37 #define ROC_SE_ZS_IA 0x2
38 #define ROC_SE_K_F8  0x4
39 #define ROC_SE_K_F9  0x8
40 
41 #define ROC_SE_FC_GEN	 0x1
42 #define ROC_SE_PDCP	 0x2
43 #define ROC_SE_KASUMI	 0x3
44 #define ROC_SE_HASH_HMAC 0x4
45 
46 #define ROC_SE_OP_CIPHER_ENCRYPT 0x1
47 #define ROC_SE_OP_CIPHER_DECRYPT 0x2
48 #define ROC_SE_OP_CIPHER_MASK                                                  \
49 	(ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_CIPHER_DECRYPT)
50 
51 #define ROC_SE_OP_AUTH_VERIFY	0x4
52 #define ROC_SE_OP_AUTH_GENERATE 0x8
53 #define ROC_SE_OP_AUTH_MASK                                                    \
54 	(ROC_SE_OP_AUTH_VERIFY | ROC_SE_OP_AUTH_GENERATE)
55 
56 #define ROC_SE_OP_ENCODE (ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_AUTH_GENERATE)
57 #define ROC_SE_OP_DECODE (ROC_SE_OP_CIPHER_DECRYPT | ROC_SE_OP_AUTH_VERIFY)
58 
59 #define ROC_SE_ALWAYS_USE_SEPARATE_BUF
60 
61 /*
62  * Parameters for Flexi Crypto
63  * requests
64  */
65 #define ROC_SE_VALID_AAD_BUF	       0x01
66 #define ROC_SE_VALID_MAC_BUF	       0x02
67 #define ROC_SE_VALID_IV_BUF	       0x04
68 #define ROC_SE_SINGLE_BUF_INPLACE      0x08
69 #define ROC_SE_SINGLE_BUF_HEADROOM     0x10
70 
71 #define ROC_SE_ENCR_IV_OFFSET(__d_offs) (((__d_offs) >> 32) & 0xffff)
72 #define ROC_SE_ENCR_OFFSET(__d_offs)	(((__d_offs) >> 16) & 0xffff)
73 #define ROC_SE_AUTH_OFFSET(__d_offs)	((__d_offs) & 0xffff)
74 #define ROC_SE_ENCR_DLEN(__d_lens)	((__d_lens) >> 32)
75 #define ROC_SE_AUTH_DLEN(__d_lens)	((__d_lens) & 0xffffffff)
76 
77 typedef enum { ROC_SE_FROM_CTX = 0, ROC_SE_FROM_DPTR = 1 } roc_se_input_type;
78 
79 typedef enum {
80 	ROC_SE_MD5_TYPE = 1,
81 	ROC_SE_SHA1_TYPE = 2,
82 	ROC_SE_SHA2_SHA224 = 3,
83 	ROC_SE_SHA2_SHA256 = 4,
84 	ROC_SE_SHA2_SHA384 = 5,
85 	ROC_SE_SHA2_SHA512 = 6,
86 	ROC_SE_GMAC_TYPE = 7,
87 	ROC_SE_POLY1305 = 8,
88 	ROC_SE_SHA3_SHA224 = 10,
89 	ROC_SE_SHA3_SHA256 = 11,
90 	ROC_SE_SHA3_SHA384 = 12,
91 	ROC_SE_SHA3_SHA512 = 13,
92 	ROC_SE_SHA3_SHAKE256 = 14,
93 	ROC_SE_SHA3_SHAKE512 = 15,
94 
95 	/* These are only for software use */
96 	ROC_SE_ZUC_EIA3 = 0x90,
97 	ROC_SE_SNOW3G_UIA2 = 0x91,
98 	ROC_SE_AES_CMAC_EIA2 = 0x92,
99 	ROC_SE_KASUMI_F9_CBC = 0x93,
100 	ROC_SE_KASUMI_F9_ECB = 0x94,
101 } roc_se_auth_type;
102 
103 typedef enum {
104 	/* To support passthrough */
105 	ROC_SE_PASSTHROUGH = 0x0,
106 	/*
107 	 * These are defined by MC for Flexi crypto
108 	 * for field of 4 bits
109 	 */
110 	ROC_SE_DES3_CBC = 0x1,
111 	ROC_SE_DES3_ECB = 0x2,
112 	ROC_SE_AES_CBC = 0x3,
113 	ROC_SE_AES_ECB = 0x4,
114 	ROC_SE_AES_CFB = 0x5,
115 	ROC_SE_AES_CTR = 0x6,
116 	ROC_SE_AES_GCM = 0x7,
117 	ROC_SE_AES_XTS = 0x8,
118 	ROC_SE_CHACHA20 = 0x9,
119 
120 	/* These are only for software use */
121 	ROC_SE_ZUC_EEA3 = 0x90,
122 	ROC_SE_SNOW3G_UEA2 = 0x91,
123 	ROC_SE_AES_CTR_EEA2 = 0x92,
124 	ROC_SE_KASUMI_F8_CBC = 0x93,
125 	ROC_SE_KASUMI_F8_ECB = 0x94,
126 } roc_se_cipher_type;
127 
128 typedef enum {
129 	/* Microcode errors */
130 	ROC_SE_NO_ERR = 0x00,
131 	ROC_SE_ERR_OPCODE_UNSUPPORTED = 0x01,
132 
133 	/* SCATTER GATHER */
134 	ROC_SE_ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
135 	ROC_SE_ERR_SCATTER_GATHER_LIST = 0x03,
136 	ROC_SE_ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
137 
138 	/* SE GC */
139 	ROC_SE_ERR_GC_LENGTH_INVALID = 0x41,
140 	ROC_SE_ERR_GC_RANDOM_LEN_INVALID = 0x42,
141 	ROC_SE_ERR_GC_DATA_LEN_INVALID = 0x43,
142 	ROC_SE_ERR_GC_DRBG_TYPE_INVALID = 0x44,
143 	ROC_SE_ERR_GC_CTX_LEN_INVALID = 0x45,
144 	ROC_SE_ERR_GC_CIPHER_UNSUPPORTED = 0x46,
145 	ROC_SE_ERR_GC_AUTH_UNSUPPORTED = 0x47,
146 	ROC_SE_ERR_GC_OFFSET_INVALID = 0x48,
147 	ROC_SE_ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
148 	ROC_SE_ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
149 	ROC_SE_ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
150 	ROC_SE_ERR_GC_ICV_MISCOMPARE = 0x4c,
151 	ROC_SE_ERR_GC_DATA_UNALIGNED = 0x4d,
152 
153 	/* API Layer */
154 	ROC_SE_ERR_REQ_PENDING = 0xfe,
155 	ROC_SE_ERR_REQ_TIMEOUT = 0xff,
156 
157 } roc_se_error_code;
158 
159 typedef enum {
160 	ROC_SE_AES_128_BIT = 0x1,
161 	ROC_SE_AES_192_BIT = 0x2,
162 	ROC_SE_AES_256_BIT = 0x3
163 } roc_se_aes_type;
164 
165 typedef enum {
166 	ROC_SE_PDCP_MAC_LEN_32_BIT = 0x1,
167 	ROC_SE_PDCP_MAC_LEN_64_BIT = 0x2,
168 	ROC_SE_PDCP_MAC_LEN_128_BIT = 0x3
169 } roc_se_pdcp_mac_len_type;
170 
171 struct roc_se_sglist_comp {
172 	union {
173 		uint64_t len;
174 		struct {
175 			uint16_t len[4];
176 		} s;
177 	} u;
178 	uint64_t ptr[4];
179 };
180 
181 struct roc_se_enc_context {
182 	uint64_t iv_source : 1;
183 	uint64_t aes_key : 2;
184 	uint64_t rsvd_60 : 1;
185 	uint64_t enc_cipher : 4;
186 	uint64_t auth_input_type : 1;
187 	uint64_t rsvd_52_54 : 3;
188 	uint64_t hash_type : 4;
189 	uint64_t mac_len : 8;
190 	uint64_t rsvd_39_0 : 40;
191 	uint8_t encr_key[32];
192 	uint8_t encr_iv[16];
193 };
194 
195 struct roc_se_hmac_context {
196 	uint8_t ipad[64];
197 	uint8_t opad[64];
198 };
199 
200 struct roc_se_context {
201 	struct roc_se_enc_context enc;
202 	struct roc_se_hmac_context hmac;
203 };
204 
205 struct roc_se_otk_zuc_ctx {
206 	union {
207 		uint64_t u64;
208 		struct {
209 			uint64_t rsvd_56 : 57;
210 			uint64_t mac_len : 2;
211 			uint64_t key_len : 2;
212 			uint64_t lfsr_state : 1;
213 			uint64_t alg_type : 2;
214 		} s;
215 	} w0;
216 	uint8_t ci_key[32];
217 	uint8_t encr_auth_iv[24];
218 	uint8_t zuc_const[32];
219 };
220 
221 struct roc_se_onk_zuc_ctx {
222 	uint8_t encr_auth_iv[16];
223 	uint8_t ci_key[16];
224 	uint8_t zuc_const[32];
225 };
226 
227 struct roc_se_zuc_snow3g_ctx {
228 	union {
229 		struct roc_se_onk_zuc_ctx onk_ctx;
230 		struct roc_se_otk_zuc_ctx otk_ctx;
231 	} zuc;
232 };
233 
234 struct roc_se_kasumi_ctx {
235 	uint8_t reg_A[8];
236 	uint8_t ci_key[16];
237 };
238 
239 /* Buffer pointer */
240 struct roc_se_buf_ptr {
241 	void *vaddr;
242 	uint32_t size;
243 	uint32_t resv;
244 };
245 
246 /* IOV Pointer */
247 struct roc_se_iov_ptr {
248 	int buf_cnt;
249 	struct roc_se_buf_ptr bufs[0];
250 };
251 
252 struct roc_se_fc_params {
253 	/* 0th cache line */
254 	union {
255 		struct roc_se_buf_ptr bufs[1];
256 		struct {
257 			struct roc_se_iov_ptr *src_iov;
258 			struct roc_se_iov_ptr *dst_iov;
259 		};
260 	};
261 	void *iv_buf;
262 	void *auth_iv_buf;
263 	struct roc_se_buf_ptr meta_buf;
264 	struct roc_se_buf_ptr ctx_buf;
265 	uint32_t rsvd2;
266 	uint8_t rsvd3;
267 	uint8_t iv_ovr;
268 	uint8_t cipher_iv_len;
269 	uint8_t auth_iv_len;
270 
271 	/* 1st cache line */
272 	struct roc_se_buf_ptr aad_buf __plt_cache_aligned;
273 	struct roc_se_buf_ptr mac_buf;
274 };
275 
276 PLT_STATIC_ASSERT((offsetof(struct roc_se_fc_params, aad_buf) % 128) == 0);
277 
278 #define ROC_SE_PDCP_ALG_TYPE_ZUC     0
279 #define ROC_SE_PDCP_ALG_TYPE_SNOW3G  1
280 #define ROC_SE_PDCP_ALG_TYPE_AES_CTR 2
281 
282 struct roc_se_ctx {
283 	/* Below fields are accessed by sw */
284 	uint64_t enc_cipher : 8;
285 	uint64_t hash_type : 8;
286 	uint64_t mac_len : 8;
287 	uint64_t auth_key_len : 8;
288 	uint64_t fc_type : 4;
289 	uint64_t hmac : 1;
290 	uint64_t zsk_flags : 3;
291 	uint64_t k_ecb : 1;
292 	uint64_t pdcp_alg_type : 2;
293 	uint64_t rsvd : 21;
294 	union cpt_inst_w4 template_w4;
295 	/* Below fields are accessed by hardware */
296 	union {
297 		struct roc_se_context fctx;
298 		struct roc_se_zuc_snow3g_ctx zs_ctx;
299 		struct roc_se_kasumi_ctx k_ctx;
300 	} se_ctx;
301 	uint8_t *auth_key;
302 };
303 
304 int __roc_api roc_se_auth_key_set(struct roc_se_ctx *se_ctx,
305 				  roc_se_auth_type type, const uint8_t *key,
306 				  uint16_t key_len, uint16_t mac_len);
307 
308 int __roc_api roc_se_ciph_key_set(struct roc_se_ctx *se_ctx,
309 				  roc_se_cipher_type type, const uint8_t *key,
310 				  uint16_t key_len, uint8_t *salt);
311 
312 void __roc_api roc_se_ctx_swap(struct roc_se_ctx *se_ctx);
313 #endif /* __ROC_SE_H__ */
314