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Searched refs:reset (Results 1 – 25 of 134) sorted by relevance

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/dpdk/drivers/net/hns3/
H A Dhns3_intr.c2482 reset_string[hw->reset.level], hw->reset.stage); in hns3_wait_callback()
2603 hw->reset.attempts++; in hns3_reset_err_handle()
2605 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending); in hns3_reset_err_handle()
2627 reset_string[hw->reset.level], hw->reset.stats.fail_cnt, in hns3_reset_err_handle()
2628 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt, in hns3_reset_err_handle()
2629 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt, in hns3_reset_err_handle()
2630 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt, in hns3_reset_err_handle()
2747 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt, in hns3_reset_post()
2748 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt, in hns3_reset_post()
2749 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt, in hns3_reset_post()
[all …]
H A Dhns3_ethdev_vf.c632 hw->reset.stats.global_cnt++; in hns3vf_check_event_cause()
1671 rte_free(hw->reset.wait_data); in hns3vf_dev_close()
1843 enum hns3_reset_level reset; in hns3vf_is_reset_pending() local
1861 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); in hns3vf_is_reset_pending()
1862 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET && in hns3vf_is_reset_pending()
1863 hw->reset.level < reset) { in hns3vf_is_reset_pending()
1888 if (hw->reset.attempts) in hns3vf_wait_hardware_ready()
1968 hw->reset.mbuf_deferred_free = true; in hns3vf_stop_service()
2134 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) in hns3vf_get_reset_level()
2343 hw->reset.ops = &hns3vf_reset_ops; in hns3vf_dev_init()
[all …]
H A Dhns3_ethdev.c131 hw->reset.stats.imp_cnt++; in hns3_proc_imp_reset_event()
151 hw->reset.stats.global_cnt++; in hns3_proc_global_reset_event()
5574 switch (hw->reset.level) { in is_pf_reset_done()
5590 hw->reset.level); in is_pf_reset_done()
5607 reset = hns3_get_reset_level(hns, &hw->reset.pending); in hns3_is_reset_pending()
5608 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && in hns3_is_reset_pending()
5609 hw->reset.level < reset) { in hns3_is_reset_pending()
5613 reset = hns3_get_reset_level(hns, &hw->reset.request); in hns3_is_reset_pending()
5614 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && in hns3_is_reset_pending()
5615 hw->reset.level < reset) { in hns3_is_reset_pending()
[all …]
H A Dhns3_cmd.c201 __atomic_store_n(&hw->reset.disable_cmd, 1, in hns3_cmd_csq_clean()
316 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) { in hns3_cmd_poll_reply()
363 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) in hns3_cmd_send()
712 __atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED); in hns3_cmd_init()
755 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); in hns3_cmd_init()
784 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); in hns3_cmd_uninit()
H A Dhns3_mbx.c80 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) { in hns3_get_mbx_resp()
250 hns3_atomic_set_bit(reset_level, &hw->reset.pending); in hns3_handle_asserting_reset()
253 hw->reset.stats.request_cnt++; in hns3_handle_asserting_reset()
481 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) { in hns3_dev_handle_mbx_msg()
/dpdk/doc/guides/tools/
H A Dproc_info.rst21 --stats-reset | --xstats-reset] [ --show-port | --show-tm | --show-crypto |
36 **--stats-reset**
37 The stats-reset parameter controls the resetting of generic port statistics. If
38 no port mask is specified, the generic stats are reset for all DPDK ports.
40 **--xstats-reset**
41 The xstats-reset parameter controls the resetting of extended port statistics.
42 If no port mask is specified xstats are reset for all DPDK ports.
/dpdk/drivers/net/sfc/
H A Dsfc_mae_counter.c122 __atomic_store(&p->reset.pkts_bytes.int128, in sfc_mae_counter_enable()
137 p->reset.pkts, p->reset.bytes); in sfc_mae_counter_enable()
178 p->reset.pkts, p->reset.bytes); in sfc_mae_counter_disable()
966 data->hits = value.pkts - p->reset.pkts; in sfc_mae_counter_get()
974 data->bytes = value.bytes - p->reset.bytes; in sfc_mae_counter_get()
977 if (data->reset != 0) { in sfc_mae_counter_get()
981 p->reset.pkts = value.pkts; in sfc_mae_counter_get()
982 p->reset.bytes = value.bytes; in sfc_mae_counter_get()
/dpdk/drivers/event/sw/
H A Dsw_evdev_xstats.c448 uint64_t values[], unsigned int n, const uint32_t reset, in sw_xstats_update() argument
498 if (xs->reset_allowed && reset) in sw_xstats_update()
515 const uint32_t reset = 0; in sw_xstats_get() local
518 reset, ret_n_lt_stats); in sw_xstats_get()
561 const uint32_t reset = 1; in sw_xstats_reset_queue() local
567 reset, ret_n_lt_stats); in sw_xstats_reset_queue()
582 const uint32_t reset = 1; in sw_xstats_reset_port() local
591 reset, ret_n_lt_stats); in sw_xstats_reset_port()
/dpdk/drivers/vdpa/mlx5/
H A Dmlx5_vdpa_virtq.c606 .value = attr->received_desc - virtq->reset.received_desc, in mlx5_vdpa_virtq_stats_get()
612 .value = attr->completed_desc - virtq->reset.completed_desc, in mlx5_vdpa_virtq_stats_get()
618 .value = attr->bad_desc_errors - virtq->reset.bad_desc_errors, in mlx5_vdpa_virtq_stats_get()
624 .value = attr->exceed_max_chain - virtq->reset.exceed_max_chain, in mlx5_vdpa_virtq_stats_get()
630 .value = attr->invalid_buffer - virtq->reset.invalid_buffer, in mlx5_vdpa_virtq_stats_get()
636 .value = attr->error_cqes - virtq->reset.error_cqes, in mlx5_vdpa_virtq_stats_get()
650 &virtq->reset); in mlx5_vdpa_virtq_stats_reset()
/dpdk/drivers/event/dlb2/
H A Ddlb2_xstats.c721 uint64_t values[], unsigned int n, const uint32_t reset) in dlb2_xstats_update() argument
779 if (xs->reset_allowed && reset) in dlb2_xstats_update()
797 const uint32_t reset = 0; in dlb2_eventdev_xstats_get() local
800 reset); in dlb2_eventdev_xstats_get()
881 const uint32_t reset = 1; in dlb2_xstats_reset_queue() local
887 reset); in dlb2_xstats_reset_queue()
903 const uint32_t reset = 1; in dlb2_xstats_reset_port() local
911 reset); in dlb2_xstats_reset_port()
/dpdk/drivers/net/thunderx/base/
H A Dnicvf_hw_defs.h1039 uint64_t reset:1; member
1053 uint64_t reset:1;
1067 uint64_t reset:1; member
1079 uint64_t reset:1;
1093 uint64_t reset:1; member
1109 uint64_t reset:1;
/dpdk/drivers/net/ice/
H A Dice_dcf.c367 int i, reset; in ice_dcf_check_reset_done() local
370 reset = IAVF_READ_REG(avf, IAVF_VFGEN_RSTAT) & in ice_dcf_check_reset_done()
372 reset = reset >> IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT; in ice_dcf_check_reset_done()
374 if (reset == VIRTCHNL_VFR_VFACTIVE || in ice_dcf_check_reset_done()
375 reset == VIRTCHNL_VFR_COMPLETED) in ice_dcf_check_reset_done()
/dpdk/doc/guides/howto/
H A Dlm_virtio_vhost_user.rst78 For Fortville and Niantic NIC's reset SRIOV and run the
159 For Fortville and Niantic NIC's reset SRIOV, and run
263 # This script is run on the host 10.237.212.46 to reset SRIOV
339 # This script is run on the host 10.237.212.131 to reset SRIOV
/dpdk/lib/timer/
H A Drte_timer.h81 uint64_t reset; /**< Number of success calls to rte_timer_reset(). */ member
H A Drte_timer.c500 __TIMER_STAT_ADD(priv_timer, reset, 1); in __rte_timer_reset()
1049 sum.reset += priv_timer[lcore_id].stats.reset; in __rte_timer_dump_stats()
1055 fprintf(f, " reset = %"PRIu64"\n", sum.reset); in __rte_timer_dump_stats()
/dpdk/doc/guides/sample_app_ug/
H A Dl2_forward_cat.rst28 By default, after reset, all CPU cores are assigned to COS 0 and all classes
128 To reset or list CAT configuration and control CDP please use ``pqos`` tool
140 to reset CAT configuration:
/dpdk/drivers/net/bnxt/tf_ulp/
H A Dulp_fc_mgr.c351 if (qcount->reset) { in ulp_fc_tf_flow_stat_get()
749 if (count->reset) { in ulp_fc_mgr_query_count_get()
760 count->reset); in ulp_fc_mgr_query_count_get()
/dpdk/drivers/net/cxgbe/base/
H A Dcommon.h342 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
344 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
345 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
/dpdk/doc/guides/rel_notes/
H A Drelease_2_2.rst74 * Check more errors for ESB2 init and reset
106 * Increased PF reset max loop limit
245 * **e1000/base: Increased timeout of reset check.**
302 * **e1000/base: Fix reset of DH89XXCC SGMII.**
474 * Some (possibly all) VF drivers (e.g. i40evf) do not handle any PF reset
476 after a PF reset in the host side. The workaround is to avoid triggering any
477 PF reset events/requests on the host side.
/dpdk/doc/guides/prog_guide/
H A Dpoll_mode_drv.rst272 the application may want to reset back to an initial state
594 Sometimes a port has to be reset passively. For example when a PF is
595 reset, all its VFs should also be reset by the application to make them
597 to trigger a port reset. Normally, a DPDK application would invokes this
602 events. When a PMD needs to trigger a reset, it can trigger an
608 For example when PF is reset, the PF sends a message to notify VFs of
612 This means that a PF reset triggers an RTE_ETH_EVENT_INTR_RESET
615 the application to handle all operations the VF reset requires including
619 some hardware reset operations through calling dev_unint() and
624 the application to handle reset event. It is duty of application to
/dpdk/doc/guides/dmadevs/
H A Dioat.rst100 to reset the device and continue processing operations. This function will also gather the status
115 which operation failed and reset the device to continue processing operations:
/dpdk/drivers/raw/ioat/
H A Ddpdk_idxd_cfg.py121 if parsed_args.reset:
/dpdk/drivers/dma/idxd/
H A Ddpdk_idxd_cfg.py121 if parsed_args.reset:
/dpdk/doc/guides/regexdevs/
H A Dfeatures_overview.rst40 Support PCRE match point reset directive.
/dpdk/drivers/crypto/virtio/
H A Dvirtio_pci.h156 void (*reset)(struct virtio_crypto_hw *hw); member

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