Home
last modified time | relevance | path

Searched refs:reg_offset (Results 1 – 21 of 21) sorted by relevance

/dpdk/drivers/net/qede/base/
H A Decore_init_fw_funcs.c1118 u32 ctrl, inc_val, reg_offset; in ecore_init_nig_lb_rl() local
1170 tc++, reg_offset += 4) { in ecore_init_nig_lb_rl()
1187 reg_offset, inc_val); in ecore_init_nig_lb_rl()
1195 reg_offset, ctrl); in ecore_init_nig_lb_rl()
1381 reg_offset, full_xoff_th); in ecore_init_brb_ram()
1384 reg_offset, full_xon_th); in ecore_init_brb_ram()
1387 reg_offset, pause_xoff_th); in ecore_init_brb_ram()
1390 reg_offset, pause_xon_th); in ecore_init_brb_ram()
1397 reg_offset, full_xoff_th); in ecore_init_brb_ram()
1400 reg_offset, full_xon_th); in ecore_init_brb_ram()
[all …]
H A Decore_cxt.c1998 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; in ecore_cxt_dynamic_ilt_alloc() local
2069 reg_offset = PSWRQ2_REG_ILT_MEMORY + in ecore_cxt_dynamic_ilt_alloc()
2081 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), in ecore_cxt_dynamic_ilt_alloc()
2101 u32 reg_offset, elem_size, hw_p_size, elems_per_p; in ecore_cxt_free_ilt_range() local
2163 reg_offset = PSWRQ2_REG_ILT_MEMORY + in ecore_cxt_free_ilt_range()
2172 reg_offset, in ecore_cxt_free_ilt_range()
H A Decore_hsi_debug_tools.h564 u16 reg_offset; member
/dpdk/drivers/crypto/ccp/
H A Dccp_dev.h166 #define CCP_READ_REG(hw_addr, reg_offset) \ argument
167 ccp_pci_reg_read(hw_addr, reg_offset)
169 #define CCP_WRITE_REG(hw_addr, reg_offset, value) \ argument
170 ccp_pci_reg_write(hw_addr, reg_offset, value)
/dpdk/drivers/net/hns3/
H A Dhns3_regs.c296 uint32_t reg_offset; in hns3_direct_access_regs() local
319 reg_offset = hns3_get_tqp_reg_offset(j); in hns3_direct_access_regs()
322 ring_reg_addrs[i] + reg_offset); in hns3_direct_access_regs()
328 reg_offset = hns3_get_tqp_intr_reg_offset(j); in hns3_direct_access_regs()
331 reg_offset); in hns3_direct_access_regs()
H A Dhns3_ethdev_dump.c325 uint32_t reg_offset; in get_queue_enable_state() local
331 reg_offset = hns3_get_tqp_reg_offset(i); in get_queue_enable_state()
332 state = hns3_read_dev(hw, reg_offset + HNS3_RING_EN_REG); in get_queue_enable_state()
334 state = state && hns3_read_dev(hw, reg_offset + in get_queue_enable_state()
H A Dhns3_stats.c839 uint32_t reg_offset; in hns3_queue_stats_get() local
845 reg_offset = hns3_get_tqp_reg_offset(j); in hns3_queue_stats_get()
847 reg_offset + hns3_rx_queue_strings[i].offset); in hns3_queue_stats_get()
856 reg_offset = hns3_get_tqp_reg_offset(j); in hns3_queue_stats_get()
858 reg_offset + hns3_tx_queue_strings[i].offset); in hns3_queue_stats_get()
H A Dhns3_rxtx.c371 uint32_t reg_offset; in hns3_stop_unused_queue() local
374 reg_offset = queue_type == HNS3_RING_TYPE_TX ? in hns3_stop_unused_queue()
376 reg = hns3_read_reg(tqp_base, reg_offset); in hns3_stop_unused_queue()
378 hns3_write_reg(tqp_base, reg_offset, reg); in hns3_stop_unused_queue()
942 uint32_t reg_offset; in hns3_get_tqp_intr_reg_offset() local
946 reg_offset = HNS3_TQP_INTR_REG_BASE + in hns3_get_tqp_intr_reg_offset()
949 reg_offset = HNS3_TQP_INTR_EXT_REG_BASE + in hns3_get_tqp_intr_reg_offset()
955 return reg_offset; in hns3_get_tqp_intr_reg_offset()
1813 uint32_t reg_offset; in hns3_get_tqp_reg_offset() local
1819 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET + in hns3_get_tqp_reg_offset()
[all …]
/dpdk/drivers/net/ixgbe/
H A Dixgbe_pf.c381 uint32_t reg_offset, vf_shift; in ixgbe_vf_reset_msg() local
388 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; in ixgbe_vf_reset_msg()
391 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); in ixgbe_vf_reset_msg()
393 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); in ixgbe_vf_reset_msg()
405 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); in ixgbe_vf_reset_msg()
407 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); in ixgbe_vf_reset_msg()
410 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); in ixgbe_vf_reset_msg()
412 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); in ixgbe_vf_reset_msg()
/dpdk/drivers/net/txgbe/
H A Dtxgbe_pf.c373 uint32_t reg_offset, vf_shift; in txgbe_vf_reset_msg() local
380 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; in txgbe_vf_reset_msg()
383 reg = rd32(hw, TXGBE_POOLTXENA(reg_offset)); in txgbe_vf_reset_msg()
385 wr32(hw, TXGBE_POOLTXENA(reg_offset), reg); in txgbe_vf_reset_msg()
396 reg = rd32(hw, TXGBE_POOLRXENA(reg_offset)); in txgbe_vf_reset_msg()
398 wr32(hw, TXGBE_POOLRXENA(reg_offset), reg); in txgbe_vf_reset_msg()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_mbx.c567 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
576 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); in ixgbe_check_for_rst_pf()
582 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); in ixgbe_check_for_rst_pf()
590 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_mbx.c516 u32 reg_offset = (vf_number < 32) ? 0 : 1; in txgbe_check_for_rst_pf() local
521 vflre = rd32(hw, TXGBE_FLRVFE(reg_offset)); in txgbe_check_for_rst_pf()
524 wr32(hw, TXGBE_FLRVFEC(reg_offset), (1 << vf_shift)); in txgbe_check_for_rst_pf()
/dpdk/drivers/common/cnxk/
H A Droc_ree.c186 msg->reg_offset = reg; in roc_ree_af_reg_read()
221 msg->reg_offset = reg; in roc_ree_af_reg_write()
H A Droc_cpt_debug.c54 msg->reg_offset = reg; in cpt_af_reg_read()
H A Droc_mbox.h1375 uint64_t __io reg_offset; member
1580 uint64_t __io reg_offset; member
/dpdk/drivers/net/i40e/
H A Di40e_ethdev.c11125 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) || in i40e_valid_regs()
11126 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) || in i40e_valid_regs()
11127 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) || in i40e_valid_regs()
11128 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) || in i40e_valid_regs()
11129 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) || in i40e_valid_regs()
11130 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) || in i40e_valid_regs()
11131 (reg_offset >= 0x265c00 && reg_offset <= 0x266000))) in i40e_valid_regs()
11162 ptr_data[reg_offset >> 2] = in i40e_get_regs()
11179 ptr_data[reg_offset >> 2] = 0; in i40e_get_regs()
11181 ptr_data[reg_offset >> 2] = in i40e_get_regs()
[all …]
/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c3962 int reg_offset; in bnx2x_attn_int_deasserted2() local
4038 val = REG_RD(sc, reg_offset); in bnx2x_attn_int_deasserted2()
4040 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted2()
4052 int reg_offset; in bnx2x_attn_int_deasserted1() local
4068 val = REG_RD(sc, reg_offset); in bnx2x_attn_int_deasserted1()
4070 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted1()
4082 int reg_offset; in bnx2x_attn_int_deasserted0() local
4089 val = REG_RD(sc, reg_offset); in bnx2x_attn_int_deasserted0()
4091 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted0()
4109 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted0()
[all …]
H A Decore_sp.c719 uint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM : in ecore_set_mac_in_nig() local
733 reg_offset += 8 * index; in ecore_set_mac_in_nig()
739 ECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2); in ecore_set_mac_in_nig()
/dpdk/drivers/net/e1000/base/
H A De1000_82575.c2093 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2097 reg_offset = E1000_DTXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2101 reg_offset = E1000_TXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2107 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2119 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
/dpdk/drivers/net/ngbe/base/
H A Dngbe_regs.h259 #define NGBE_PHY_CONFIG(reg_offset) (0x014000 + (reg_offset) * 4) argument
/dpdk/drivers/net/qede/
H A Dqede_debug.c1984 u32 offset = 0, reg_offset = 0; in qed_grc_dump_reg_entry_skip() local
1991 while (reg_offset < total_len) { in qed_grc_dump_reg_entry_skip()
1993 total_len - reg_offset); in qed_grc_dump_reg_entry_skip()
2000 reg_offset += curr_len; in qed_grc_dump_reg_entry_skip()
2003 if (reg_offset < total_len) { in qed_grc_dump_reg_entry_skip()
2008 reg_offset += curr_len; in qed_grc_dump_reg_entry_skip()
3582 rule->reg_offset; in qed_idle_chk_dump_failure()
3723 rule->reg_offset; in qed_idle_chk_dump_rule_entries()