| /dpdk/drivers/crypto/ccp/ |
| H A D | ccp_dev.c | 537 cmd_q->reg_base = (uint8_t *)vaddr + in ccp_add_device()
554 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_add_device()
558 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INT_ENABLE_BASE, 0x00); in ccp_add_device()
559 CCP_READ_REG(cmd_q->reg_base, CMD_Q_INT_STATUS_BASE); in ccp_add_device()
560 CCP_READ_REG(cmd_q->reg_base, CMD_Q_STATUS_BASE); in ccp_add_device()
563 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INTERRUPT_STATUS_BASE, in ccp_add_device()
571 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, in ccp_add_device()
573 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_HEAD_LO_BASE, in ccp_add_device()
578 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_add_device()
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| H A D | ccp_crypto.c | 1647 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_hmac()
1733 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_hmac()
1827 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha()
1912 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha3_hmac()
1988 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha3_hmac()
2060 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha3()
2420 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_3des()
2506 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_aes_gcm()
2548 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_aes_gcm()
2593 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_aes_gcm()
[all …]
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| H A D | ccp_dev.h | 204 void *reg_base; member
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| /dpdk/drivers/common/cnxk/ |
| H A D | roc_mbox.c | 38 mbox->reg_base = 0; in mbox_fini()
64 mbox_init(struct mbox *mbox, uintptr_t hwbase, uintptr_t reg_base, in mbox_init() argument
72 mbox->reg_base = reg_base; in mbox_init()
230 plt_write64(1, (volatile void *)(mbox->reg_base + in mbox_msg_send()
273 reg_addr = mbox->reg_base + mbox->intr_offset; in mbox_poll()
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| H A D | roc_mbox_priv.h | 58 uintptr_t reg_base; /* CSR base for this dev */ member
74 int mbox_init(struct mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
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| /dpdk/drivers/net/thunderx/base/ |
| H A D | nicvf_hw.h | 114 nicvf_addr_write(nic->reg_base + offset, val); in nicvf_reg_write()
120 return nicvf_addr_read(nic->reg_base + offset); in nicvf_reg_read()
126 return nic->reg_base + (qidx << NIC_Q_NUM_SHIFT); in nicvf_qset_base()
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| /dpdk/drivers/crypto/octeontx/ |
| H A D | otx_cryptodev_hw_access.h | 37 #define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base)
85 uint8_t *reg_base; member
162 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
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| H A D | otx_cryptodev_hw_access.c | 369 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name) in otx_cpt_hw_init() argument
374 cptvf->reg_base = reg_base; in otx_cpt_hw_init()
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| H A D | otx_cryptodev_ops.c | 1053 void *reg_base; in otx_cpt_dev_create() local
1078 reg_base = pdev->mem_resource[0].addr; in otx_cpt_dev_create()
1079 if (!reg_base) { in otx_cpt_dev_create()
1085 ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name); in otx_cpt_dev_create()
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| /dpdk/drivers/compress/octeontx/ |
| H A D | otx_zip.c | 102 void *reg_base = qp->vf->vbar0; in zipvf_push_command() local
138 zip_reg_write64(reg_base, ZIP_VQ_DOORBELL, dbell.u); in zipvf_push_command()
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| /dpdk/drivers/event/skeleton/ |
| H A D | skeleton_eventdev.h | 24 uintptr_t reg_base; member
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| H A D | skeleton_eventdev.c | 363 skel->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; in skeleton_eventdev_init()
364 if (!skel->reg_base) { in skeleton_eventdev_init()
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| /dpdk/drivers/net/thunderx/ |
| H A D | nicvf_struct.h | 84 uintptr_t reg_base; member
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| H A D | nicvf_ethdev.c | 2155 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; in nicvf_eth_dev_init()
2156 if (!nic->reg_base) { in nicvf_eth_dev_init()
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| /dpdk/drivers/net/bnxt/ |
| H A D | bnxt_ethdev.c | 3430 uint32_t reg_base = *reg_arr & 0xfffff000; in bnxt_map_regs() local
3435 if ((reg_arr[i] & 0xfffff000) != reg_base) in bnxt_map_regs()
3439 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); in bnxt_map_regs()
4121 uint32_t reg_base = 0xffffffff; in bnxt_map_fw_health_status_regs() local
4131 if (reg_base == 0xffffffff) in bnxt_map_fw_health_status_regs()
4132 reg_base = reg & 0xfffff000; in bnxt_map_fw_health_status_regs()
4133 if ((reg & 0xfffff000) != reg_base) in bnxt_map_fw_health_status_regs()
4143 if (reg_base == 0xffffffff) in bnxt_map_fw_health_status_regs()
4146 rte_write32(reg_base, (uint8_t *)bp->bar0 + in bnxt_map_fw_health_status_regs()
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