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Searched refs:readq (Results 1 – 15 of 15) sorted by relevance

/dpdk/drivers/raw/ifpga/base/
H A Difpga_fme_error.c14 fme_error0.csr = readq(&fme_err->fme_err); in fme_err_get_errors()
27 fme_first_err.csr = readq(&fme_err->fme_first_err); in fme_err_get_first_error()
40 fme_next_err.csr = readq(&fme_err->fme_next_err); in fme_err_get_next_error()
68 header.csr = readq(&fme_err->header); in fme_err_get_revision()
81 pcie0_err.csr = readq(&fme_err->pcie0_err); in fme_err_get_pcie0_errors()
98 pcie0_err.csr = readq(&fme_err->pcie0_err); in fme_err_set_pcie0_errors()
118 pcie1_err.csr = readq(&fme_err->pcie1_err); in fme_err_get_pcie1_errors()
135 pcie1_err.csr = readq(&fme_err->pcie1_err); in fme_err_set_pcie1_errors()
155 ras_nonfaterr.csr = readq(&fme_err->ras_nonfaterr); in fme_err_get_nonfatal_errors()
260 *val = readq(&fme_err->seu_emr_h); in fme_err_get_seu_emr()
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H A Difpga_port.c59 header.csr = readq(&port_hdr->header); in port_get_revision()
74 capability.csr = readq(&port_hdr->capability); in port_get_portidx()
88 control.csr = readq(&port_hdr->control); in port_get_latency_tolerance()
103 status.csr = readq(&port_hdr->status); in port_get_ap1_event()
120 status.csr = readq(&port_hdr->status); in port_set_ap1_event()
137 status.csr = readq(&port_hdr->status); in port_get_ap2_event()
154 status.csr = readq(&port_hdr->status); in port_set_ap2_event()
171 status.csr = readq(&port_hdr->status); in port_get_power_state()
187 *val = readq(&port_hdr->user_clk_freq_cmd0); in port_get_userclk_freqcmd()
215 *val = readq(&port_hdr->user_clk_freq_cmd1); in port_get_userclk_freqcntrcmd()
[all …]
H A Difpga_fme.c86 header.csr = readq(&fme_hdr->header); in fme_hdr_get_revision()
98 fme_capability.csr = readq(&fme_hdr->capability); in fme_hdr_get_ports_num()
111 pt.csr = readq(&fme_hdr->port[port]); in fme_hdr_get_port_type()
128 fme_capability.csr = readq(&fme_hdr->capability); in fme_hdr_get_cache_size()
164 *bitstream_id = readq(&fme_hdr->bitstream_id); in fme_hdr_get_bitstream_id()
240 tmp_threshold.csr = readq(&thermal->threshold); in fme_thermal_set_threshold1()
289 tmp_threshold.csr = readq(&thermal->threshold); in fme_thermal_set_threshold2()
420 header.csr = readq(&fme_thermal->header); in fme_thermal_get_revision()
522 pm_status.csr = readq(&fme_power->status); in fme_pwr_get_consumed()
640 pm_status.csr = readq(&fme_power->status); in fme_pwr_get_rtl()
[all …]
H A Difpga_fme_iperf.c29 header.csr = readq(&iperf->header); in fme_iperf_get_revision()
42 ctl.csr = readq(&iperf->ch_ctl); in fme_iperf_get_cache_freeze()
58 ctl.csr = readq(&iperf->ch_ctl); in fme_iperf_set_cache_freeze()
81 ctl.csr = readq(&iperf->ch_ctl); in read_cache_counter()
96 ctr0.csr = readq(&iperf->ch_ctr0); in read_cache_counter()
97 ctr1.csr = readq(&iperf->ch_ctr1); in read_cache_counter()
132 ctl.csr = readq(&iperf->vtd_ctl); in fme_iperf_get_vtd_freeze()
149 ctl.csr = readq(&iperf->vtd_ctl); in fme_iperf_set_vtd_freeze()
221 ctl.csr = readq(&iperf->vtd_ctl); in read_iommu_counter()
234 ctr.csr = readq(&iperf->vtd_ctr); in read_iommu_counter()
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H A Difpga_fme_pr.c15 fme_pr_status.csr = readq(&fme_pr->ccip_fme_pr_status); in pr_err_handle()
19 err_code = readq(&fme_pr->ccip_fme_pr_err); in pr_err_handle()
48 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
61 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
99 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write()
106 fme_pr_status.csr = readq(&fme_pr->ccip_fme_pr_status); in fme_pr_write()
120 fme_pr_status.csr = readq(&fme_pr->ccip_fme_pr_status); in fme_pr_write()
160 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_complete()
254 fme_capability.csr = readq(&fme_hdr->capability); in fme_pr()
335 fme_pr_header.csr = readq(&fme_pr->header); in fme_pr_mgmt_init()
H A Difpga_feature_dev.c30 control.csr = readq(&port_hdr->control); in __fpga_port_enable()
48 control.csr = readq(&port_hdr->control); in __fpga_port_disable()
80 guidl = readq(&port_hdr->afu_header.guid.b[0]); in fpga_get_afu_uuid()
81 guidh = readq(&port_hdr->afu_header.guid.b[8]); in fpga_get_afu_uuid()
101 guidl = readq(&fme_pr->fme_pr_intfc_id_l); in fpga_get_pr_uuid()
102 guidh = readq(&fme_pr->fme_pr_intfc_id_h); in fpga_get_pr_uuid()
156 status.csr = readq(&port_hdr->status); in port_err_clear()
171 mask.csr = readq(&port_err->port_error); in port_err_clear()
176 first.csr = readq(&port_err->port_first_error); in port_err_clear()
198 error.csr = readq(&port_err->port_error); in port_clear_error()
H A Difpga_fme_dperf.c16 clk.afu_interf_clock = readq(&dperf->clk); in fme_dperf_get_clock()
29 header.csr = readq(&dperf->header); in fme_dperf_get_revision()
42 ctl.csr = readq(&dperf->fab_ctl); in fabric_pobj_is_enabled()
66 ctl.csr = readq(&dperf->fab_ctl); in read_fabric_counter()
79 ctr.csr = readq(&dperf->fab_ctr); in read_fabric_counter()
138 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_set_fab_port_enable()
159 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_get_fab_freeze()
176 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_set_fab_freeze()
H A Difpga_enumerate.c35 header.csr = readq(start); in feature_revision()
44 header.csr = readq(start); in feature_size()
54 header.csr = readq(start); in feature_id()
172 capability.csr = readq(&port_hdr->capability); in parse_feature_port_uafu()
211 header.csr = readq(&afu_hdr->csr); in parse_feature_afus()
382 header.csr = readq(hdr); in parse_feature_fiu()
399 fiu_header.csr = readq(&fiu_hdr->csr); in parse_feature_fiu()
493 header.csr = readq(hdr); in parse_feature_private()
513 header.csr = readq(hdr); in parse_feature()
548 header.csr = readq(hdr); in parse_feature_list()
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H A Difpga_port_error.c14 header.csr = readq(&port_err->header); in port_err_get_revision()
27 error.csr = readq(&port_err->port_error); in port_err_get_errors()
40 first_error.csr = readq(&port_err->port_first_error); in port_err_get_first_error()
55 malreq0.header_lsb = readq(&port_err->malreq0); in port_err_get_first_malformed_req_lsb()
70 malreq1.header_msb = readq(&port_err->malreq1); in port_err_get_first_malformed_req_msb()
H A Difpga_compat.h26 #define readq(addr) opae_readq(addr) macro
44 value.csr = readq(_reg_addr); \
/dpdk/drivers/bus/fslmc/mc/
H A Dfsl_mc_sys.h24 #define ioread64(_p) readq(_p)
42 #define readq(c) \ macro
48 #define ioread64(_p) readq(_p)
/dpdk/drivers/common/iavf/
H A Diavf_osdep.h108 readq(volatile void *addr) in readq() function
122 #define rd64(a, reg) readq((a)->hw_addr + (reg))
/dpdk/drivers/net/enic/base/
H A Dvnic_dev.h22 #ifndef readq
23 static inline uint64_t readq(void __iomem *reg) in readq() function
H A Dvnic_dev.c349 err = -(int)readq(&devcmd->args[0]); in _vnic_dev_cmd()
362 vdev->args[i] = readq(&devcmd->args[i]); in _vnic_dev_cmd()
/dpdk/drivers/net/ice/base/
H A Dice_osdep.h115 readq(volatile void *addr) in readq() function
129 #define rd64(a, reg) readq((a)->hw_addr + (reg))