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Searched refs:rd32 (Results 1 – 25 of 44) sorted by relevance

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/dpdk/drivers/net/ngbe/base/
H A Dngbe_hw.c215 rd32(hw, NGBE_PBRXLNKXON); in ngbe_clear_hw_cntrs()
216 rd32(hw, NGBE_PBRXLNKXOFF); in ngbe_clear_hw_cntrs()
217 rd32(hw, NGBE_PBTXLNKXON); in ngbe_clear_hw_cntrs()
218 rd32(hw, NGBE_PBTXLNKXOFF); in ngbe_clear_hw_cntrs()
221 rd32(hw, NGBE_DMARXPKT); in ngbe_clear_hw_cntrs()
222 rd32(hw, NGBE_DMATXPKT); in ngbe_clear_hw_cntrs()
237 rd32(hw, NGBE_MACTXOCTL); in ngbe_clear_hw_cntrs()
254 rd32(hw, NGBE_MACRXJABBER); in ngbe_clear_hw_cntrs()
257 rd32(hw, NGBE_LSECTX_UTPKT); in ngbe_clear_hw_cntrs()
262 rd32(hw, NGBE_LSECRX_UTPKT); in ngbe_clear_hw_cntrs()
[all …]
H A Dngbe_eeprom.c38 eec = rd32(hw, NGBE_SPISTAT); in ngbe_init_eeprom_params()
79 swsm = rd32(hw, NGBE_SWSEM); in ngbe_get_eeprom_semaphore()
103 swsm = rd32(hw, NGBE_SWSEM); in ngbe_get_eeprom_semaphore()
119 swsm = rd32(hw, NGBE_MNGSWSYNC); in ngbe_get_eeprom_semaphore()
277 eeprom_cksum_devcap = rd32(hw, NGBE_CALSUM_CAP_STATUS); in ngbe_validate_eeprom_checksum_em()
278 hw->rom.saved_version = rd32(hw, NGBE_EEPROM_VERSION_STORE_REG); in ngbe_validate_eeprom_checksum_em()
H A Dngbe_regs.h1365 rd32(struct ngbe_hw *hw, u32 reg) in rd32() function
1383 u32 val = rd32(hw, reg); in rd32m()
1391 u32 val = rd32(hw, reg); in wr32m()
1399 u64 lsb = rd32(hw, reg); in rd64()
1400 u64 msb = rd32(hw, reg + 4); in rd64()
1425 all |= rd32(hw, reg); in po32m()
1440 #define ngbe_flush(hw) rd32(hw, 0x00100C)
1443 rd32((hw), (reg) + ((idx) << 2)))
1448 rd32((hw), reg); \
1466 data = rd32(hw, NGBE_XPCS_IDADATA); in rd32_epcs()
[all …]
H A Dngbe_mbx.c114 u32 mbvficr = rd32(hw, NGBE_MBVFICR); in ngbe_check_for_bit_pf()
177 vflre = rd32(hw, NGBE_FLRVFE); in ngbe_check_for_rst_pf()
203 p2v_mailbox = rd32(hw, NGBE_MBCTL(vf_number)); in ngbe_obtain_mbx_lock_pf()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_hw.c325 rd32(hw, TXGBE_DMARXPKT); in txgbe_clear_hw_cntrs()
326 rd32(hw, TXGBE_DMATXPKT); in txgbe_clear_hw_cntrs()
361 rd32(hw, TXGBE_FCOECRC); in txgbe_clear_hw_cntrs()
362 rd32(hw, TXGBE_FCOELAST); in txgbe_clear_hw_cntrs()
363 rd32(hw, TXGBE_FCOERPDC); in txgbe_clear_hw_cntrs()
364 rd32(hw, TXGBE_FCOEPRC); in txgbe_clear_hw_cntrs()
365 rd32(hw, TXGBE_FCOEPTC); in txgbe_clear_hw_cntrs()
366 rd32(hw, TXGBE_FCOEDWRC); in txgbe_clear_hw_cntrs()
367 rd32(hw, TXGBE_FCOEDWTC); in txgbe_clear_hw_cntrs()
371 rd32(hw, TXGBE_FDIRMISS); in txgbe_clear_hw_cntrs()
[all …]
H A Dtxgbe_dcb.c53 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); in txgbe_dcb_pfc_enable()
56 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); in txgbe_dcb_pfc_enable()
67 uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i)); in txgbe_dcb_pfc_enable()
90 uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i)); in txgbe_dcb_pfc_enable()
134 fcrth = rd32(hw, TXGBE_PBRXSIZE(tc_num)) - 32; in txgbe_dcb_pfc_enable()
H A Dtxgbe_eeprom.c39 eec = rd32(hw, TXGBE_SPISTAT); in txgbe_init_eeprom_params()
85 swsm = rd32(hw, TXGBE_SWSEM); in txgbe_get_eeprom_semaphore()
109 swsm = rd32(hw, TXGBE_SWSEM); in txgbe_get_eeprom_semaphore()
125 swsm = rd32(hw, TXGBE_MNGSWSYNC); in txgbe_get_eeprom_semaphore()
H A Dtxgbe_regs.h1807 rd32(struct txgbe_hw *hw, u32 reg) in rd32() function
1825 u32 val = rd32(hw, reg); in rd32m()
1833 u32 val = rd32(hw, reg); in wr32m()
1841 u64 lsb = rd32(hw, reg); in rd64()
1842 u64 msb = rd32(hw, reg + 4); in rd64()
1867 all |= rd32(hw, reg); in po32m()
1882 #define txgbe_flush(hw) rd32(hw, 0x00100C)
1885 rd32((hw), (reg) + ((idx) << 2)))
1895 rd32((hw), reg); \
1913 data = rd32(hw, TXGBE_XPCS_IDADATA); in rd32_epcs()
[all …]
H A Dtxgbe_mbx.c236 u32 v2p_mailbox = rd32(hw, TXGBE_VFMBCTL); in txgbe_read_v2p_mailbox()
452 u32 mbvficr = rd32(hw, TXGBE_MBVFICR(index)); in txgbe_check_for_bit_pf()
521 vflre = rd32(hw, TXGBE_FLRVFE(reg_offset)); in txgbe_check_for_rst_pf()
547 p2v_mailbox = rd32(hw, TXGBE_MBCTL(vf_number)); in txgbe_obtain_mbx_lock_pf()
H A Dtxgbe_mng.c83 if ((rd32(hw, TXGBE_MNGMBX) & 0xff0000) >> 16 == 0x80) { in txgbe_hic_unlocked()
287 tmp = rd32(hw, TXGBE_MNGSWSYNC); in txgbe_close_notify()
317 tmp = rd32(hw, TXGBE_MNGSWSYNC); in txgbe_open_notify()
/dpdk/drivers/net/ngbe/
H A Dngbe_ethdev.c762 ctrl = rd32(hw, NGBE_PORTCTL); in ngbe_vlan_hw_extend_disable()
776 ctrl = rd32(hw, NGBE_PORTCTL); in ngbe_vlan_hw_extend_enable()
789 ctrl = rd32(hw, NGBE_PORTCTL); in ngbe_qinq_hw_strip_disable()
802 ctrl = rd32(hw, NGBE_PORTCTL); in ngbe_qinq_hw_strip_enable()
1404 rd32(hw, NGBE_LSECTX_ENCPKT); in ngbe_read_stats_registers()
1939 fctrl = rd32(hw, NGBE_PSRCTL); in ngbe_dev_promiscuous_enable()
1952 fctrl = rd32(hw, NGBE_PSRCTL); in ngbe_dev_promiscuous_disable()
1969 fctrl = rd32(hw, NGBE_PSRCTL); in ngbe_dev_allmulticast_enable()
1985 fctrl = rd32(hw, NGBE_PSRCTL); in ngbe_dev_allmulticast_disable()
2650 gpie = rd32(hw, NGBE_GPIE); in ngbe_configure_msix()
[all …]
H A Dngbe_pf.c152 vtctl = rd32(hw, NGBE_POOLCTL); in ngbe_pf_host_configure()
179 gpie = rd32(hw, NGBE_GPIE); in ngbe_pf_host_configure()
181 gcr_ext = rd32(hw, NGBE_PORTCTL); in ngbe_pf_host_configure()
193 vlanctrl = rd32(hw, NGBE_VLANCTL); in ngbe_pf_host_configure()
206 fcrth = rd32(hw, NGBE_PBRXSIZE) - 32; in ngbe_pf_host_configure()
295 reg = rd32(hw, NGBE_POOLTXENA(0)); in ngbe_vf_reset_msg()
308 reg = rd32(hw, NGBE_POOLRXENA(0)); in ngbe_vf_reset_msg()
321 vmolr = rd32(hw, NGBE_POOLETHCTL(vf)); in ngbe_disable_vf_mc_promisc()
394 u32 vmolr = rd32(hw, NGBE_POOLETHCTL(vf)); in ngbe_vf_set_multicast()
563 fctrl = rd32(hw, NGBE_PSRCTL); in ngbe_set_vf_mc_promisc()
[all …]
H A Dngbe_rxtx.c2563 mrqc = rd32(hw, NGBE_RACTL); in ngbe_dev_rss_hash_update()
2616 mrqc = rd32(hw, NGBE_RACTL); in ngbe_dev_rss_hash_conf_get()
2873 fctrl = rd32(hw, NGBE_PSRCTL); in ngbe_dev_rx_init()
2880 hlreg0 = rd32(hw, NGBE_SECRXCTL); in ngbe_dev_rx_init()
2897 hlreg0 = rd32(hw, NGBE_PSRCTL); in ngbe_dev_rx_init()
2973 rxcsum = rd32(hw, NGBE_PSRCTL); in ngbe_dev_rx_init()
2983 rdrxctl = rd32(hw, NGBE_SECRXCTL); in ngbe_dev_rx_init()
3070 dmatxctl = rd32(hw, NGBE_DMATXCTRL); in ngbe_dev_rxtx_start()
3093 rxctrl = rd32(hw, NGBE_PBRXCTL); in ngbe_dev_rxtx_start()
3272 txtdh = rd32(hw, NGBE_TXRP(txq->reg_idx)); in ngbe_dev_tx_queue_stop()
[all …]
H A Dngbe_regs_group.h26 reg_buf[i] = rd32(hw, reg->base_addr + i * reg->stride); in ngbe_read_regs()
/dpdk/drivers/net/txgbe/
H A Dtxgbe_ethdev.c1184 ctrl = rd32(hw, TXGBE_PORTCTL); in txgbe_vlan_hw_extend_disable()
1197 ctrl = rd32(hw, TXGBE_PORTCTL); in txgbe_vlan_hw_extend_enable()
1210 ctrl = rd32(hw, TXGBE_PORTCTL); in txgbe_qinq_hw_strip_disable()
1223 ctrl = rd32(hw, TXGBE_PORTCTL); in txgbe_qinq_hw_strip_enable()
2132 rd32(hw, TXGBE_PBRXMISS(i)); in txgbe_read_stats_registers()
2776 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_promiscuous_enable()
2789 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_promiscuous_disable()
2806 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_allmulticast_enable()
2822 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_allmulticast_disable()
3713 gpie = rd32(hw, TXGBE_GPIE); in txgbe_configure_msix()
[all …]
H A Dtxgbe_pf.c222 vtctl = rd32(hw, TXGBE_POOLCTL); in txgbe_pf_host_configure()
253 gpie = rd32(hw, TXGBE_GPIE); in txgbe_pf_host_configure()
255 gcr_ext = rd32(hw, TXGBE_PORTCTL); in txgbe_pf_host_configure()
276 vlanctrl = rd32(hw, TXGBE_VLANCTL); in txgbe_pf_host_configure()
290 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 32; in txgbe_pf_host_configure()
383 reg = rd32(hw, TXGBE_POOLTXENA(reg_offset)); in txgbe_vf_reset_msg()
409 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); in txgbe_disable_vf_mc_promisc()
482 u32 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); in txgbe_vf_set_multicast()
638 vmvir = rd32(hw, TXGBE_POOLTAG(vf)); in txgbe_get_vf_queues()
703 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_set_vf_mc_promisc()
[all …]
H A Dtxgbe_rxtx.c2931 mrqc = rd32(hw, TXGBE_RACTL); in txgbe_dev_rss_hash_update()
3004 mrqc = rd32(hw, TXGBE_RACTL); in txgbe_dev_rss_hash_conf_get()
3186 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_dcb_tx_hw_config()
3191 reg = rd32(hw, TXGBE_PORTCTL); in txgbe_dcb_tx_hw_config()
3202 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_dcb_tx_hw_config()
3373 reg = rd32(hw, TXGBE_PORTCTL); in txgbe_dcb_rx_hw_config()
3840 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_vmdq_tx_hw_configure()
3854 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_vmdq_tx_hw_configure()
3904 mrqc = rd32(hw, TXGBE_PORTCTL); in txgbe_config_vf_rss()
3931 mrqc = rd32(hw, TXGBE_PORTCTL); in txgbe_config_vf_default()
[all …]
H A Dtxgbe_fdir.c88 if (rd32(hw, TXGBE_FDIRCTL) & TXGBE_FDIRCTL_INITDONE) in txgbe_fdir_enable()
271 flexreg = rd32(hw, TXGBE_FDIRFLEXCFG(i / 4)); in txgbe_fdir_set_flexbytes_offset()
281 if (rd32(hw, TXGBE_FDIRCTL) & in txgbe_fdir_set_flexbytes_offset()
352 flexreg = rd32(hw, TXGBE_FDIRFLEXCFG(i / 4)); in txgbe_set_fdir_flex_conf()
386 pbsize = rd32(hw, TXGBE_PBRXSIZE(0)); in txgbe_fdir_configure()
550 *fdircmd = rd32(hw, TXGBE_FDIRPICMD); in txgbe_fdir_check_cmd_complete()
H A Dtxgbe_regs_group.h26 reg_buf[i] = rd32(hw, in txgbe_read_regs()
/dpdk/drivers/net/i40e/base/
H A Di40e_diag.c39 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
43 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
50 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
H A Di40e_adminq.c305 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
355 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
797 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
799 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
838 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
877 val = rd32(hw, hw->aq.asq.head);
1035 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
1168 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1170 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
1173 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
[all …]
H A Di40e_lan_hmc.c106 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
109 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
126 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
132 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
149 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
155 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
172 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
178 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
/dpdk/drivers/net/ice/base/
H A Dice_controlq.c83 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask | in ice_check_sq_alive()
260 if (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa)) in ice_cfg_cq_regs()
844 while (rd32(hw, cq->sq.head) != ntc) { in ice_clean_sq()
845 ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head)); in ice_clean_sq()
920 return rd32(hw, cq->sq.head) == cq->sq.next_to_use; in ice_sq_done()
979 val = rd32(hw, cq->sq.head); in ice_sq_send_cmd_nolock()
1088 if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask || in ice_sq_send_cmd_nolock()
1089 rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) { in ice_sq_send_cmd_nolock()
1185 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
1241 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
/dpdk/drivers/common/iavf/
H A Diavf_adminq.c272 reg = rd32(hw, hw->aq.asq.bal); in iavf_config_asq_regs()
304 reg = rd32(hw, hw->aq.arq.bal); in iavf_config_arq_regs()
595 while (rd32(hw, hw->aq.asq.head) != ntc) { in iavf_clean_asq()
597 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in iavf_clean_asq()
632 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in iavf_asq_done()
672 val = rd32(hw, hw->aq.asq.head); in iavf_asq_send_command()
829 if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) { in iavf_asq_send_command()
899 ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK; in iavf_clean_arq_element()
H A Diavf_osdep.h120 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
140 #define IAVF_READ_REG(hw, reg) rd32(hw, reg)

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