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Searched refs:plt_err (Results 1 – 25 of 77) sorted by relevance

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/dpdk/drivers/common/cnxk/
H A Droc_tim.c36 plt_err("Invalid NPA pf func."); in tim_err_desc()
39 plt_err("Invalid SSO pf func."); in tim_err_desc()
42 plt_err("Ring busy."); in tim_err_desc()
45 plt_err("Invalid Ring id."); in tim_err_desc()
51 plt_err("Chunk size too small."); in tim_err_desc()
54 plt_err("Chunk size too big."); in tim_err_desc()
60 plt_err("Invalid Big endian value."); in tim_err_desc()
69 plt_err("Invalid bucket size."); in tim_err_desc()
72 plt_err("Invalid bucket size."); in tim_err_desc()
81 plt_err("Ring already stopped"); in tim_err_desc()
[all …]
H A Droc_ree.c55 plt_err("Could not allocate mailbox message"); in roc_ree_queues_attach()
81 plt_err("Could not allocate mailbox message"); in roc_ree_queues_detach()
131 plt_err("Could not get mailbox response"); in ree_send_mbox_msg()
148 plt_err("Could not allocate mailbox message"); in roc_ree_config_lf()
159 plt_err("Could not get mailbox response"); in roc_ree_config_lf()
178 plt_err("Could not allocate mailbox message"); in roc_ree_af_reg_read()
263 plt_err("Rule db size is too small"); in roc_ree_rule_db_get()
291 plt_err("Rule dbi size is too small"); in roc_ree_rule_db_get()
385 plt_err("Couldn't program empty rule db"); in roc_ree_rule_db_prog()
390 plt_err("Couldn't program NULL rule db"); in roc_ree_rule_db_prog()
[all …]
H A Droc_nix_inl_dev.c226 plt_err("Failed to detach CPT LF, rc=%d", rc); in nix_inl_cpt_release()
243 plt_err("Failed to alloc SSO HWS, rc=%d", rc); in nix_inl_sso_setup()
250 plt_err("Failed to alloc SSO HWGRP, rc=%d", rc); in nix_inl_sso_setup()
368 plt_err("Failed to alloc lf, rc=%d", rc); in nix_inl_nix_setup()
382 plt_err("Failed to get HW info, rc=%d", rc); in nix_inl_nix_setup()
429 plt_err("Failed to allocate memory for RQ's"); in nix_inl_nix_setup()
682 plt_err("Invalid soft exp ring base"); in inl_outb_soft_exp_poll()
716 plt_err("Invalid SA"); in inl_outb_soft_exp_poll()
763 plt_err("soft expiry ring bmap alloc failed"); in nix_inl_outb_poll_thread_setup()
770 plt_err("soft expiry ring bmap init failed"); in nix_inl_outb_poll_thread_setup()
[all …]
H A Droc_npa_irq.c18 plt_err("Err_intr=0x%" PRIx64 "", intr); in npa_err_irq()
66 plt_err("Ras_intr=0x%" PRIx64 "", intr); in npa_ras_irq()
114 plt_err("Failed execute irq get off=0x%x", off); in npa_q_irq_get_and_clear()
150 plt_err("queue_intr=0x%" PRIx64 " qintx=%d", intr, qintx); in npa_q_irq()
162 plt_err("Pool=%d NPA_POOL_ERR_INT_OVFLS", pool); in npa_q_irq()
165 plt_err("Pool=%d NPA_POOL_ERR_INT_RANGE", pool); in npa_q_irq()
168 plt_err("Pool=%d NPA_POOL_ERR_INT_PERR", pool); in npa_q_irq()
181 plt_err("Aura=%d NPA_AURA_ERR_INT_ADD_OVER", aura); in npa_q_irq()
184 plt_err("Aura=%d NPA_AURA_ERR_INT_ADD_UNDER", aura); in npa_q_irq()
187 plt_err("Aura=%d NPA_AURA_ERR_INT_FREE_UNDER", aura); in npa_q_irq()
[all …]
H A Droc_nix_irq.c171 plt_err("Failed execute irq get off=0x%x", off); in nix_lf_q_irq_get_and_clear()
208 plt_err("Failed to get sq context"); in nix_lf_is_sqb_null()
271 plt_err("RQ=%d NIX_RQINT_DROP", rq); in nix_lf_q_irq()
274 plt_err("RQ=%d NIX_RQINT_RED", rq); in nix_lf_q_irq()
283 plt_err("CQ=%d NIX_CQERRINT_DOOR_ERR", cq); in nix_lf_q_irq()
286 plt_err("CQ=%d NIX_CQERRINT_WR_FULL", cq); in nix_lf_q_irq()
289 plt_err("CQ=%d NIX_CQERRINT_CQE_FAULT", cq); in nix_lf_q_irq()
300 plt_err("SQ=%d NIX_SQINT_LMT_ERR, errcode %x", sq, rc); in nix_lf_q_irq()
315 plt_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq); in nix_lf_q_irq()
444 plt_err("Fail to register CQ irq, rc=%d", rc); in roc_nix_register_cq_irqs()
[all …]
H A Droc_nix_inl_dev_irq.c81 plt_err("GGRP 0 GGRP_INT=0x%" PRIx64 "", intr); in nix_inl_sso_hwgrp_irq()
98 plt_err("GWS 0 GWS_INT=0x%" PRIx64 "", intr); in nix_inl_sso_hws_irq()
117 plt_err("Invalid SSO/SSOW MSIX offsets (0x%x, 0x%x)", in nix_inl_sso_register_irqs()
207 plt_err("Failed to get rq_int"); in nix_inl_nix_q_irq()
214 plt_err("RQ=0 NIX_RQINT_DROP"); in nix_inl_nix_q_irq()
217 plt_err("RQ=0 NIX_RQINT_RED"); in nix_inl_nix_q_irq()
230 plt_err("Failed to get rq %d context, rc=%d", q, rc); in nix_inl_nix_q_irq()
262 plt_err("Failed to get rq %d context, rc=%d", q, rc); in nix_inl_nix_ras_irq()
295 plt_err("Failed to get rq %d context, rc=%d", q, rc); in nix_inl_nix_err_irq()
314 plt_err("Invalid NIXLF MSIX vector offset: 0x%x", msixoff); in nix_inl_nix_register_irqs()
[all …]
H A Droc_bphy_irq.c55 plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH); in roc_bphy_intr_init()
61 plt_err("Failed to get max irq number via ioctl"); in roc_bphy_intr_init()
73 plt_err("Failed to alloc irq_chip"); in roc_bphy_intr_init()
83 plt_err("Failed to alloc irq_chip irq_vecs"); in roc_bphy_intr_init()
89 plt_err("Failed to alloc irq_chip name"); in roc_bphy_intr_init()
250 plt_err("Failed to get affinity mask"); in roc_bphy_irq_handler_set()
265 plt_err("Failed to set affinity mask"); in roc_bphy_irq_handler_set()
276 plt_err("Failed to restore affinity mask"); in roc_bphy_irq_handler_set()
374 plt_err("Failed to free memzone: irq %d", in roc_bphy_intr_clear()
406 plt_err("Failed to get affinity mask"); in roc_bphy_intr_register()
[all …]
H A Droc_irq.c31 plt_err("Failed to get IRQ info rc=%d errno=%d", rc, errno); in irq_get_info()
39 plt_err("HW max=%d > PLT_MAX_RXTX_INTR_VEC_ID: %d", irq.count, in irq_get_info()
59 plt_err("vector=%d greater than max_intr=%d", vec, in irq_config()
82 plt_err("Failed to set_irqs vector=0x%x rc=%d", vec, rc); in irq_config()
114 plt_err("Failed to set irqs vector rc=%d", rc); in irq_init()
142 plt_err("Vector=%d greater than max_intr=%d or ", in dev_irq_register()
159 plt_err("Failed to register vector:0x%x irq callback.", vec); in dev_irq_register()
191 plt_err("Error unregistering MSI-X interrupts vec:%d > %d", vec, in dev_irq_unregister()
215 plt_err("Error unregistering MSI-X vec %d cb, rc=%d", vec, rc); in dev_irq_unregister()
H A Droc_model.c78 plt_err("Failed to open /proc/device-tree/compatible"); in cn10k_part_get()
83 plt_err("Failed to read from /proc/device-tree/compatible"); in cn10k_part_get()
88 plt_err("Malformed 'CPU compatible': <%s>", buf); in cn10k_part_get()
99 plt_err("Unidentified 'CPU compatible': <%s>", ptr); in cn10k_part_get()
139 plt_err("Invalid RoC model (impl=0x%x, part=0x%x, major=0x%x, minor=0x%x)", in populate_model()
221 plt_err("Failed to open %s", path); in of_env_get()
226 plt_err("Failed to read %s", path); in of_env_get()
232 plt_err("Unknown platform: %s", model->env); in of_env_get()
H A Droc_dpi.c68 plt_err("roc_dpi is NULL"); in roc_dpi_configure()
80 plt_err("Failed to create NPA pool, err %d\n", rc); in roc_dpi_configure()
89 plt_err("dpi memzone reserve failed"); in roc_dpi_configure()
103 plt_err("Failed to alloc buffer from NPA aura"); in roc_dpi_configure()
110 plt_err("Failed to alloc buffer from NPA aura"); in roc_dpi_configure()
135 plt_err("Failed to send mbox message %d to DPI PF, err %d", in roc_dpi_configure()
186 plt_err("Failed to send mbox message %d to DPI PF, err %d", in roc_dpi_dev_fini()
H A Droc_nix_inl.c47 plt_err("Failed to allocate memory for Inbound SA"); in nix_inl_inb_sa_tbl_setup()
299 plt_err("Failed to setup inbound lf, rc=%d", rc); in roc_nix_inl_inb_init()
362 plt_err("Failed to setup inline outb, need either " in roc_nix_inl_outb_init()
399 plt_err("Failed to alloc cpt lf memory"); in roc_nix_inl_outb_init()
417 plt_err("Failed to initialize CPT LF, rc=%d", rc); in roc_nix_inl_outb_init()
446 plt_err("Outbound SA base alloc failed"); in roc_nix_inl_outb_init()
534 plt_err("Failed to detach CPT LF, rc=%d", rc); in roc_nix_inl_outb_fini()
691 plt_err("Failed to prepare aq_enq msg, rc=%d", rc); in roc_nix_inl_dev_rq_get()
697 plt_err("Failed to send aq_enq msg, rc=%d", rc); in roc_nix_inl_dev_rq_get()
726 plt_err("Failed to find inline device with refs"); in roc_nix_inl_dev_rq_put()
[all …]
H A Droc_npc.c183 plt_err("Bmap alloc failed"); in roc_npc_init()
191 plt_err("flow_list alloc failed"); in roc_npc_init()
199 plt_err("prio_flow_list alloc failed"); in roc_npc_init()
215 plt_err("Bmap alloc failed"); in roc_npc_init()
223 plt_err("bitmap init failed"); in roc_npc_init()
280 plt_err("Output port should be VF"); in roc_npc_validate_portid_action()
285 plt_err("Invalid VF for output port"); in roc_npc_validate_portid_action()
372 plt_err("mark value must be < 0xfffe"); in npc_parse_actions()
545 plt_err("Unsupported action for egress"); in npc_parse_actions()
821 plt_err("too many queues for RSS context"); in npc_rss_action_configure()
[all …]
H A Droc_sso.c439 plt_err("Failed to release XAQ %d", rc); in sso_hwgrp_init_xaq_aura()
450 plt_err("Failed to allocate XAQ FC"); in sso_hwgrp_init_xaq_aura()
463 plt_err("Failed to allocate XAQ mem"); in sso_hwgrp_init_xaq_aura()
478 plt_err("Failed to create XAQ pool"); in sso_hwgrp_init_xaq_aura()
676 plt_err("Unable to attach SSO HWS LFs"); in roc_sso_rsrc_init()
688 plt_err("Unable to alloc SSO HWS LFs"); in roc_sso_rsrc_init()
695 plt_err("Unable to alloc SSO HWGRP Lfs"); in roc_sso_rsrc_init()
775 plt_err("Failed to init roc device"); in roc_sso_dev_init()
782 plt_err("Failed to get SSO resources"); in roc_sso_dev_init()
797 plt_err("Failed to get link_map memory"); in roc_sso_dev_init()
[all …]
H A Droc_dev.c75 plt_err("Message timeout: %dms", mbox->rsp_tmo); in pf_af_sync_msg()
142 plt_err("Routed messages: %d received: %d", num_msg, in af_pf_wait_msg()
156 plt_err("Failed to reserve VF%d message", vf); in af_pf_wait_msg()
245 plt_err("Failed to alloc VF%d READY message", in vf_pf_process_msgs()
427 plt_err("Message (%s) response has err=%d", in process_msgs()
464 plt_err("Failed to alloc VF%d UP message", vf); in pf_vf_mbox_send_up_msg()
672 plt_err("Fail to register PF(VF0-63) mbox irq"); in mbox_register_pf_irq()
687 plt_err("Fail to register AF<->PF mbox irq"); in mbox_register_pf_irq()
715 plt_err("Fail to register PF<->VF mbox irq"); in mbox_register_vf_irq()
974 plt_err("Invalid VF mbox base pa"); in dev_vf_mbase_get()
[all …]
H A Droc_tim_irq.c18 plt_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr); in tim_lf_irq()
20 plt_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr); in tim_lf_irq()
63 plt_err("Invalid MSIX offset for TIM LF %d", ring_id); in tim_register_irq_priv()
98 plt_err("Invalid MSIX offset for TIM LF %d", ring_id); in tim_unregister_irq_priv()
H A Droc_nix_tm_ops.c393 plt_err("Failed to enable smq %u, rc=%d", node->hw_id, in roc_nix_smq_flush()
448 plt_err("cgx start failed, rc=%d", rc); in roc_nix_tm_hierarchy_disable()
478 plt_err("Failed to disable backpressure, rc=%d", rc); in roc_nix_tm_hierarchy_disable()
491 plt_err("Failed to disable sqb aura fc, rc=%d", rc); in roc_nix_tm_hierarchy_disable()
498 plt_err("Failed to drain sq, rc=%d\n", rc); in roc_nix_tm_hierarchy_disable()
538 plt_err("Failed to gracefully flush sq %u", sq->qid); in roc_nix_tm_hierarchy_disable()
592 plt_err("TM failed to alloc tm resources=%d", rc); in roc_nix_tm_hierarchy_enable()
598 plt_err("TM failed to assign tm resources=%d", rc); in roc_nix_tm_hierarchy_enable()
625 plt_err("SQ %u sched update failed, rc=%d", node->id, in roc_nix_tm_hierarchy_enable()
654 plt_err("TM sw xon failed on SQ %u, rc=%d", node->id, in roc_nix_tm_hierarchy_enable()
[all …]
/dpdk/drivers/net/cnxk/
H A Dcnxk_ethdev.c136 plt_err("Outbound SA bmap alloc failed"); in nix_security_setup()
145 plt_err("Outbound SA bmap init failed"); in nix_security_setup()
163 plt_err("Outbound fc sw mem alloc failed"); in nix_security_setup()
453 plt_err("Failed to alloc tx queue mem"); in cnxk_nix_tx_queue_setup()
498 plt_err("Failed to cleanup sq, rc=%d", rc); in cnxk_nix_tx_queue_release()
536 plt_err("Invalid pool_id"); in cnxk_nix_rx_queue_setup()
1041 plt_err("Huge page is not configured"); in cnxk_nix_configure()
1046 plt_err("dcb enable is not supported"); in cnxk_nix_configure()
1145 plt_err("Failed to alloc rqs"); in cnxk_nix_configure()
1152 plt_err("Failed to alloc cqs"); in cnxk_nix_configure()
[all …]
H A Dcnxk_ptp.c38 plt_err("Failed to read the raw clock value: %d", rc); in cnxk_nix_tsc_convert()
46 plt_err("Failed to read the raw clock value: %d", rc); in cnxk_nix_tsc_convert()
64 plt_err("Failed to read the raw clock value: %d", rc); in cnxk_nix_tsc_convert()
128 plt_err("Failed to calculate delta and freq mult"); in cnxk_nix_timesync_adjust_time()
187 plt_err("PTP cannot be enabled for VF/SDP/LBK"); in cnxk_nix_timesync_enable()
195 plt_err("Ptype offload is disabled, it should be enabled"); in cnxk_nix_timesync_enable()
200 plt_err("Both PTP and switch header cannot be enabled"); in cnxk_nix_timesync_enable()
207 plt_err("Failed to allocate mem for tx tstamp addr"); in cnxk_nix_timesync_enable()
217 plt_err("Failed to register Rx timestamp field/flag"); in cnxk_nix_timesync_enable()
243 plt_err("Failed to set MTU size for ptp"); in cnxk_nix_timesync_enable()
[all …]
H A Dcnxk_ethdev_ops.c416 plt_err("Failed to add mac address, rc=%d", rc); in cnxk_nix_mac_addr_add()
438 plt_err("Failed to delete mac address, rc=%d", rc); in cnxk_nix_mac_addr_del()
457 plt_err("MTU is lesser than minimum"); in cnxk_nix_mtu_set()
463 plt_err("MTU is greater than maximum"); in cnxk_nix_mtu_set()
475 plt_err("Scatter offload is not enabled for mtu"); in cnxk_nix_mtu_set()
491 plt_err("Failed to set MTU, rc=%d", rc); in cnxk_nix_mtu_set()
501 plt_err("Failed to max Rx frame length, rc=%d", rc); in cnxk_nix_mtu_set()
925 plt_err("Hash key size mismatch %d vs %d", in cnxk_nix_rss_hash_update()
943 plt_err("Failed to set RSS hash function rc=%d", rc); in cnxk_nix_rss_hash_update()
985 plt_err("Failed to flush mcast address, rc=%d", in cnxk_nix_mc_addr_list_configure()
[all …]
/dpdk/drivers/crypto/cnxk/
H A Dcn9k_ipsec.c66 plt_err("Request timed out"); in cn9k_cpt_enq_sa_write()
79 plt_err("Request failed with DMA fault"); in cn9k_cpt_enq_sa_write()
97 plt_err("Invalid auth type"); in cn9k_cpt_enq_sa_write()
100 plt_err("Invalid encrypt type"); in cn9k_cpt_enq_sa_write()
167 plt_err("Unsupported AEAD algorithm"); in ipsec_sa_ctl_set()
185 plt_err("Unsupported cipher algorithm"); in ipsec_sa_ctl_set()
220 plt_err("Unsupported auth algorithm"); in ipsec_sa_ctl_set()
242 plt_err("Invalid AES key length"); in ipsec_sa_ctl_set()
394 plt_err("Unsupported auth algorithm"); in cn9k_ipsec_outb_sa_create()
481 plt_err("Unsupported auth algorithm %u", in cn9k_ipsec_outb_sa_create()
[all …]
H A Dcn9k_cryptodev.c52 plt_err("Failed to initialize platform model"); in cn9k_cpt_pci_probe()
74 plt_err("Failed to parse devargs rc=%d", rc); in cn9k_cpt_pci_probe()
80 plt_err("Failed to initialize roc cpt rc=%d", rc); in cn9k_cpt_pci_probe()
86 plt_err("Failed to add engine group rc=%d", rc); in cn9k_cpt_pci_probe()
115 plt_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)", in cn9k_cpt_pci_probe()
H A Dcn10k_cryptodev.c52 plt_err("Failed to initialize platform model"); in cn10k_cpt_pci_probe()
74 plt_err("Failed to parse devargs rc=%d", rc); in cn10k_cpt_pci_probe()
80 plt_err("Failed to initialize roc cpt rc=%d", rc); in cn10k_cpt_pci_probe()
86 plt_err("Failed to add engine group rc=%d", rc); in cn10k_cpt_pci_probe()
115 plt_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)", in cn10k_cpt_pci_probe()
H A Dcnxk_cryptodev.c40 plt_err("Could not add CPT SE engines"); in cnxk_cpt_eng_grp_add()
46 plt_err("Could not add CPT IE engines"); in cnxk_cpt_eng_grp_add()
52 plt_err("Could not add CPT AE engines"); in cnxk_cpt_eng_grp_add()
H A Dcnxk_cryptodev_ops.c71 plt_err("Could not configure device"); in cnxk_cpt_dev_config()
79 plt_err("Could not get FPM table"); in cnxk_cpt_dev_config()
86 plt_err("Could not get EC grp table"); in cnxk_cpt_dev_config()
140 plt_err("Could not release queue pair %u", i); in cnxk_cpt_dev_close()
221 plt_err("Could not create mempool for metabuf"); in cnxk_cpt_metabuf_mempool_create()
259 plt_err("Could not allocate queue pair"); in cnxk_cpt_qp_create()
274 plt_err("Could not allocate reserved memzone"); in cnxk_cpt_qp_create()
284 plt_err("Could not create mempool for metabuf"); in cnxk_cpt_qp_create()
345 plt_err("Could not destroy queue pair %d", qp_id); in cnxk_cpt_queue_pair_release()
373 plt_err("Invalid PCI mem address"); in cnxk_cpt_queue_pair_setup()
[all …]
/dpdk/drivers/raw/cnxk_bphy/
H A Dcnxk_bphy.c68 plt_err("Wrong number of descs reported\n"); in bphy_rawdev_selftest()
82 plt_err("intr init failed"); in bphy_rawdev_selftest()
90 plt_err("intr alloc failed"); in bphy_rawdev_selftest()
119 plt_err("intr register failed at irq %d", i); in bphy_rawdev_selftest()
129 plt_err("intr %u not handled", i); in bphy_rawdev_selftest()
134 plt_err("intr %u has wrong handler", i); in bphy_rawdev_selftest()
319 plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p", in bphy_rawdev_probe()
333 plt_err("Failed to allocate rawdev"); in bphy_rawdev_probe()
366 plt_err("invalid pci_dev"); in bphy_rawdev_remove()
373 plt_err("invalid device name (%s)", name); in bphy_rawdev_remove()

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