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Searched refs:pi (Results 1 – 25 of 76) sorted by relevance

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/dpdk/lib/power/
H A Dpower_acpi_cpufreq.c75 idx, pi->freqs[idx], pi->lcore_id); in set_freq_internal()
81 if (fprintf(pi->f, "%u", pi->freqs[idx]) < 0) { in set_freq_internal()
101 pi->governor_ori, sizeof(pi->governor_ori)); in power_set_governor_userspace()
159 pi->freqs[pi->nb_freqs++] = strtoul(freqs[i], &p, in power_get_available_freqs()
163 if ((pi->freqs[0]-1000) == pi->freqs[1]) { in power_get_available_freqs()
418 if (pi->curr_idx + 1 == pi->nb_freqs) in power_acpi_cpufreq_freq_down()
422 return set_freq_internal(pi, pi->curr_idx + 1); in power_acpi_cpufreq_freq_down()
437 (pi->curr_idx == 1 && pi->turbo_available && !pi->turbo_enable)) in power_acpi_cpufreq_freq_up()
441 return set_freq_internal(pi, pi->curr_idx - 1); in power_acpi_cpufreq_freq_up()
479 return set_freq_internal(pi, pi->nb_freqs - 1); in power_acpi_cpufreq_freq_min()
[all …]
H A Dpower_pstate_cpufreq.c125 pi->lcore_id); in power_init_for_setting_freq()
133 pi->lcore_id); in power_init_for_setting_freq()
334 pi->governor_ori, sizeof(pi->governor_ori)); in power_set_governor_performance()
430 pi->freqs[pi->nb_freqs++] = base_max_freq + 1; in power_get_available_freqs()
432 pi->freqs[pi->nb_freqs++] = in power_get_available_freqs()
700 (pi->curr_idx == 1 && pi->turbo_available && !pi->turbo_enable)) in power_pstate_cpufreq_freq_up()
704 return set_freq_internal(pi, pi->curr_idx - 1); in power_pstate_cpufreq_freq_up()
718 if (pi->curr_idx + 1 == pi->nb_freqs) in power_pstate_cpufreq_freq_down()
722 return set_freq_internal(pi, pi->curr_idx + 1); in power_pstate_cpufreq_freq_down()
761 return set_freq_internal(pi, pi->nb_freqs - 1); in power_pstate_cpufreq_freq_min()
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H A Dpower_cppc_cpufreq.c83 idx, pi->freqs[idx], pi->lcore_id); in set_freq_internal()
89 if (fprintf(pi->f, "%u", pi->freqs[idx]) < 0) { in set_freq_internal()
109 pi->governor_ori, sizeof(pi->governor_ori)); in power_set_governor_userspace()
257 pi->freqs[pi->nb_freqs++] = scaling_max_freq; in power_get_available_freqs()
259 pi->freqs[pi->nb_freqs++] = in power_get_available_freqs()
522 if (pi->curr_idx + 1 == pi->nb_freqs) in power_cppc_cpufreq_freq_down()
526 return set_freq_internal(pi, pi->curr_idx + 1); in power_cppc_cpufreq_freq_down()
540 if (pi->curr_idx == 0 || (pi->curr_idx == 1 && in power_cppc_cpufreq_freq_up()
541 pi->turbo_available && !pi->turbo_enable)) in power_cppc_cpufreq_freq_up()
545 return set_freq_internal(pi, pi->curr_idx - 1); in power_cppc_cpufreq_freq_up()
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/dpdk/drivers/net/ice/base/
H A Dice_sched.c22 if (!pi) in ice_sched_add_root_node()
25 hw = pi->hw; in ice_sched_add_root_node()
159 if (!pi) in ice_sched_add_node()
162 hw = pi->hw; in ice_sched_add_node()
285 if (!pi || !pi->root) in ice_sched_get_tc_node()
790 if (!pi) in ice_sched_clear_tx_topo()
795 ice_free_sched_node(pi, pi->root); in ice_sched_clear_tx_topo()
1211 if (!pi) in ice_sched_init_port()
1291 ice_free_sched_node(pi, pi->root); in ice_sched_init_port()
1311 if (!pi) in ice_sched_get_node()
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H A Dice_sched.h88 enum ice_status ice_sched_init_port(struct ice_port_info *pi);
93 void ice_sched_clear_port(struct ice_port_info *pi);
103 ice_sched_add_node(struct ice_port_info *pi, u8 layer,
125 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,
132 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
138 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc,
141 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc,
164 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id);
190 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,
204 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
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H A Dice_dcb.c787 struct ice_port_info *pi) in ice_cee_to_dcb_cfg() argument
912 if (!pi) in ice_get_ieee_or_cee_dcb_cfg()
952 if (!pi) in ice_get_dcb_cfg()
959 ice_cee_to_dcb_cfg(&cee_cfg, pi); in ice_get_dcb_cfg()
1479 if (!pi) in ice_set_dcb_cfg()
1482 hw = pi->hw; in ice_set_dcb_cfg()
1522 if (!pi) in ice_aq_query_port_ets()
1526 if (pi->root) in ice_aq_query_port_ets()
1550 if (!pi) in ice_update_port_tc_tree_cfg()
1572 tc_node = pi->root->children[i]; in ice_update_port_tc_tree_cfg()
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H A Dice_common.h41 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
42 enum ice_status ice_update_link_info(struct ice_port_info *pi);
141 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
157 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
162 struct ice_port_info *pi);
168 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
174 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
181 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
186 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
195 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
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H A Dice_common.c335 hw = pi->hw; in ice_aq_get_phy_caps()
458 if (!pi) in ice_get_media_type()
592 if (!pi) in ice_aq_get_link_info()
594 hw = pi->hw; in ice_aq_get_link_info()
3286 if (!pi) in ice_update_link_info()
3332 if (!pi) in ice_cache_phy_user_req()
3489 hw = pi->hw; in ice_set_fc()
3508 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); in ice_set_fc()
3635 hw = pi->hw; in ice_cfg_phy_fec()
4929 hw = pi->hw; in ice_ena_vsi_txq()
[all …]
H A Dice_dcb.h206 enum ice_status ice_get_dcb_cfg(struct ice_port_info *pi);
207 enum ice_status ice_set_dcb_cfg(struct ice_port_info *pi);
211 ice_query_port_ets(struct ice_port_info *pi,
215 ice_aq_query_port_ets(struct ice_port_info *pi,
219 ice_update_port_tc_tree_cfg(struct ice_port_info *pi,
/dpdk/drivers/net/cxgbe/
H A Dcxgbe_ethdev.c262 if (pi->link_cfg.link_ok) in cxgbe_dev_set_link_up()
291 if (!pi->link_cfg.link_ok) in cxgbe_dev_set_link_down()
329 if (!pi->viid) in cxgbe_dev_close()
332 cxgbe_down(pi); in cxgbe_dev_close()
335 pi->viid = 0; in cxgbe_dev_close()
423 cxgbe_down(pi); in cxgbe_dev_stop()
741 cxgbe_stats_reset(pi); in cxgbe_dev_stats_reset()
1249 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); in cxgbe_dev_rss_reta_update()
1261 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); in cxgbe_dev_rss_reta_update()
1467 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); in cxgbe_mac_addr_set()
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H A Dcxgbe_main.c646 t4_clr_port_stats(pi->adapter, pi->tx_chan); in cxgbe_stats_reset()
1611 pi->port_id, pi->link_cfg.mod_type); in t4_os_portmod_changed()
1623 pi->vi_en_rx == pi->link_cfg.link_ok) in t4_os_link_changed()
1629 if (pi->vi_en_tx == 0 && pi->vi_en_rx == 0) in t4_os_link_changed()
1637 pi->vi_en_rx = pi->link_cfg.link_ok; in t4_os_link_changed()
1638 t4_enable_vi(adap, adap->mbox, pi->viid, pi->vi_en_rx, pi->vi_en_tx); in t4_os_link_changed()
1691 pi->vi_en_rx, pi->vi_en_tx, false); in cxgbe_link_start()
1786 pi->rss_size, rss, pi->rss_size); in cxgbe_write_rss()
1808 __func__, pi->rss_size, pi->n_rx_qsets); in cxgbe_setup_rss()
1814 pi->rss[j] = j % pi->n_rx_qsets; in cxgbe_setup_rss()
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H A Dcxgbevf_main.c65 t4vf_get_port_stats(pi->adapter, pi->pidx, stats); in cxgbevf_stats_get()
175 struct port_info *pi; in cxgbevf_probe() local
242 adapter->port[i] = pi; in cxgbevf_probe()
243 pi->eth_dev = eth_dev; in cxgbevf_probe()
244 pi->adapter = adapter; in cxgbevf_probe()
245 pi->xact_addr_filt = -1; in cxgbevf_probe()
246 pi->port_id = port_id; in cxgbevf_probe()
247 pi->pidx = i; in cxgbevf_probe()
300 pi = adap2pinfo(adapter, i); in cxgbevf_probe()
301 if (pi->viid != 0) in cxgbevf_probe()
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H A Dmps_tcam.c65 struct adapter *adap = pi->adapter; in cxgbe_mpstcam_alloc()
91 mpstcam->free_idx, 0, pi->port_id, false); in cxgbe_mpstcam_alloc()
113 struct adapter *adap = pi->adapter; in cxgbe_mpstcam_modify()
179 struct adapter *adap = pi->adapter; in cxgbe_mpstcam_remove()
195 entry->mask, idx, 1, pi->port_id, in cxgbe_mpstcam_remove()
212 struct adapter *adap = pi->adapter; in cxgbe_mpstcam_rawf_enable()
223 rawf_idx = adap->params.rawf_start + pi->port_id; in cxgbe_mpstcam_rawf_enable()
229 entry->mask, rawf_idx, 0, pi->port_id, in cxgbe_mpstcam_rawf_enable()
243 struct adapter *adap = pi->adapter; in cxgbe_mpstcam_rawf_disable()
254 rawf_idx = adap->params.rawf_start + pi->port_id; in cxgbe_mpstcam_rawf_disable()
[all …]
H A Dcxgbe.h91 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps);
92 int cxgbe_set_link_status(struct port_info *pi, bool status);
94 int cxgbe_down(struct port_info *pi);
96 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats);
97 void cxgbevf_stats_get(struct port_info *pi, struct port_stats *stats);
98 void cxgbe_stats_reset(struct port_info *pi);
101 int cxgbe_link_start(struct port_info *pi);
108 int cxgbe_setup_rss(struct port_info *pi);
109 void cxgbe_enable_rx_queues(struct port_info *pi);
H A Dmps_tcam.h49 int cxgbe_mpstcam_alloc(struct port_info *pi, const u8 *mac, const u8 *mask);
50 int cxgbe_mpstcam_remove(struct port_info *pi, u16 idx);
51 int cxgbe_mpstcam_modify(struct port_info *pi, int idx, const u8 *addr);
52 int cxgbe_mpstcam_rawf_enable(struct port_info *pi);
53 int cxgbe_mpstcam_rawf_disable(struct port_info *pi);
H A Dcxgbevf_ethdev.c39 struct port_info *pi = eth_dev->data->dev_private; in cxgbevf_dev_stats_get() local
40 struct adapter *adapter = pi->adapter; in cxgbevf_dev_stats_get()
45 cxgbevf_stats_get(pi, &ps); in cxgbevf_dev_stats_get()
56 for (i = 0; i < pi->n_rx_qsets; i++) { in cxgbevf_dev_stats_get()
57 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; in cxgbevf_dev_stats_get()
104 struct port_info *pi = eth_dev->data->dev_private; in eth_cxgbevf_dev_init() local
159 pi->adapter = adapter; in eth_cxgbevf_dev_init()
/dpdk/app/test-pmd/
H A Dtestpmd.c2541 pi); in setup_hairpin_queues()
2564 pi); in setup_hairpin_queues()
2744 pi); in start_port()
2953 pi); in start_port()
3041 pi); in stop_port()
3048 pi); in stop_port()
3079 pi); in stop_port()
3085 pi); in stop_port()
3134 pi); in close_port()
3141 pi); in close_port()
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H A Dieee1588fwd.c55 port_ieee1588_rx_timestamp_check(portid_t pi, uint32_t index) in port_ieee1588_rx_timestamp_check() argument
59 if (rte_eth_timesync_read_rx_timestamp(pi, &timestamp, index) < 0) { in port_ieee1588_rx_timestamp_check()
60 printf("Port %u RX timestamp registers not valid\n", pi); in port_ieee1588_rx_timestamp_check()
64 pi, (uintmax_t)timestamp.tv_sec, timestamp.tv_nsec); in port_ieee1588_rx_timestamp_check()
70 port_ieee1588_tx_timestamp_check(portid_t pi) in port_ieee1588_tx_timestamp_check() argument
75 while ((rte_eth_timesync_read_tx_timestamp(pi, &timestamp) < 0) && in port_ieee1588_tx_timestamp_check()
83 pi, MAX_TX_TMST_WAIT_MICROSECS); in port_ieee1588_tx_timestamp_check()
202 port_ieee1588_fwd_begin(portid_t pi) in port_ieee1588_fwd_begin() argument
204 rte_eth_timesync_enable(pi); in port_ieee1588_fwd_begin()
209 port_ieee1588_fwd_end(portid_t pi) in port_ieee1588_fwd_end() argument
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H A Dnoisy_vnf.c227 noisy_fwd_end(portid_t pi) in noisy_fwd_end() argument
229 rte_ring_free(noisy_cfg[pi]->f); in noisy_fwd_end()
230 rte_free(noisy_cfg[pi]->vnf_mem); in noisy_fwd_end()
231 rte_free(noisy_cfg[pi]); in noisy_fwd_end()
235 noisy_fwd_begin(portid_t pi) in noisy_fwd_begin() argument
240 noisy_cfg[pi] = rte_zmalloc("testpmd noisy fifo and timers", in noisy_fwd_begin()
243 if (noisy_cfg[pi] == NULL) { in noisy_fwd_begin()
246 (int) pi); in noisy_fwd_begin()
248 n = noisy_cfg[pi]; in noisy_fwd_begin()
255 snprintf(name, NOISY_STRSIZE, NOISY_RING, pi); in noisy_fwd_begin()
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/dpdk/drivers/regex/mlx5/
H A Dmlx5_regex_fastpath.c104 ((uint32_t)pi << 8) | in set_wqe_ctrl_seg()
115 size_t pi, struct mlx5_klm *klm) in __prep_one() argument
141 (priv->has_umr ? (pi * 4 + 3) : pi), in __prep_one()
166 qp_obj->db_pi = qp_obj->pi; in prep_one()
167 qp_obj->pi = (qp_obj->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; in prep_one()
295 size_t pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, left_ops); in prep_regex_umr_wqe_set() local
316 qp_size_get(qp_obj), pi); in prep_regex_umr_wqe_set()
366 qp_obj->pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops); in prep_regex_umr_wqe_set()
398 queue->pi += nb_ops; in mlx5_regexdev_enqueue_gga()
417 qp_obj->pi); in mlx5_regexdev_enqueue()
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/dpdk/drivers/bus/fslmc/qbman/
H A Dqbman_portal.c821 s->eqcr.pi++; in qbman_swp_enqueue_ring_mode_direct()
859 s->eqcr.pi++; in qbman_swp_enqueue_ring_mode_cinh_read_direct()
897 s->eqcr.pi++; in qbman_swp_enqueue_ring_mode_cinh_direct()
933 s->eqcr.pi++; in qbman_swp_enqueue_ring_mode_mem_back()
987 eqcr_pi = s->eqcr.pi; in qbman_swp_enqueue_multiple_direct()
1003 eqcr_pi = s->eqcr.pi; in qbman_swp_enqueue_multiple_direct()
1020 eqcr_pi = s->eqcr.pi; in qbman_swp_enqueue_multiple_direct()
1057 eqcr_pi = s->eqcr.pi; in qbman_swp_enqueue_multiple_cinh_read_direct()
1073 eqcr_pi = s->eqcr.pi; in qbman_swp_enqueue_multiple_cinh_read_direct()
1090 eqcr_pi = s->eqcr.pi; in qbman_swp_enqueue_multiple_cinh_read_direct()
[all …]
/dpdk/drivers/baseband/la12xx/
H A Dbbdev_la12xx.c150 ch->md.pi = 0; in ipc_queue_configure()
346 uint32_t pi, uint32_t pi_flag) in is_bd_ring_full() argument
348 if (pi == ci) { in is_bd_ring_full()
423 uint32_t ci, ci_flag, pi, pi_flag; in enqueue_single_op() local
451 q_priv->bbdev_op[pi] = bbdev_op; in enqueue_single_op()
505 pi++; in enqueue_single_op()
508 pi = 0; in enqueue_single_op()
513 IPC_SET_PI_FLAG(pi); in enqueue_single_op()
515 IPC_RESET_PI_FLAG(pi); in enqueue_single_op()
516 q_priv->host_pi = pi; in enqueue_single_op()
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/dpdk/drivers/bus/pci/bsd/
H A Dpci.c411 struct pci_io pi = { in rte_pci_read_config() local
429 pi.pi_width = size; in rte_pci_read_config()
431 if (ioctl(fd, PCIOCREAD, &pi) < 0) in rte_pci_read_config()
433 memcpy(buf, &pi.pi_data, size); in rte_pci_read_config()
436 pi.pi_reg += size; in rte_pci_read_config()
455 struct pci_io pi = { in rte_pci_write_config() local
467 if (len == 3 || len > sizeof(pi.pi_data)) { in rte_pci_write_config()
472 memcpy(&pi.pi_data, buf, len); in rte_pci_write_config()
480 if (ioctl(fd, PCIOCWRITE, &pi) < 0) in rte_pci_write_config()
/dpdk/drivers/net/cxgbe/base/
H A Dt4_hw.c4527 pi->port_id, in t4_handle_get_port_info()
4597 struct port_info *pi = NULL; in t4_handle_fw_rpl() local
4601 pi = adap2pinfo(adap, i); in t4_handle_fw_rpl()
4602 if (pi->tx_chan == chan) in t4_handle_fw_rpl()
5371 pi->viid = ret; in t4_port_init()
5372 pi->tx_chan = j; in t4_port_init()
5373 pi->rss_size = rss_size; in t4_port_init()
5380 pi->vivld = vivld; in t4_port_init()
5381 pi->vin = vin; in t4_port_init()
5384 pi->vivld = G_FW_VIID_VIVLD(pi->viid); in t4_port_init()
[all …]
/dpdk/drivers/net/hinic/
H A Dhinic_pmd_rx.c35 #define HINIC_UPDATE_RQ_HW_PI(rxq, pi) \ argument
37 cpu_to_be16((pi) & HINIC_GET_RQ_WQE_MASK(rxq)))
339 u16 pi = 0; in hinic_rx_fill_wqe() local
902 u16 pi; in hinic_rearm_rxq_mbuf() local
914 pi = HINIC_GET_RQ_LOCAL_PI(rxq); in hinic_rearm_rxq_mbuf()
918 exp_wqebbs = rxq->q_depth - pi; in hinic_rearm_rxq_mbuf()
928 rq_wqe = WQ_WQE_ADDR(rxq->wq, (u32)pi); in hinic_rearm_rxq_mbuf()
942 HINIC_UPDATE_RQ_HW_PI(rxq, pi + rearm_wqebbs); in hinic_rearm_rxq_mbuf()
952 u16 pi = 0; in hinic_rx_alloc_pkts() local
975 rx_info = &rxq->rx_info[pi]; in hinic_rx_alloc_pkts()
[all …]

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