1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #ifndef _TXGBE_MNG_H_ 7 #define _TXGBE_MNG_H_ 8 9 #include "txgbe_type.h" 10 11 12 #define TXGBE_PMMBX_QSIZE 64 /* Num of dwords in range */ 13 #define TXGBE_PMMBX_BSIZE (TXGBE_PMMBX_QSIZE * 4) 14 #define TXGBE_PMMBX_DATA_SIZE (TXGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4) 15 #define TXGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */ 16 #define TXGBE_HI_FLASH_ERASE_TIMEOUT 5000 /* Process Erase command limit */ 17 #define TXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 18 #define TXGBE_HI_FLASH_VERIFY_TIMEOUT 60000 /* Process Apply command limit */ 19 #define TXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */ 20 21 /* CEM Support */ 22 #define FW_CEM_HDR_LEN 0x4 23 #define FW_CEM_CMD_DRIVER_INFO 0xDD 24 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 25 #define FW_CEM_CMD_RESERVED 0X0 26 #define FW_CEM_UNUSED_VER 0x0 27 #define FW_CEM_MAX_RETRIES 3 28 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 29 #define FW_READ_SHADOW_RAM_CMD 0x31 30 #define FW_READ_SHADOW_RAM_LEN 0x6 31 #define FW_WRITE_SHADOW_RAM_CMD 0x33 32 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 33 #define FW_SHADOW_RAM_DUMP_CMD 0x36 34 #define FW_SHADOW_RAM_DUMP_LEN 0 35 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 36 #define FW_NVM_DATA_OFFSET 3 37 #define FW_MAX_READ_BUFFER_SIZE 244 38 #define FW_DISABLE_RXEN_CMD 0xDE 39 #define FW_DISABLE_RXEN_LEN 0x1 40 #define FW_PHY_MGMT_REQ_CMD 0x20 41 #define FW_RESET_CMD 0xDF 42 #define FW_RESET_LEN 0x2 43 #define FW_SETUP_MAC_LINK_CMD 0xE0 44 #define FW_SETUP_MAC_LINK_LEN 0x2 45 #define FW_FLASH_UPGRADE_START_CMD 0xE3 46 #define FW_FLASH_UPGRADE_START_LEN 0x1 47 #define FW_FLASH_UPGRADE_WRITE_CMD 0xE4 48 #define FW_FLASH_UPGRADE_VERIFY_CMD 0xE5 49 #define FW_FLASH_UPGRADE_VERIFY_LEN 0x4 50 #define FW_PHY_ACT_DATA_COUNT 4 51 #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ 52 #define FW_PHY_TOKEN_WAIT 5 /* seconds */ 53 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) 54 #define FW_DW_OPEN_NOTIFY 0xE9 55 #define FW_DW_CLOSE_NOTIFY 0xEA 56 57 #define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383 58 #define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376 59 60 /* Host Interface Command Structures */ 61 struct txgbe_hic_hdr { 62 u8 cmd; 63 u8 buf_len; 64 union { 65 u8 cmd_resv; 66 u8 ret_status; 67 } cmd_or_resp; 68 u8 checksum; 69 }; 70 71 struct txgbe_hic_hdr2_req { 72 u8 cmd; 73 u8 buf_lenh; 74 u8 buf_lenl; 75 u8 checksum; 76 }; 77 78 struct txgbe_hic_hdr2_rsp { 79 u8 cmd; 80 u8 buf_lenl; 81 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 82 u8 checksum; 83 }; 84 85 union txgbe_hic_hdr2 { 86 struct txgbe_hic_hdr2_req req; 87 struct txgbe_hic_hdr2_rsp rsp; 88 }; 89 90 struct txgbe_hic_drv_info { 91 struct txgbe_hic_hdr hdr; 92 u8 port_num; 93 u8 ver_sub; 94 u8 ver_build; 95 u8 ver_min; 96 u8 ver_maj; 97 u8 pad; /* end spacing to ensure length is mult. of dword */ 98 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 99 }; 100 101 /* These need to be dword aligned */ 102 struct txgbe_hic_read_shadow_ram { 103 union txgbe_hic_hdr2 hdr; 104 u32 address; 105 u16 length; 106 u16 pad2; 107 u16 data; 108 u16 pad3; 109 }; 110 111 struct txgbe_hic_write_shadow_ram { 112 union txgbe_hic_hdr2 hdr; 113 u32 address; 114 u16 length; 115 u16 pad2; 116 u16 data; 117 u16 pad3; 118 }; 119 120 struct txgbe_hic_disable_rxen { 121 struct txgbe_hic_hdr hdr; 122 u8 port_number; 123 u8 pad2; 124 u16 pad3; 125 }; 126 127 struct txgbe_hic_reset { 128 struct txgbe_hic_hdr hdr; 129 u16 lan_id; 130 u16 reset_type; 131 }; 132 133 struct txgbe_hic_phy_cfg { 134 struct txgbe_hic_hdr hdr; 135 u8 lan_id; 136 u8 phy_mode; 137 u16 phy_speed; 138 }; 139 140 enum txgbe_module_id { 141 TXGBE_MODULE_EEPROM = 0, 142 TXGBE_MODULE_FIRMWARE, 143 TXGBE_MODULE_HARDWARE, 144 TXGBE_MODULE_PCIE 145 }; 146 147 struct txgbe_hic_upg_start { 148 struct txgbe_hic_hdr hdr; 149 u8 module_id; 150 u8 pad2; 151 u16 pad3; 152 }; 153 154 struct txgbe_hic_upg_write { 155 struct txgbe_hic_hdr hdr; 156 u8 data_len; 157 u8 eof_flag; 158 u16 check_sum; 159 u32 data[62]; 160 }; 161 162 enum txgbe_upg_flag { 163 TXGBE_RESET_NONE = 0, 164 TXGBE_RESET_FIRMWARE, 165 TXGBE_RELOAD_EEPROM, 166 TXGBE_RESET_LAN 167 }; 168 169 struct txgbe_hic_upg_verify { 170 struct txgbe_hic_hdr hdr; 171 u32 action_flag; 172 }; 173 174 s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len); 175 s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len); 176 s32 txgbe_close_notify(struct txgbe_hw *hw); 177 s32 txgbe_open_notify(struct txgbe_hw *hw); 178 179 s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min, u8 build, 180 u8 ver, u16 len, const char *str); 181 s32 txgbe_hic_reset(struct txgbe_hw *hw); 182 bool txgbe_mng_present(struct txgbe_hw *hw); 183 bool txgbe_mng_enabled(struct txgbe_hw *hw); 184 #endif /* _TXGBE_MNG_H_ */ 185