1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-3-Clause */
2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */
3
4 #ifndef _IONIC_IF_H_
5 #define _IONIC_IF_H_
6
7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
8 #define IONIC_DEV_INFO_VERSION 1
9 #define IONIC_IFNAMSIZ 16
10
11 /**
12 * enum ionic_cmd_opcode - Device commands
13 */
14 enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17 /* Device commands */
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24 /* Port commands */
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31 /* LIF commands */
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37
38 IONIC_CMD_RX_MODE_SET = 30,
39 IONIC_CMD_RX_FILTER_ADD = 31,
40 IONIC_CMD_RX_FILTER_DEL = 32,
41
42 /* Queue commands */
43 IONIC_CMD_Q_IDENTIFY = 39,
44 IONIC_CMD_Q_INIT = 40,
45 IONIC_CMD_Q_CONTROL = 41,
46
47 /* RDMA commands */
48 IONIC_CMD_RDMA_RESET_LIF = 50,
49 IONIC_CMD_RDMA_CREATE_EQ = 51,
50 IONIC_CMD_RDMA_CREATE_CQ = 52,
51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
52
53 /* SR/IOV commands */
54 IONIC_CMD_VF_GETATTR = 60,
55 IONIC_CMD_VF_SETATTR = 61,
56
57 /* QoS commands */
58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
59 IONIC_CMD_QOS_CLASS_INIT = 241,
60 IONIC_CMD_QOS_CLASS_RESET = 242,
61 IONIC_CMD_QOS_CLASS_UPDATE = 243,
62 IONIC_CMD_QOS_CLEAR_STATS = 244,
63 IONIC_CMD_QOS_RESET = 245,
64
65 /* Firmware commands */
66 IONIC_CMD_FW_DOWNLOAD = 254,
67 IONIC_CMD_FW_CONTROL = 255,
68 };
69
70 /**
71 * enum ionic_status_code - Device command return codes
72 */
73 enum ionic_status_code {
74 IONIC_RC_SUCCESS = 0, /* Success */
75 IONIC_RC_EVERSION = 1, /* Incorrect version for request */
76 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */
77 IONIC_RC_EIO = 3, /* I/O error */
78 IONIC_RC_EPERM = 4, /* Permission denied */
79 IONIC_RC_EQID = 5, /* Bad qid */
80 IONIC_RC_EQTYPE = 6, /* Bad qtype */
81 IONIC_RC_ENOENT = 7, /* No such element */
82 IONIC_RC_EINTR = 8, /* operation interrupted */
83 IONIC_RC_EAGAIN = 9, /* Try again */
84 IONIC_RC_ENOMEM = 10, /* Out of memory */
85 IONIC_RC_EFAULT = 11, /* Bad address */
86 IONIC_RC_EBUSY = 12, /* Device or resource busy */
87 IONIC_RC_EEXIST = 13, /* object already exists */
88 IONIC_RC_EINVAL = 14, /* Invalid argument */
89 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */
90 IONIC_RC_ERANGE = 16, /* Parameter out of range */
91 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
92 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
93 IONIC_RC_ENOSUPP = 19, /* Operation not supported */
94 IONIC_RC_ERROR = 29, /* Generic error */
95 IONIC_RC_ERDMA = 30, /* Generic RDMA error */
96 IONIC_RC_EVFID = 31, /* VF ID does not exist */
97 };
98
99 enum ionic_notifyq_opcode {
100 IONIC_EVENT_LINK_CHANGE = 1,
101 IONIC_EVENT_RESET = 2,
102 IONIC_EVENT_HEARTBEAT = 3,
103 IONIC_EVENT_LOG = 4,
104 IONIC_EVENT_XCVR = 5,
105 };
106
107 /**
108 * struct ionic_admin_cmd - General admin command format
109 * @opcode: Opcode for the command
110 * @lif_index: LIF index
111 * @cmd_data: Opcode-specific command bytes
112 */
113 struct ionic_admin_cmd {
114 u8 opcode;
115 u8 rsvd;
116 __le16 lif_index;
117 u8 cmd_data[60];
118 };
119
120 /**
121 * struct ionic_admin_comp - General admin command completion format
122 * @status: Status of the command (enum ionic_status_code)
123 * @comp_index: Index in the descriptor ring for which this is the completion
124 * @cmd_data: Command-specific bytes
125 * @color: Color bit (Always 0 for commands issued to the
126 * Device Cmd Registers)
127 */
128 struct ionic_admin_comp {
129 u8 status;
130 u8 rsvd;
131 __le16 comp_index;
132 u8 cmd_data[11];
133 u8 color;
134 #define IONIC_COMP_COLOR_MASK 0x80
135 };
136
color_match(u8 color,u8 done_color)137 static inline u8 color_match(u8 color, u8 done_color)
138 {
139 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
140 }
141
142 /**
143 * struct ionic_nop_cmd - NOP command
144 * @opcode: opcode
145 */
146 struct ionic_nop_cmd {
147 u8 opcode;
148 u8 rsvd[63];
149 };
150
151 /**
152 * struct ionic_nop_comp - NOP command completion
153 * @status: Status of the command (enum ionic_status_code)
154 */
155 struct ionic_nop_comp {
156 u8 status;
157 u8 rsvd[15];
158 };
159
160 /**
161 * struct ionic_dev_init_cmd - Device init command
162 * @opcode: opcode
163 * @type: Device type
164 */
165 struct ionic_dev_init_cmd {
166 u8 opcode;
167 u8 type;
168 u8 rsvd[62];
169 };
170
171 /**
172 * struct ionic_dev_init_comp - Device init command completion
173 * @status: Status of the command (enum ionic_status_code)
174 */
175 struct ionic_dev_init_comp {
176 u8 status;
177 u8 rsvd[15];
178 };
179
180 /**
181 * struct ionic_dev_reset_cmd - Device reset command
182 * @opcode: opcode
183 */
184 struct ionic_dev_reset_cmd {
185 u8 opcode;
186 u8 rsvd[63];
187 };
188
189 /**
190 * struct ionic_dev_reset_comp - Reset command completion
191 * @status: Status of the command (enum ionic_status_code)
192 */
193 struct ionic_dev_reset_comp {
194 u8 status;
195 u8 rsvd[15];
196 };
197
198 #define IONIC_IDENTITY_VERSION_1 1
199
200 /**
201 * struct ionic_dev_identify_cmd - Driver/device identify command
202 * @opcode: opcode
203 * @ver: Highest version of identify supported by driver
204 */
205 struct ionic_dev_identify_cmd {
206 u8 opcode;
207 u8 ver;
208 u8 rsvd[62];
209 };
210
211 /**
212 * struct ionic_dev_identify_comp - Driver/device identify command completion
213 * @status: Status of the command (enum ionic_status_code)
214 * @ver: Version of identify returned by device
215 */
216 struct ionic_dev_identify_comp {
217 u8 status;
218 u8 ver;
219 u8 rsvd[14];
220 };
221
222 enum ionic_os_type {
223 IONIC_OS_TYPE_LINUX = 1,
224 IONIC_OS_TYPE_WIN = 2,
225 IONIC_OS_TYPE_DPDK = 3,
226 IONIC_OS_TYPE_FREEBSD = 4,
227 IONIC_OS_TYPE_IPXE = 5,
228 IONIC_OS_TYPE_ESXI = 6,
229 };
230
231 /**
232 * union ionic_drv_identity - driver identity information
233 * @os_type: OS type (see enum ionic_os_type)
234 * @os_dist: OS distribution, numeric format
235 * @os_dist_str: OS distribution, string format
236 * @kernel_ver: Kernel version, numeric format
237 * @kernel_ver_str: Kernel version, string format
238 * @driver_ver_str: Driver version, string format
239 */
240 union ionic_drv_identity {
241 struct {
242 __le32 os_type;
243 __le32 os_dist;
244 char os_dist_str[128];
245 __le32 kernel_ver;
246 char kernel_ver_str[32];
247 char driver_ver_str[32];
248 };
249 __le32 words[478];
250 };
251
252 /**
253 * union ionic_dev_identity - device identity information
254 * @version: Version of device identify
255 * @type: Identify type (0 for now)
256 * @nports: Number of ports provisioned
257 * @nlifs: Number of LIFs provisioned
258 * @nintrs: Number of interrupts provisioned
259 * @ndbpgs_per_lif: Number of doorbell pages per LIF
260 * @intr_coal_mult: Interrupt coalescing multiplication factor
261 * Scale user-supplied interrupt coalescing
262 * value in usecs to device units using:
263 * device units = usecs * mult / div
264 * @intr_coal_div: Interrupt coalescing division factor
265 * Scale user-supplied interrupt coalescing
266 * value in usecs to device units using:
267 * device units = usecs * mult / div
268 * @eq_count: Number of shared event queues
269 */
270 union ionic_dev_identity {
271 struct {
272 u8 version;
273 u8 type;
274 u8 rsvd[2];
275 u8 nports;
276 u8 rsvd2[3];
277 __le32 nlifs;
278 __le32 nintrs;
279 __le32 ndbpgs_per_lif;
280 __le32 intr_coal_mult;
281 __le32 intr_coal_div;
282 __le32 eq_count;
283 };
284 __le32 words[478];
285 };
286
287 enum ionic_lif_type {
288 IONIC_LIF_TYPE_CLASSIC = 0,
289 IONIC_LIF_TYPE_MACVLAN = 1,
290 IONIC_LIF_TYPE_NETQUEUE = 2,
291 };
292
293 /**
294 * struct ionic_lif_identify_cmd - LIF identify command
295 * @opcode: opcode
296 * @type: LIF type (enum ionic_lif_type)
297 * @ver: Version of identify returned by device
298 */
299 struct ionic_lif_identify_cmd {
300 u8 opcode;
301 u8 type;
302 u8 ver;
303 u8 rsvd[61];
304 };
305
306 /**
307 * struct ionic_lif_identify_comp - LIF identify command completion
308 * @status: Status of the command (enum ionic_status_code)
309 * @ver: Version of identify returned by device
310 */
311 struct ionic_lif_identify_comp {
312 u8 status;
313 u8 ver;
314 u8 rsvd2[14];
315 };
316
317 /**
318 * enum ionic_lif_capability - LIF capabilities
319 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet
320 * @IONIC_LIF_CAP_RDMA: LIF support RDMA
321 */
322 enum ionic_lif_capability {
323 IONIC_LIF_CAP_ETH = BIT(0),
324 IONIC_LIF_CAP_RDMA = BIT(1),
325 };
326
327 /**
328 * enum ionic_logical_qtype - Logical Queue Types
329 * @IONIC_QTYPE_ADMINQ: Administrative Queue
330 * @IONIC_QTYPE_NOTIFYQ: Notify Queue
331 * @IONIC_QTYPE_RXQ: Receive Queue
332 * @IONIC_QTYPE_TXQ: Transmit Queue
333 * @IONIC_QTYPE_EQ: Event Queue
334 * @IONIC_QTYPE_MAX: Max queue type supported
335 */
336 enum ionic_logical_qtype {
337 IONIC_QTYPE_ADMINQ = 0,
338 IONIC_QTYPE_NOTIFYQ = 1,
339 IONIC_QTYPE_RXQ = 2,
340 IONIC_QTYPE_TXQ = 3,
341 IONIC_QTYPE_EQ = 4,
342 IONIC_QTYPE_MAX = 16,
343 };
344
345 /**
346 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type
347 * @qtype: Hardware Queue Type
348 * @qid_count: Number of Queue IDs of the logical type
349 * @qid_base: Minimum Queue ID of the logical type
350 */
351 struct ionic_lif_logical_qtype {
352 u8 qtype;
353 u8 rsvd[3];
354 __le32 qid_count;
355 __le32 qid_base;
356 };
357
358 /**
359 * enum ionic_lif_state - LIF state
360 * @IONIC_LIF_DISABLE: LIF disabled
361 * @IONIC_LIF_ENABLE: LIF enabled
362 * @IONIC_LIF_QUIESCE: LIF Quiesced
363 */
364 enum ionic_lif_state {
365 IONIC_LIF_QUIESCE = 0,
366 IONIC_LIF_ENABLE = 1,
367 IONIC_LIF_DISABLE = 2,
368 };
369
370 /**
371 * union ionic_lif_config - LIF configuration
372 * @state: LIF state (enum ionic_lif_state)
373 * @name: LIF name
374 * @mtu: MTU
375 * @mac: Station MAC address
376 * @vlan: Default Vlan ID
377 * @features: Features (enum ionic_eth_hw_features)
378 * @queue_count: Queue counts per queue-type
379 */
380 union ionic_lif_config {
381 struct {
382 u8 state;
383 u8 rsvd[3];
384 char name[IONIC_IFNAMSIZ];
385 __le32 mtu;
386 u8 mac[6];
387 __le16 vlan;
388 __le64 features;
389 __le32 queue_count[IONIC_QTYPE_MAX];
390 } __rte_packed;
391 __le32 words[64];
392 };
393
394 /**
395 * struct ionic_lif_identity - LIF identity information (type-specific)
396 *
397 * @capabilities: LIF capabilities
398 *
399 * @eth: Ethernet identify structure
400 * @version: Ethernet identify structure version
401 * @max_ucast_filters: Number of perfect unicast addresses supported
402 * @max_mcast_filters: Number of perfect multicast addresses supported
403 * @min_frame_size: Minimum size of frames to be sent
404 * @max_frame_size: Maximum size of frames to be sent
405 * @config: LIF config struct with features, mtu, mac, q counts
406 *
407 * @rdma: RDMA identify structure
408 * @version: RDMA version of opcodes and queue descriptors
409 * @qp_opcodes: Number of RDMA queue pair opcodes supported
410 * @admin_opcodes: Number of RDMA admin opcodes supported
411 * @npts_per_lif: Page table size per LIF
412 * @nmrs_per_lif: Number of memory regions per LIF
413 * @nahs_per_lif: Number of address handles per LIF
414 * @max_stride: Max work request stride
415 * @cl_stride: Cache line stride
416 * @pte_stride: Page table entry stride
417 * @rrq_stride: Remote RQ work request stride
418 * @rsq_stride: Remote SQ work request stride
419 * @dcqcn_profiles: Number of DCQCN profiles
420 * @aq_qtype: RDMA Admin Qtype
421 * @sq_qtype: RDMA Send Qtype
422 * @rq_qtype: RDMA Receive Qtype
423 * @cq_qtype: RDMA Completion Qtype
424 * @eq_qtype: RDMA Event Qtype
425 */
426 union ionic_lif_identity {
427 struct {
428 __le64 capabilities;
429
430 struct {
431 u8 version;
432 u8 rsvd[3];
433 __le32 max_ucast_filters;
434 __le32 max_mcast_filters;
435 __le16 rss_ind_tbl_sz;
436 __le32 min_frame_size;
437 __le32 max_frame_size;
438 u8 rsvd2[106];
439 union ionic_lif_config config;
440 } __rte_packed eth;
441
442 struct {
443 u8 version;
444 u8 qp_opcodes;
445 u8 admin_opcodes;
446 u8 rsvd;
447 __le32 npts_per_lif;
448 __le32 nmrs_per_lif;
449 __le32 nahs_per_lif;
450 u8 max_stride;
451 u8 cl_stride;
452 u8 pte_stride;
453 u8 rrq_stride;
454 u8 rsq_stride;
455 u8 dcqcn_profiles;
456 u8 rsvd_dimensions[10];
457 struct ionic_lif_logical_qtype aq_qtype;
458 struct ionic_lif_logical_qtype sq_qtype;
459 struct ionic_lif_logical_qtype rq_qtype;
460 struct ionic_lif_logical_qtype cq_qtype;
461 struct ionic_lif_logical_qtype eq_qtype;
462 } __rte_packed rdma;
463 } __rte_packed;
464 __le32 words[478];
465 };
466
467 /**
468 * struct ionic_lif_init_cmd - LIF init command
469 * @opcode: Opcode
470 * @type: LIF type (enum ionic_lif_type)
471 * @index: LIF index
472 * @info_pa: Destination address for LIF info (struct ionic_lif_info)
473 */
474 struct ionic_lif_init_cmd {
475 u8 opcode;
476 u8 type;
477 __le16 index;
478 __le32 rsvd;
479 __le64 info_pa;
480 u8 rsvd2[48];
481 };
482
483 /**
484 * struct ionic_lif_init_comp - LIF init command completion
485 * @status: Status of the command (enum ionic_status_code)
486 * @hw_index: Hardware index of the initialized LIF
487 */
488 struct ionic_lif_init_comp {
489 u8 status;
490 u8 rsvd;
491 __le16 hw_index;
492 u8 rsvd2[12];
493 };
494
495 /**
496 * struct ionic_q_identify_cmd - queue identify command
497 * @opcode: opcode
498 * @lif_type: LIF type (enum ionic_lif_type)
499 * @type: Logical queue type (enum ionic_logical_qtype)
500 * @ver: Highest queue type version that the driver supports
501 */
502 struct ionic_q_identify_cmd {
503 u8 opcode;
504 u8 rsvd;
505 __le16 lif_type;
506 u8 type;
507 u8 ver;
508 u8 rsvd2[58];
509 };
510
511 /**
512 * struct ionic_q_identify_comp - queue identify command completion
513 * @status: Status of the command (enum ionic_status_code)
514 * @comp_index: Index in the descriptor ring for which this is the completion
515 * @ver: Queue type version that can be used with FW
516 */
517 struct ionic_q_identify_comp {
518 u8 status;
519 u8 rsvd;
520 __le16 comp_index;
521 u8 ver;
522 u8 rsvd2[11];
523 };
524
525 /**
526 * union ionic_q_identity - queue identity information
527 * @version: Queue type version that can be used with FW
528 * @supported: Bitfield of queue versions, first bit = ver 0
529 * @features: Queue features
530 * @desc_sz: Descriptor size
531 * @comp_sz: Completion descriptor size
532 * @sg_desc_sz: Scatter/Gather descriptor size
533 * @max_sg_elems: Maximum number of Scatter/Gather elements
534 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor
535 */
536 union ionic_q_identity {
537 struct {
538 u8 version;
539 u8 supported;
540 u8 rsvd[6];
541 #define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */
542 #define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */
543 #define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */
544 #define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */
545 __le64 features;
546 __le16 desc_sz;
547 __le16 comp_sz;
548 __le16 sg_desc_sz;
549 __le16 max_sg_elems;
550 __le16 sg_desc_stride;
551 };
552 __le32 words[478];
553 };
554
555 /**
556 * struct ionic_q_init_cmd - Queue init command
557 * @opcode: opcode
558 * @type: Logical queue type
559 * @ver: Queue type version
560 * @lif_index: LIF index
561 * @index: (LIF, qtype) relative admin queue index
562 * @intr_index: Interrupt control register index, or Event queue index
563 * @pid: Process ID
564 * @flags:
565 * IRQ: Interrupt requested on completion
566 * ENA: Enable the queue. If ENA=0 the queue is initialized
567 * but remains disabled, to be later enabled with the
568 * Queue Enable command. If ENA=1, then queue is
569 * initialized and then enabled.
570 * SG: Enable Scatter-Gather on the queue.
571 * in number of descs. The actual ring size is
572 * (1 << ring_size). For example, to
573 * select a ring size of 64 descriptors write
574 * ring_size = 6. The minimum ring_size value is 2
575 * for a ring size of 4 descriptors. The maximum
576 * ring_size value is 16 for a ring size of 64k
577 * descriptors. Values of ring_size <2 and >16 are
578 * reserved.
579 * EQ: Enable the Event Queue
580 * @cos: Class of service for this queue
581 * @ring_size: Queue ring size, encoded as a log2(size)
582 * @ring_base: Queue ring base address
583 * @cq_ring_base: Completion queue ring base address
584 * @sg_ring_base: Scatter/Gather ring base address
585 */
586 struct ionic_q_init_cmd {
587 u8 opcode;
588 u8 rsvd;
589 __le16 lif_index;
590 u8 type;
591 u8 ver;
592 u8 rsvd1[2];
593 __le32 index;
594 __le16 pid;
595 __le16 intr_index;
596 __le16 flags;
597 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */
598 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
599 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
600 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
601 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */
602 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
603 u8 cos;
604 u8 ring_size;
605 __le64 ring_base;
606 __le64 cq_ring_base;
607 __le64 sg_ring_base;
608 u8 rsvd2[20];
609 } __rte_packed;
610
611 /**
612 * struct ionic_q_init_comp - Queue init command completion
613 * @status: Status of the command (enum ionic_status_code)
614 * @comp_index: Index in the descriptor ring for which this is the completion
615 * @hw_index: Hardware Queue ID
616 * @hw_type: Hardware Queue type
617 * @color: Color
618 */
619 struct ionic_q_init_comp {
620 u8 status;
621 u8 rsvd;
622 __le16 comp_index;
623 __le32 hw_index;
624 u8 hw_type;
625 u8 rsvd2[6];
626 u8 color;
627 };
628
629 /* the device's internal addressing uses up to 52 bits */
630 #define IONIC_ADDR_LEN 52
631 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
632
633 enum ionic_txq_desc_opcode {
634 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
635 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
636 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
637 IONIC_TXQ_DESC_OPCODE_TSO = 3,
638 };
639
640 /**
641 * struct ionic_txq_desc - Ethernet Tx queue descriptor format
642 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*:
643 *
644 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
645 * Non-offload send. No segmentation,
646 * fragmentation or checksum calc/insertion is
647 * performed by device; packet is prepared
648 * to send by software stack and requires
649 * no further manipulation from device.
650 *
651 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
652 * Offload 16-bit L4 checksum
653 * calculation/insertion. The device will
654 * calculate the L4 checksum value and
655 * insert the result in the packet's L4
656 * header checksum field. The L4 checksum
657 * is calculated starting at @csum_start bytes
658 * into the packet to the end of the packet.
659 * The checksum insertion position is given
660 * in @csum_offset, which is the offset from
661 * @csum_start to the checksum field in the L4
662 * header. This feature is only applicable to
663 * protocols such as TCP, UDP and ICMP where a
664 * standard (i.e. the 'IP-style' checksum)
665 * one's complement 16-bit checksum is used,
666 * using an IP pseudo-header to seed the
667 * calculation. Software will preload the L4
668 * checksum field with the IP pseudo-header
669 * checksum.
670 *
671 * For tunnel encapsulation, @csum_start and
672 * @csum_offset refer to the inner L4
673 * header. Supported tunnels encapsulations
674 * are: IPIP, GRE, and UDP. If the @encap
675 * is clear, no further processing by the
676 * device is required; software will
677 * calculate the outer header checksums. If
678 * the @encap is set, the device will
679 * offload the outer header checksums using
680 * LCO (local checksum offload) (see
681 * Documentation/networking/checksum-offloads.rst
682 * for more info).
683 *
684 * IONIC_TXQ_DESC_OPCODE_CSUM_HW:
685 * Offload 16-bit checksum computation to hardware.
686 * If @csum_l3 is set then the packet's L3 checksum is
687 * updated. Similarly, if @csum_l4 is set the L4
688 * checksum is updated. If @encap is set then encap header
689 * checksums are also updated.
690 *
691 * IONIC_TXQ_DESC_OPCODE_TSO:
692 * Device performs TCP segmentation offload
693 * (TSO). @hdr_len is the number of bytes
694 * to the end of TCP header (the offset to
695 * the TCP payload). @mss is the desired
696 * MSS, the TCP payload length for each
697 * segment. The device will calculate/
698 * insert IP (IPv4 only) and TCP checksums
699 * for each segment. In the first data
700 * buffer containing the header template,
701 * the driver will set IPv4 checksum to 0
702 * and preload TCP checksum with the IP
703 * pseudo header calculated with IP length = 0.
704 *
705 * Supported tunnel encapsulations are IPIP,
706 * layer-3 GRE, and UDP. @hdr_len includes
707 * both outer and inner headers. The driver
708 * will set IPv4 checksum to zero and
709 * preload TCP checksum with IP pseudo
710 * header on the inner header.
711 *
712 * TCP ECN offload is supported. The device
713 * will set CWR flag in the first segment if
714 * CWR is set in the template header, and
715 * clear CWR in remaining segments.
716 * @flags:
717 * vlan:
718 * Insert an L2 VLAN header using @vlan_tci
719 * encap:
720 * Calculate encap header checksum
721 * csum_l3:
722 * Compute L3 header checksum
723 * csum_l4:
724 * Compute L4 header checksum
725 * tso_sot:
726 * TSO start
727 * tso_eot:
728 * TSO end
729 * @num_sg_elems: Number of scatter-gather elements in SG
730 * descriptor
731 * @addr: First data buffer's DMA address
732 * (Subsequent data buffers are on txq_sg_desc)
733 * @len: First data buffer's length, in bytes
734 * @vlan_tci: VLAN tag to insert in the packet (if requested
735 * by @V-bit). Includes .1p and .1q tags
736 * @hdr_len: Length of packet headers, including
737 * encapsulating outer header, if applicable
738 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and
739 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for
740 * all other modes. For
741 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
742 * of headers up to inner-most L4 header. For
743 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to
744 * inner-most L4 payload, so inclusive of
745 * inner-most L4 header.
746 * @mss: Desired MSS value for TSO; only applicable for
747 * IONIC_TXQ_DESC_OPCODE_TSO
748 * @csum_start: Offset from packet to first byte checked in L4 checksum
749 * @csum_offset: Offset from csum_start to L4 checksum field
750 */
751 struct ionic_txq_desc {
752 __le64 cmd;
753 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf
754 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4
755 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf
756 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0
757 #define IONIC_TXQ_DESC_NSGE_MASK 0xf
758 #define IONIC_TXQ_DESC_NSGE_SHIFT 8
759 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
760 #define IONIC_TXQ_DESC_ADDR_SHIFT 12
761
762 /* common flags */
763 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1
764 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
765
766 /* flags for csum_hw opcode */
767 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
768 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
769
770 /* flags for tso opcode */
771 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
772 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
773
774 __le16 len;
775 union {
776 __le16 vlan_tci;
777 __le16 hword0;
778 };
779 union {
780 __le16 csum_start;
781 __le16 hdr_len;
782 __le16 hword1;
783 };
784 union {
785 __le16 csum_offset;
786 __le16 mss;
787 __le16 hword2;
788 };
789 };
790
encode_txq_desc_cmd(u8 opcode,u8 flags,u8 nsge,u64 addr)791 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
792 u8 nsge, u64 addr)
793 {
794 u64 cmd;
795
796 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) <<
797 IONIC_TXQ_DESC_OPCODE_SHIFT;
798 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) <<
799 IONIC_TXQ_DESC_FLAGS_SHIFT;
800 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) <<
801 IONIC_TXQ_DESC_NSGE_SHIFT;
802 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) <<
803 IONIC_TXQ_DESC_ADDR_SHIFT;
804
805 return cmd;
806 };
807
808 static inline void
decode_txq_desc_cmd(u64 cmd,u8 * opcode,u8 * flags,u8 * nsge,u64 * addr)809 decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
810 u8 *nsge, u64 *addr)
811 {
812 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) &
813 IONIC_TXQ_DESC_OPCODE_MASK;
814 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) &
815 IONIC_TXQ_DESC_FLAGS_MASK;
816 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) &
817 IONIC_TXQ_DESC_NSGE_MASK;
818 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) &
819 IONIC_TXQ_DESC_ADDR_MASK;
820 };
821
822 /**
823 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element
824 * @addr: DMA address of SG element data buffer
825 * @len: Length of SG element data buffer, in bytes
826 */
827 struct ionic_txq_sg_elem {
828 __le64 addr;
829 __le16 len;
830 __le16 rsvd[3];
831 };
832
833 /**
834 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
835 * @elems: Scatter-gather elements
836 */
837 struct ionic_txq_sg_desc {
838 #define IONIC_TX_MAX_SG_ELEMS 8
839 #define IONIC_TX_SG_DESC_STRIDE 8
840 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
841 };
842
843 struct ionic_txq_sg_desc_v1 {
844 #define IONIC_TX_MAX_SG_ELEMS_V1 15
845 #define IONIC_TX_SG_DESC_STRIDE_V1 16
846 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
847 };
848
849 /**
850 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
851 * @status: Status of the command (enum ionic_status_code)
852 * @comp_index: Index in the descriptor ring for which this is the completion
853 * @color: Color bit
854 */
855 struct ionic_txq_comp {
856 u8 status;
857 u8 rsvd;
858 __le16 comp_index;
859 u8 rsvd2[11];
860 u8 color;
861 };
862
863 enum ionic_rxq_desc_opcode {
864 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
865 IONIC_RXQ_DESC_OPCODE_SG = 1,
866 };
867
868 /**
869 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
870 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*:
871 *
872 * IONIC_RXQ_DESC_OPCODE_SIMPLE:
873 * Receive full packet into data buffer
874 * starting at @addr. Results of
875 * receive, including actual bytes received,
876 * are recorded in Rx completion descriptor.
877 *
878 * @len: Data buffer's length, in bytes
879 * @addr: Data buffer's DMA address
880 */
881 struct ionic_rxq_desc {
882 u8 opcode;
883 u8 rsvd[5];
884 __le16 len;
885 __le64 addr;
886 };
887
888 /**
889 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element
890 * @addr: DMA address of SG element data buffer
891 * @len: Length of SG element data buffer, in bytes
892 */
893 struct ionic_rxq_sg_elem {
894 __le64 addr;
895 __le16 len;
896 __le16 rsvd[3];
897 };
898
899 /**
900 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
901 * @elems: Scatter-gather elements
902 */
903 struct ionic_rxq_sg_desc {
904 #define IONIC_RX_MAX_SG_ELEMS 8
905 #define IONIC_RX_SG_DESC_STRIDE 8
906 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
907 };
908
909 /**
910 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
911 * @status: Status of the command (enum ionic_status_code)
912 * @num_sg_elems: Number of SG elements used by this descriptor
913 * @comp_index: Index in the descriptor ring for which this is the completion
914 * @rss_hash: 32-bit RSS hash
915 * @csum: 16-bit sum of the packet's L2 payload
916 * If the packet's L2 payload is odd length, an extra
917 * zero-value byte is included in the @csum calculation but
918 * not included in @len.
919 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is
920 * set. Includes .1p and .1q tags.
921 * @len: Received packet length, in bytes. Excludes FCS.
922 * @csum_calc L2 payload checksum is computed or not
923 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*:
924 *
925 * IONIC_RXQ_COMP_CSUM_F_TCP_OK:
926 * The TCP checksum calculated by the device
927 * matched the checksum in the receive packet's
928 * TCP header.
929 *
930 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD:
931 * The TCP checksum calculated by the device did
932 * not match the checksum in the receive packet's
933 * TCP header.
934 *
935 * IONIC_RXQ_COMP_CSUM_F_UDP_OK:
936 * The UDP checksum calculated by the device
937 * matched the checksum in the receive packet's
938 * UDP header
939 *
940 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD:
941 * The UDP checksum calculated by the device did
942 * not match the checksum in the receive packet's
943 * UDP header.
944 *
945 * IONIC_RXQ_COMP_CSUM_F_IP_OK:
946 * The IPv4 checksum calculated by the device
947 * matched the checksum in the receive packet's
948 * first IPv4 header. If the receive packet
949 * contains both a tunnel IPv4 header and a
950 * transport IPv4 header, the device validates the
951 * checksum for the both IPv4 headers.
952 *
953 * IONIC_RXQ_COMP_CSUM_F_IP_BAD:
954 * The IPv4 checksum calculated by the device did
955 * not match the checksum in the receive packet's
956 * first IPv4 header. If the receive packet
957 * contains both a tunnel IPv4 header and a
958 * transport IPv4 header, the device validates the
959 * checksum for both IP headers.
960 *
961 * IONIC_RXQ_COMP_CSUM_F_VLAN:
962 * The VLAN header was stripped and placed in @vlan_tci.
963 *
964 * IONIC_RXQ_COMP_CSUM_F_CALC:
965 * The checksum was calculated by the device.
966 *
967 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
968 */
969 struct ionic_rxq_comp {
970 u8 status;
971 u8 num_sg_elems;
972 __le16 comp_index;
973 __le32 rss_hash;
974 __le16 csum;
975 __le16 vlan_tci;
976 __le16 len;
977 u8 csum_flags;
978 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
979 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
980 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
981 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
982 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
983 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
984 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
985 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
986 u8 pkt_type_color;
987 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
988 };
989
990 enum ionic_pkt_type {
991 IONIC_PKT_TYPE_NON_IP = 0x00,
992 IONIC_PKT_TYPE_IPV4 = 0x01,
993 IONIC_PKT_TYPE_IPV4_TCP = 0x03,
994 IONIC_PKT_TYPE_IPV4_UDP = 0x05,
995 IONIC_PKT_TYPE_IPV6 = 0x08,
996 IONIC_PKT_TYPE_IPV6_TCP = 0x18,
997 IONIC_PKT_TYPE_IPV6_UDP = 0x28,
998 /* below types are only used if encap offloads are enabled on lif */
999 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
1000 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
1001 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
1002 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
1003 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
1004 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
1005 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1006 };
1007
1008 enum ionic_eth_hw_features {
1009 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1010 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1011 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1012 IONIC_ETH_HW_RX_HASH = BIT(3),
1013 IONIC_ETH_HW_RX_CSUM = BIT(4),
1014 IONIC_ETH_HW_TX_SG = BIT(5),
1015 IONIC_ETH_HW_RX_SG = BIT(6),
1016 IONIC_ETH_HW_TX_CSUM = BIT(7),
1017 IONIC_ETH_HW_TSO = BIT(8),
1018 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1019 IONIC_ETH_HW_TSO_ECN = BIT(10),
1020 IONIC_ETH_HW_TSO_GRE = BIT(11),
1021 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1022 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1023 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1024 IONIC_ETH_HW_TSO_UDP = BIT(15),
1025 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1026 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1027 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1028 IONIC_ETH_HW_TSO_GENEVE = BIT(19)
1029 };
1030
1031 /**
1032 * struct ionic_q_control_cmd - Queue control command
1033 * @opcode: opcode
1034 * @type: Queue type
1035 * @lif_index: LIF index
1036 * @index: Queue index
1037 * @oper: Operation (enum ionic_q_control_oper)
1038 */
1039 struct ionic_q_control_cmd {
1040 u8 opcode;
1041 u8 type;
1042 __le16 lif_index;
1043 __le32 index;
1044 u8 oper;
1045 u8 rsvd[55];
1046 };
1047
1048 typedef struct ionic_admin_comp ionic_q_control_comp;
1049
1050 enum ionic_q_control_oper {
1051 IONIC_Q_DISABLE = 0,
1052 IONIC_Q_ENABLE = 1,
1053 IONIC_Q_HANG_RESET = 2,
1054 };
1055
1056 /**
1057 * enum ionic_phy_type - Physical connection type
1058 * @IONIC_PHY_TYPE_NONE: No PHY installed
1059 * @IONIC_PHY_TYPE_COPPER: Copper PHY
1060 * @IONIC_PHY_TYPE_FIBER: Fiber PHY
1061 */
1062 enum ionic_phy_type {
1063 IONIC_PHY_TYPE_NONE = 0,
1064 IONIC_PHY_TYPE_COPPER = 1,
1065 IONIC_PHY_TYPE_FIBER = 2,
1066 };
1067
1068 /**
1069 * enum ionic_xcvr_state - Transceiver status
1070 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed
1071 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted
1072 * @IONIC_XCVR_STATE_PENDING: Transceiver pending
1073 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read
1074 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error
1075 */
1076 enum ionic_xcvr_state {
1077 IONIC_XCVR_STATE_REMOVED = 0,
1078 IONIC_XCVR_STATE_INSERTED = 1,
1079 IONIC_XCVR_STATE_PENDING = 2,
1080 IONIC_XCVR_STATE_SPROM_READ = 3,
1081 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1082 };
1083
1084 /**
1085 * enum ionic_xcvr_pid - Supported link modes
1086 */
1087 enum ionic_xcvr_pid {
1088 IONIC_XCVR_PID_UNKNOWN = 0,
1089
1090 /* CU */
1091 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1092 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1093 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1094 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1095 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1096
1097 /* Fiber */
1098 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1099 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1100 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1101 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1102 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1103 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1104 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1105 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1106 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1107 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1108 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1109 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1110 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1111 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1112 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1113 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1114 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1115 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1116 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1117 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1118 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1119 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1120 };
1121
1122 /**
1123 * enum ionic_port_admin_state - Port config state
1124 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured
1125 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled
1126 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled
1127 */
1128 enum ionic_port_admin_state {
1129 IONIC_PORT_ADMIN_STATE_NONE = 0,
1130 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1131 IONIC_PORT_ADMIN_STATE_UP = 2,
1132 };
1133
1134 /**
1135 * enum ionic_port_oper_status - Port operational status
1136 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled
1137 * @IONIC_PORT_OPER_STATUS_UP: Port link status up
1138 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down
1139 */
1140 enum ionic_port_oper_status {
1141 IONIC_PORT_OPER_STATUS_NONE = 0,
1142 IONIC_PORT_OPER_STATUS_UP = 1,
1143 IONIC_PORT_OPER_STATUS_DOWN = 2,
1144 };
1145
1146 /**
1147 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes
1148 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled
1149 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC
1150 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC
1151 */
1152 enum ionic_port_fec_type {
1153 IONIC_PORT_FEC_TYPE_NONE = 0,
1154 IONIC_PORT_FEC_TYPE_FC = 1,
1155 IONIC_PORT_FEC_TYPE_RS = 2,
1156 };
1157
1158 /**
1159 * enum ionic_port_pause_type - Ethernet pause (flow control) modes
1160 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause
1161 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause
1162 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control
1163 */
1164 enum ionic_port_pause_type {
1165 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1166 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1167 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1168 };
1169
1170 /**
1171 * enum ionic_port_loopback_mode - Loopback modes
1172 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback
1173 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback
1174 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback
1175 */
1176 enum ionic_port_loopback_mode {
1177 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1178 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1179 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1180 };
1181
1182 /**
1183 * struct ionic_xcvr_status - Transceiver Status information
1184 * @state: Transceiver status (enum ionic_xcvr_state)
1185 * @phy: Physical connection type (enum ionic_phy_type)
1186 * @pid: Transceiver link mode (enum ionic_xcvr_pid)
1187 * @sprom: Transceiver sprom contents
1188 */
1189 struct ionic_xcvr_status {
1190 u8 state;
1191 u8 phy;
1192 __le16 pid;
1193 u8 sprom[256];
1194 };
1195
1196 /**
1197 * union ionic_port_config - Port configuration
1198 * @speed: port speed (in Mbps)
1199 * @mtu: mtu
1200 * @state: port admin state (enum ionic_port_admin_state)
1201 * @an_enable: autoneg enable
1202 * @fec_type: fec type (enum ionic_port_fec_type)
1203 * @pause_type: pause type (enum ionic_port_pause_type)
1204 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode)
1205 */
1206 union ionic_port_config {
1207 struct {
1208 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */
1209 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */
1210 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */
1211 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */
1212 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */
1213 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */
1214 __le32 speed;
1215 __le32 mtu;
1216 u8 state;
1217 u8 an_enable;
1218 u8 fec_type;
1219 #define IONIC_PAUSE_TYPE_MASK 0x0f
1220 #define IONIC_PAUSE_FLAGS_MASK 0xf0
1221 #define IONIC_PAUSE_F_TX 0x10
1222 #define IONIC_PAUSE_F_RX 0x20
1223 u8 pause_type;
1224 u8 loopback_mode;
1225 };
1226 __le32 words[64];
1227 };
1228
1229 /**
1230 * struct ionic_port_status - Port Status information
1231 * @status: link status (enum ionic_port_oper_status)
1232 * @id: port id
1233 * @speed: link speed (in Mbps)
1234 * @link_down_count: number of times link went from up to down
1235 * @fec_type: fec type (enum ionic_port_fec_type)
1236 * @xcvr: transceiver status
1237 */
1238 struct ionic_port_status {
1239 __le32 id;
1240 __le32 speed;
1241 u8 status;
1242 __le16 link_down_count;
1243 u8 fec_type;
1244 u8 rsvd[48];
1245 struct ionic_xcvr_status xcvr;
1246 } __rte_packed;
1247
1248 /**
1249 * struct ionic_port_identify_cmd - Port identify command
1250 * @opcode: opcode
1251 * @index: port index
1252 * @ver: Highest version of identify supported by driver
1253 */
1254 struct ionic_port_identify_cmd {
1255 u8 opcode;
1256 u8 index;
1257 u8 ver;
1258 u8 rsvd[61];
1259 };
1260
1261 /**
1262 * struct ionic_port_identify_comp - Port identify command completion
1263 * @status: Status of the command (enum ionic_status_code)
1264 * @ver: Version of identify returned by device
1265 */
1266 struct ionic_port_identify_comp {
1267 u8 status;
1268 u8 ver;
1269 u8 rsvd[14];
1270 };
1271
1272 /**
1273 * struct ionic_port_init_cmd - Port initialization command
1274 * @opcode: opcode
1275 * @index: port index
1276 * @info_pa: destination address for port info (struct ionic_port_info)
1277 */
1278 struct ionic_port_init_cmd {
1279 u8 opcode;
1280 u8 index;
1281 u8 rsvd[6];
1282 __le64 info_pa;
1283 u8 rsvd2[48];
1284 };
1285
1286 /**
1287 * struct ionic_port_init_comp - Port initialization command completion
1288 * @status: Status of the command (enum ionic_status_code)
1289 */
1290 struct ionic_port_init_comp {
1291 u8 status;
1292 u8 rsvd[15];
1293 };
1294
1295 /**
1296 * struct ionic_port_reset_cmd - Port reset command
1297 * @opcode: opcode
1298 * @index: port index
1299 */
1300 struct ionic_port_reset_cmd {
1301 u8 opcode;
1302 u8 index;
1303 u8 rsvd[62];
1304 };
1305
1306 /**
1307 * struct ionic_port_reset_comp - Port reset command completion
1308 * @status: Status of the command (enum ionic_status_code)
1309 */
1310 struct ionic_port_reset_comp {
1311 u8 status;
1312 u8 rsvd[15];
1313 };
1314
1315 /**
1316 * enum ionic_stats_ctl_cmd - List of commands for stats control
1317 * @IONIC_STATS_CTL_RESET: Reset statistics
1318 */
1319 enum ionic_stats_ctl_cmd {
1320 IONIC_STATS_CTL_RESET = 0,
1321 };
1322
1323 /**
1324 * enum ionic_port_attr - List of device attributes
1325 * @IONIC_PORT_ATTR_STATE: Port state attribute
1326 * @IONIC_PORT_ATTR_SPEED: Port speed attribute
1327 * @IONIC_PORT_ATTR_MTU: Port MTU attribute
1328 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute
1329 * @IONIC_PORT_ATTR_FEC: Port FEC attribute
1330 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute
1331 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute
1332 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
1333 */
1334 enum ionic_port_attr {
1335 IONIC_PORT_ATTR_STATE = 0,
1336 IONIC_PORT_ATTR_SPEED = 1,
1337 IONIC_PORT_ATTR_MTU = 2,
1338 IONIC_PORT_ATTR_AUTONEG = 3,
1339 IONIC_PORT_ATTR_FEC = 4,
1340 IONIC_PORT_ATTR_PAUSE = 5,
1341 IONIC_PORT_ATTR_LOOPBACK = 6,
1342 IONIC_PORT_ATTR_STATS_CTRL = 7,
1343 };
1344
1345 /**
1346 * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1347 * @opcode: Opcode
1348 * @index: Port index
1349 * @attr: Attribute type (enum ionic_port_attr)
1350 * @state: Port state
1351 * @speed: Port speed
1352 * @mtu: Port MTU
1353 * @an_enable: Port autonegotiation setting
1354 * @fec_type: Port FEC type setting
1355 * @pause_type: Port pause type setting
1356 * @loopback_mode: Port loopback mode
1357 * @stats_ctl: Port stats setting
1358 */
1359 struct ionic_port_setattr_cmd {
1360 u8 opcode;
1361 u8 index;
1362 u8 attr;
1363 u8 rsvd;
1364 union {
1365 u8 state;
1366 __le32 speed;
1367 __le32 mtu;
1368 u8 an_enable;
1369 u8 fec_type;
1370 u8 pause_type;
1371 u8 loopback_mode;
1372 u8 stats_ctl;
1373 u8 rsvd2[60];
1374 };
1375 };
1376
1377 /**
1378 * struct ionic_port_setattr_comp - Port set attr command completion
1379 * @status: Status of the command (enum ionic_status_code)
1380 * @color: Color bit
1381 */
1382 struct ionic_port_setattr_comp {
1383 u8 status;
1384 u8 rsvd[14];
1385 u8 color;
1386 };
1387
1388 /**
1389 * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1390 * @opcode: Opcode
1391 * @index: port index
1392 * @attr: Attribute type (enum ionic_port_attr)
1393 */
1394 struct ionic_port_getattr_cmd {
1395 u8 opcode;
1396 u8 index;
1397 u8 attr;
1398 u8 rsvd[61];
1399 };
1400
1401 /**
1402 * struct ionic_port_getattr_comp - Port get attr command completion
1403 * @status: Status of the command (enum ionic_status_code)
1404 * @state: Port state
1405 * @speed: Port speed
1406 * @mtu: Port MTU
1407 * @an_enable: Port autonegotiation setting
1408 * @fec_type: Port FEC type setting
1409 * @pause_type: Port pause type setting
1410 * @loopback_mode: Port loopback mode
1411 * @color: Color bit
1412 */
1413 struct ionic_port_getattr_comp {
1414 u8 status;
1415 u8 rsvd[3];
1416 union {
1417 u8 state;
1418 __le32 speed;
1419 __le32 mtu;
1420 u8 an_enable;
1421 u8 fec_type;
1422 u8 pause_type;
1423 u8 loopback_mode;
1424 u8 rsvd2[11];
1425 } __rte_packed;
1426 u8 color;
1427 };
1428
1429 /**
1430 * struct ionic_lif_status - LIF status register
1431 * @eid: most recent NotifyQ event id
1432 * @port_num: port the LIF is connected to
1433 * @link_status: port status (enum ionic_port_oper_status)
1434 * @link_speed: speed of link in Mbps
1435 * @link_down_count: number of times link went from up to down
1436 */
1437 struct ionic_lif_status {
1438 __le64 eid;
1439 u8 port_num;
1440 u8 rsvd;
1441 __le16 link_status;
1442 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
1443 __le16 link_down_count;
1444 u8 rsvd2[46];
1445 };
1446
1447 /**
1448 * struct ionic_lif_reset_cmd - LIF reset command
1449 * @opcode: opcode
1450 * @index: LIF index
1451 */
1452 struct ionic_lif_reset_cmd {
1453 u8 opcode;
1454 u8 rsvd;
1455 __le16 index;
1456 __le32 rsvd2[15];
1457 };
1458
1459 typedef struct ionic_admin_comp ionic_lif_reset_comp;
1460
1461 enum ionic_dev_state {
1462 IONIC_DEV_DISABLE = 0,
1463 IONIC_DEV_ENABLE = 1,
1464 IONIC_DEV_HANG_RESET = 2,
1465 };
1466
1467 /**
1468 * enum ionic_dev_attr - List of device attributes
1469 * @IONIC_DEV_ATTR_STATE: Device state attribute
1470 * @IONIC_DEV_ATTR_NAME: Device name attribute
1471 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes
1472 */
1473 enum ionic_dev_attr {
1474 IONIC_DEV_ATTR_STATE = 0,
1475 IONIC_DEV_ATTR_NAME = 1,
1476 IONIC_DEV_ATTR_FEATURES = 2,
1477 };
1478
1479 /**
1480 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1481 * @opcode: Opcode
1482 * @attr: Attribute type (enum ionic_dev_attr)
1483 * @state: Device state (enum ionic_dev_state)
1484 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated
1485 * @features: Device features
1486 */
1487 struct ionic_dev_setattr_cmd {
1488 u8 opcode;
1489 u8 attr;
1490 __le16 rsvd;
1491 union {
1492 u8 state;
1493 char name[IONIC_IFNAMSIZ];
1494 __le64 features;
1495 u8 rsvd2[60];
1496 } __rte_packed;
1497 };
1498
1499 /**
1500 * struct ionic_dev_setattr_comp - Device set attr command completion
1501 * @status: Status of the command (enum ionic_status_code)
1502 * @features: Device features
1503 * @color: Color bit
1504 */
1505 struct ionic_dev_setattr_comp {
1506 u8 status;
1507 u8 rsvd[3];
1508 union {
1509 __le64 features;
1510 u8 rsvd2[11];
1511 } __rte_packed;
1512 u8 color;
1513 };
1514
1515 /**
1516 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1517 * @opcode: opcode
1518 * @attr: Attribute type (enum ionic_dev_attr)
1519 */
1520 struct ionic_dev_getattr_cmd {
1521 u8 opcode;
1522 u8 attr;
1523 u8 rsvd[62];
1524 };
1525
1526 /**
1527 * struct ionic_dev_setattr_comp - Device set attr command completion
1528 * @status: Status of the command (enum ionic_status_code)
1529 * @features: Device features
1530 * @color: Color bit
1531 */
1532 struct ionic_dev_getattr_comp {
1533 u8 status;
1534 u8 rsvd[3];
1535 union {
1536 __le64 features;
1537 u8 rsvd2[11];
1538 } __rte_packed;
1539 u8 color;
1540 };
1541
1542 /**
1543 * RSS parameters
1544 */
1545 #define IONIC_RSS_HASH_KEY_SIZE 40
1546
1547 enum ionic_rss_hash_types {
1548 IONIC_RSS_TYPE_IPV4 = BIT(0),
1549 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1550 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1551 IONIC_RSS_TYPE_IPV6 = BIT(3),
1552 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1553 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1554 };
1555
1556 /**
1557 * enum ionic_lif_attr - List of LIF attributes
1558 * @IONIC_LIF_ATTR_STATE: LIF state attribute
1559 * @IONIC_LIF_ATTR_NAME: LIF name attribute
1560 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute
1561 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute
1562 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute
1563 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute
1564 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute
1565 */
1566 enum ionic_lif_attr {
1567 IONIC_LIF_ATTR_STATE = 0,
1568 IONIC_LIF_ATTR_NAME = 1,
1569 IONIC_LIF_ATTR_MTU = 2,
1570 IONIC_LIF_ATTR_MAC = 3,
1571 IONIC_LIF_ATTR_FEATURES = 4,
1572 IONIC_LIF_ATTR_RSS = 5,
1573 IONIC_LIF_ATTR_STATS_CTRL = 6,
1574 };
1575
1576 /**
1577 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1578 * @opcode: Opcode
1579 * @attr: Attribute type (enum ionic_lif_attr)
1580 * @index: LIF index
1581 * @state: LIF state (enum ionic_lif_state)
1582 * @name: The netdev name string, 0 terminated
1583 * @mtu: Mtu
1584 * @mac: Station mac
1585 * @features: Features (enum ionic_eth_hw_features)
1586 * @rss: RSS properties
1587 * @types: The hash types to enable (see rss_hash_types)
1588 * @key: The hash secret key
1589 * @addr: Address for the indirection table shared memory
1590 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd)
1591 */
1592 struct ionic_lif_setattr_cmd {
1593 u8 opcode;
1594 u8 attr;
1595 __le16 index;
1596 union {
1597 u8 state;
1598 char name[IONIC_IFNAMSIZ];
1599 __le32 mtu;
1600 u8 mac[6];
1601 __le64 features;
1602 struct {
1603 __le16 types;
1604 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1605 u8 rsvd[6];
1606 __le64 addr;
1607 } rss;
1608 u8 stats_ctl;
1609 u8 rsvd[60];
1610 } __rte_packed;
1611 };
1612
1613 /**
1614 * struct ionic_lif_setattr_comp - LIF set attr command completion
1615 * @status: Status of the command (enum ionic_status_code)
1616 * @comp_index: Index in the descriptor ring for which this is the completion
1617 * @features: features (enum ionic_eth_hw_features)
1618 * @color: Color bit
1619 */
1620 struct ionic_lif_setattr_comp {
1621 u8 status;
1622 u8 rsvd;
1623 __le16 comp_index;
1624 union {
1625 __le64 features;
1626 u8 rsvd2[11];
1627 } __rte_packed;
1628 u8 color;
1629 };
1630
1631 /**
1632 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1633 * @opcode: Opcode
1634 * @attr: Attribute type (enum ionic_lif_attr)
1635 * @index: LIF index
1636 */
1637 struct ionic_lif_getattr_cmd {
1638 u8 opcode;
1639 u8 attr;
1640 __le16 index;
1641 u8 rsvd[60];
1642 };
1643
1644 /**
1645 * struct ionic_lif_getattr_comp - LIF get attr command completion
1646 * @status: Status of the command (enum ionic_status_code)
1647 * @comp_index: Index in the descriptor ring for which this is the completion
1648 * @state: LIF state (enum ionic_lif_state)
1649 * @name: The netdev name string, 0 terminated
1650 * @mtu: Mtu
1651 * @mac: Station mac
1652 * @features: Features (enum ionic_eth_hw_features)
1653 * @color: Color bit
1654 */
1655 struct ionic_lif_getattr_comp {
1656 u8 status;
1657 u8 rsvd;
1658 __le16 comp_index;
1659 union {
1660 u8 state;
1661 __le32 mtu;
1662 u8 mac[6];
1663 __le64 features;
1664 u8 rsvd2[11];
1665 } __rte_packed;
1666 u8 color;
1667 };
1668
1669 enum ionic_rx_mode {
1670 IONIC_RX_MODE_F_UNICAST = BIT(0),
1671 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1672 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1673 IONIC_RX_MODE_F_PROMISC = BIT(3),
1674 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1675 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
1676 };
1677
1678 /**
1679 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
1680 * @opcode: opcode
1681 * @lif_index: LIF index
1682 * @rx_mode: Rx mode flags:
1683 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets
1684 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets
1685 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets
1686 * IONIC_RX_MODE_F_PROMISC: Accept any packets
1687 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets
1688 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets
1689 */
1690 struct ionic_rx_mode_set_cmd {
1691 u8 opcode;
1692 u8 rsvd;
1693 __le16 lif_index;
1694 __le16 rx_mode;
1695 __le16 rsvd2[29];
1696 };
1697
1698 typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1699
1700 enum ionic_rx_filter_match_type {
1701 IONIC_RX_FILTER_MATCH_VLAN = 0,
1702 IONIC_RX_FILTER_MATCH_MAC,
1703 IONIC_RX_FILTER_MATCH_MAC_VLAN,
1704 };
1705
1706 /**
1707 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
1708 * @opcode: opcode
1709 * @qtype: Queue type
1710 * @lif_index: LIF index
1711 * @qid: Queue ID
1712 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)
1713 * @vlan: VLAN filter
1714 * @vlan: VLAN ID
1715 * @mac: MAC filter
1716 * @addr: MAC address (network-byte order)
1717 * @mac_vlan: MACVLAN filter
1718 * @vlan: VLAN ID
1719 * @addr: MAC address (network-byte order)
1720 */
1721 struct ionic_rx_filter_add_cmd {
1722 u8 opcode;
1723 u8 qtype;
1724 __le16 lif_index;
1725 __le32 qid;
1726 __le16 match;
1727 union {
1728 struct {
1729 __le16 vlan;
1730 } vlan;
1731 struct {
1732 u8 addr[6];
1733 } mac;
1734 struct {
1735 __le16 vlan;
1736 u8 addr[6];
1737 } mac_vlan;
1738 u8 rsvd[54];
1739 };
1740 };
1741
1742 /**
1743 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
1744 * @status: Status of the command (enum ionic_status_code)
1745 * @comp_index: Index in the descriptor ring for which this is the completion
1746 * @filter_id: Filter ID
1747 * @color: Color bit
1748 */
1749 struct ionic_rx_filter_add_comp {
1750 u8 status;
1751 u8 rsvd;
1752 __le16 comp_index;
1753 __le32 filter_id;
1754 u8 rsvd2[7];
1755 u8 color;
1756 };
1757
1758 /**
1759 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
1760 * @opcode: opcode
1761 * @lif_index: LIF index
1762 * @filter_id: Filter ID
1763 */
1764 struct ionic_rx_filter_del_cmd {
1765 u8 opcode;
1766 u8 rsvd;
1767 __le16 lif_index;
1768 __le32 filter_id;
1769 u8 rsvd2[56];
1770 };
1771
1772 typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1773
1774 enum ionic_vf_attr {
1775 IONIC_VF_ATTR_SPOOFCHK = 1,
1776 IONIC_VF_ATTR_TRUST = 2,
1777 IONIC_VF_ATTR_MAC = 3,
1778 IONIC_VF_ATTR_LINKSTATE = 4,
1779 IONIC_VF_ATTR_VLAN = 5,
1780 IONIC_VF_ATTR_RATE = 6,
1781 IONIC_VF_ATTR_STATSADDR = 7,
1782 };
1783
1784 /**
1785 * enum ionic_vf_link_status - Virtual Function link status
1786 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink
1787 * @IONIC_VF_LINK_STATUS_UP: Link always up
1788 * @IONIC_VF_LINK_STATUS_DOWN: Link always down
1789 */
1790 enum ionic_vf_link_status {
1791 IONIC_VF_LINK_STATUS_AUTO = 0,
1792 IONIC_VF_LINK_STATUS_UP = 1,
1793 IONIC_VF_LINK_STATUS_DOWN = 2,
1794 };
1795
1796 /**
1797 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
1798 * @opcode: Opcode
1799 * @attr: Attribute type (enum ionic_vf_attr)
1800 * @vf_index: VF index
1801 * @macaddr: mac address
1802 * @vlanid: vlan ID
1803 * @maxrate: max Tx rate in Mbps
1804 * @spoofchk: enable address spoof checking
1805 * @trust: enable VF trust
1806 * @linkstate: set link up or down
1807 * @stats_pa: set DMA address for VF stats
1808 */
1809 struct ionic_vf_setattr_cmd {
1810 u8 opcode;
1811 u8 attr;
1812 __le16 vf_index;
1813 union {
1814 u8 macaddr[6];
1815 __le16 vlanid;
1816 __le32 maxrate;
1817 u8 spoofchk;
1818 u8 trust;
1819 u8 linkstate;
1820 __le64 stats_pa;
1821 u8 pad[60];
1822 } __rte_packed;
1823 };
1824
1825 struct ionic_vf_setattr_comp {
1826 u8 status;
1827 u8 attr;
1828 __le16 vf_index;
1829 __le16 comp_index;
1830 u8 rsvd[9];
1831 u8 color;
1832 };
1833
1834 /**
1835 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
1836 * @opcode: Opcode
1837 * @attr: Attribute type (enum ionic_vf_attr)
1838 * @vf_index: VF index
1839 */
1840 struct ionic_vf_getattr_cmd {
1841 u8 opcode;
1842 u8 attr;
1843 __le16 vf_index;
1844 u8 rsvd[60];
1845 };
1846
1847 struct ionic_vf_getattr_comp {
1848 u8 status;
1849 u8 attr;
1850 __le16 vf_index;
1851 union {
1852 u8 macaddr[6];
1853 __le16 vlanid;
1854 __le32 maxrate;
1855 u8 spoofchk;
1856 u8 trust;
1857 u8 linkstate;
1858 __le64 stats_pa;
1859 u8 pad[11];
1860 } __rte_packed;
1861 u8 color;
1862 };
1863
1864 /**
1865 * struct ionic_qos_identify_cmd - QoS identify command
1866 * @opcode: opcode
1867 * @ver: Highest version of identify supported by driver
1868 *
1869 */
1870 struct ionic_qos_identify_cmd {
1871 u8 opcode;
1872 u8 ver;
1873 u8 rsvd[62];
1874 };
1875
1876 /**
1877 * struct ionic_qos_identify_comp - QoS identify command completion
1878 * @status: Status of the command (enum ionic_status_code)
1879 * @ver: Version of identify returned by device
1880 */
1881 struct ionic_qos_identify_comp {
1882 u8 status;
1883 u8 ver;
1884 u8 rsvd[14];
1885 };
1886
1887 #define IONIC_QOS_TC_MAX 8
1888 #define IONIC_QOS_ALL_TC 0xFF
1889 /* Capri max supported, should be renamed. */
1890 #define IONIC_QOS_CLASS_MAX 7
1891 #define IONIC_QOS_PCP_MAX 8
1892 #define IONIC_QOS_CLASS_NAME_SZ 32
1893 #define IONIC_QOS_DSCP_MAX 64
1894 #define IONIC_QOS_ALL_PCP 0xFF
1895 #define IONIC_DSCP_BLOCK_SIZE 8
1896
1897 /**
1898 * enum ionic_qos_class
1899 */
1900 enum ionic_qos_class {
1901 IONIC_QOS_CLASS_DEFAULT = 0,
1902 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
1903 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
1904 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
1905 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
1906 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
1907 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
1908 };
1909
1910 /**
1911 * enum ionic_qos_class_type - Traffic classification criteria
1912 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS
1913 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP
1914 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP
1915 */
1916 enum ionic_qos_class_type {
1917 IONIC_QOS_CLASS_TYPE_NONE = 0,
1918 IONIC_QOS_CLASS_TYPE_PCP = 1,
1919 IONIC_QOS_CLASS_TYPE_DSCP = 2,
1920 };
1921
1922 /**
1923 * enum ionic_qos_sched_type - QoS class scheduling type
1924 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority
1925 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin
1926 */
1927 enum ionic_qos_sched_type {
1928 IONIC_QOS_SCHED_TYPE_STRICT = 0,
1929 IONIC_QOS_SCHED_TYPE_DWRR = 1,
1930 };
1931
1932 /**
1933 * union ionic_qos_config - QoS configuration structure
1934 * @flags: Configuration flags
1935 * IONIC_QOS_CONFIG_F_ENABLE enable
1936 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop
1937 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
1938 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
1939 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update
1940 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type)
1941 * @class_type: QoS class type (enum ionic_qos_class_type)
1942 * @pause_type: QoS pause type (enum ionic_qos_pause_type)
1943 * @name: QoS class name
1944 * @mtu: MTU of the class
1945 * @pfc_cos: Priority-Flow Control class of service
1946 * @dwrr_weight: QoS class scheduling weight
1947 * @strict_rlmt: Rate limit for strict priority scheduling
1948 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP)
1949 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP)
1950 * @dot1q_pcp: Dot1q pcp value
1951 * @ndscp: Number of valid dscp values in the ip_dscp field
1952 * @ip_dscp: IP dscp values
1953 */
1954 union ionic_qos_config {
1955 struct {
1956 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
1957 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
1958 /* Used to rewrite PCP or DSCP value. */
1959 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
1960 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
1961 /* Non-disruptive TC update */
1962 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
1963 u8 flags;
1964 u8 sched_type;
1965 u8 class_type;
1966 u8 pause_type;
1967 char name[IONIC_QOS_CLASS_NAME_SZ];
1968 __le32 mtu;
1969 /* flow control */
1970 u8 pfc_cos;
1971 /* scheduler */
1972 union {
1973 u8 dwrr_weight;
1974 __le64 strict_rlmt;
1975 };
1976 /* marking */
1977 /* Used to rewrite PCP or DSCP value. */
1978 union {
1979 u8 rw_dot1q_pcp;
1980 u8 rw_ip_dscp;
1981 };
1982 /* classification */
1983 union {
1984 u8 dot1q_pcp;
1985 struct {
1986 u8 ndscp;
1987 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
1988 };
1989 };
1990 } __rte_packed;
1991 __le32 words[64];
1992 };
1993
1994 /**
1995 * union ionic_qos_identity - QoS identity structure
1996 * @version: Version of the identify structure
1997 * @type: QoS system type
1998 * @nclasses: Number of usable QoS classes
1999 * @config: Current configuration of classes
2000 */
2001 union ionic_qos_identity {
2002 struct {
2003 u8 version;
2004 u8 type;
2005 u8 rsvd[62];
2006 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2007 };
2008 __le32 words[478];
2009 };
2010
2011 /**
2012 * struct ionic_qos_init_cmd - QoS config init command
2013 * @opcode: Opcode
2014 * @group: QoS class id
2015 * @info_pa: destination address for qos info
2016 */
2017 struct ionic_qos_init_cmd {
2018 u8 opcode;
2019 u8 group;
2020 u8 rsvd[6];
2021 __le64 info_pa;
2022 u8 rsvd1[48];
2023 };
2024
2025 typedef struct ionic_admin_comp ionic_qos_init_comp;
2026
2027 /**
2028 * struct ionic_qos_reset_cmd - QoS config reset command
2029 * @opcode: Opcode
2030 * @group: QoS class id
2031 */
2032 struct ionic_qos_reset_cmd {
2033 u8 opcode;
2034 u8 group;
2035 u8 rsvd[62];
2036 };
2037
2038 /**
2039 * struct ionic_qos_clear_port_stats_cmd - Qos config reset command
2040 * @opcode: Opcode
2041 */
2042 struct ionic_qos_clear_stats_cmd {
2043 u8 opcode;
2044 u8 group_bitmap;
2045 u8 rsvd[62];
2046 };
2047
2048 typedef struct ionic_admin_comp ionic_qos_reset_comp;
2049
2050 /**
2051 * struct ionic_fw_download_cmd - Firmware download command
2052 * @opcode: opcode
2053 * @addr: dma address of the firmware buffer
2054 * @offset: offset of the firmware buffer within the full image
2055 * @length: number of valid bytes in the firmware buffer
2056 */
2057 struct ionic_fw_download_cmd {
2058 u8 opcode;
2059 u8 rsvd[3];
2060 __le32 offset;
2061 __le64 addr;
2062 __le32 length;
2063 };
2064
2065 typedef struct ionic_admin_comp ionic_fw_download_comp;
2066
2067 /**
2068 * enum ionic_fw_control_oper - FW control operations
2069 * @IONIC_FW_RESET: Reset firmware
2070 * @IONIC_FW_INSTALL: Install firmware
2071 * @IONIC_FW_ACTIVATE: Activate firmware
2072 */
2073 enum ionic_fw_control_oper {
2074 IONIC_FW_RESET = 0,
2075 IONIC_FW_INSTALL = 1,
2076 IONIC_FW_ACTIVATE = 2,
2077 };
2078
2079 /**
2080 * struct ionic_fw_control_cmd - Firmware control command
2081 * @opcode: opcode
2082 * @oper: firmware control operation (enum ionic_fw_control_oper)
2083 * @slot: slot to activate
2084 */
2085 struct ionic_fw_control_cmd {
2086 u8 opcode;
2087 u8 rsvd[3];
2088 u8 oper;
2089 u8 slot;
2090 u8 rsvd1[58];
2091 };
2092
2093 /**
2094 * struct ionic_fw_control_comp - Firmware control completion
2095 * @status: Status of the command (enum ionic_status_code)
2096 * @comp_index: Index in the descriptor ring for which this is the completion
2097 * @slot: Slot where the firmware was installed
2098 * @color: Color bit
2099 */
2100 struct ionic_fw_control_comp {
2101 u8 status;
2102 u8 rsvd;
2103 __le16 comp_index;
2104 u8 slot;
2105 u8 rsvd1[10];
2106 u8 color;
2107 };
2108
2109 /******************************************************************
2110 ******************* RDMA Commands ********************************
2111 ******************************************************************/
2112
2113 /**
2114 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
2115 * @opcode: opcode
2116 * @lif_index: LIF index
2117 *
2118 * There is no RDMA specific dev command completion struct. Completion uses
2119 * the common struct ionic_admin_comp. Only the status is indicated.
2120 * Nonzero status means the LIF does not support RDMA.
2121 **/
2122 struct ionic_rdma_reset_cmd {
2123 u8 opcode;
2124 u8 rsvd;
2125 __le16 lif_index;
2126 u8 rsvd2[60];
2127 };
2128
2129 /**
2130 * struct ionic_rdma_queue_cmd - Create RDMA Queue command
2131 * @opcode: opcode, 52, 53
2132 * @lif_index: LIF index
2133 * @qid_ver: (qid | (RDMA version << 24))
2134 * @cid: intr, eq_id, or cq_id
2135 * @dbid: doorbell page id
2136 * @depth_log2: log base two of queue depth
2137 * @stride_log2: log base two of queue stride
2138 * @dma_addr: address of the queue memory
2139 *
2140 * The same command struct is used to create an RDMA event queue, completion
2141 * queue, or RDMA admin queue. The cid is an interrupt number for an event
2142 * queue, an event queue id for a completion queue, or a completion queue id
2143 * for an RDMA admin queue.
2144 *
2145 * The queue created via a dev command must be contiguous in dma space.
2146 *
2147 * The dev commands are intended only to be used during driver initialization,
2148 * to create queues supporting the RDMA admin queue. Other queues, and other
2149 * types of RDMA resources like memory regions, will be created and registered
2150 * via the RDMA admin queue, and will support a more complete interface
2151 * providing scatter gather lists for larger, scattered queue buffers and
2152 * memory registration.
2153 *
2154 * There is no RDMA specific dev command completion struct. Completion uses
2155 * the common struct ionic_admin_comp. Only the status is indicated.
2156 **/
2157 struct ionic_rdma_queue_cmd {
2158 u8 opcode;
2159 u8 rsvd;
2160 __le16 lif_index;
2161 __le32 qid_ver;
2162 __le32 cid;
2163 __le16 dbid;
2164 u8 depth_log2;
2165 u8 stride_log2;
2166 __le64 dma_addr;
2167 u8 rsvd2[40];
2168 };
2169
2170 /******************************************************************
2171 ******************* Notify Events ********************************
2172 ******************************************************************/
2173
2174 /**
2175 * struct ionic_notifyq_event - Generic event reporting structure
2176 * @eid: event number
2177 * @ecode: event code
2178 * @data: unspecified data about the event
2179 *
2180 * This is the generic event report struct from which the other
2181 * actual events will be formed.
2182 */
2183 struct ionic_notifyq_event {
2184 __le64 eid;
2185 __le16 ecode;
2186 u8 data[54];
2187 };
2188
2189 /**
2190 * struct ionic_link_change_event - Link change event notification
2191 * @eid: event number
2192 * @ecode: event code = IONIC_EVENT_LINK_CHANGE
2193 * @link_status: link up/down, with error bits (enum ionic_port_status)
2194 * @link_speed: speed of the network link
2195 *
2196 * Sent when the network link state changes between UP and DOWN
2197 */
2198 struct ionic_link_change_event {
2199 __le64 eid;
2200 __le16 ecode;
2201 __le16 link_status;
2202 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
2203 u8 rsvd[48];
2204 };
2205
2206 /**
2207 * struct ionic_reset_event - Reset event notification
2208 * @eid: event number
2209 * @ecode: event code = IONIC_EVENT_RESET
2210 * @reset_code: reset type
2211 * @state: 0=pending, 1=complete, 2=error
2212 *
2213 * Sent when the NIC or some subsystem is going to be or
2214 * has been reset.
2215 */
2216 struct ionic_reset_event {
2217 __le64 eid;
2218 __le16 ecode;
2219 u8 reset_code;
2220 u8 state;
2221 u8 rsvd[52];
2222 };
2223
2224 /**
2225 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health
2226 * @eid: event number
2227 * @ecode: event code = IONIC_EVENT_HEARTBEAT
2228 */
2229 struct ionic_heartbeat_event {
2230 __le64 eid;
2231 __le16 ecode;
2232 u8 rsvd[54];
2233 };
2234
2235 /**
2236 * struct ionic_log_event - Sent to notify the driver of an internal error
2237 * @eid: event number
2238 * @ecode: event code = IONIC_EVENT_LOG
2239 * @data: log data
2240 */
2241 struct ionic_log_event {
2242 __le64 eid;
2243 __le16 ecode;
2244 u8 data[54];
2245 };
2246
2247 /**
2248 * struct ionic_xcvr_event - Transceiver change event
2249 * @eid: event number
2250 * @ecode: event code = IONIC_EVENT_XCVR
2251 */
2252 struct ionic_xcvr_event {
2253 __le64 eid;
2254 __le16 ecode;
2255 u8 rsvd[54];
2256 };
2257
2258 /**
2259 * struct ionic_port_stats - Port statistics structure
2260 */
2261 struct ionic_port_stats {
2262 __le64 frames_rx_ok;
2263 __le64 frames_rx_all;
2264 __le64 frames_rx_bad_fcs;
2265 __le64 frames_rx_bad_all;
2266 __le64 octets_rx_ok;
2267 __le64 octets_rx_all;
2268 __le64 frames_rx_unicast;
2269 __le64 frames_rx_multicast;
2270 __le64 frames_rx_broadcast;
2271 __le64 frames_rx_pause;
2272 __le64 frames_rx_bad_length;
2273 __le64 frames_rx_undersized;
2274 __le64 frames_rx_oversized;
2275 __le64 frames_rx_fragments;
2276 __le64 frames_rx_jabber;
2277 __le64 frames_rx_pripause;
2278 __le64 frames_rx_stomped_crc;
2279 __le64 frames_rx_too_long;
2280 __le64 frames_rx_vlan_good;
2281 __le64 frames_rx_dropped;
2282 __le64 frames_rx_less_than_64b;
2283 __le64 frames_rx_64b;
2284 __le64 frames_rx_65b_127b;
2285 __le64 frames_rx_128b_255b;
2286 __le64 frames_rx_256b_511b;
2287 __le64 frames_rx_512b_1023b;
2288 __le64 frames_rx_1024b_1518b;
2289 __le64 frames_rx_1519b_2047b;
2290 __le64 frames_rx_2048b_4095b;
2291 __le64 frames_rx_4096b_8191b;
2292 __le64 frames_rx_8192b_9215b;
2293 __le64 frames_rx_other;
2294 __le64 frames_tx_ok;
2295 __le64 frames_tx_all;
2296 __le64 frames_tx_bad;
2297 __le64 octets_tx_ok;
2298 __le64 octets_tx_total;
2299 __le64 frames_tx_unicast;
2300 __le64 frames_tx_multicast;
2301 __le64 frames_tx_broadcast;
2302 __le64 frames_tx_pause;
2303 __le64 frames_tx_pripause;
2304 __le64 frames_tx_vlan;
2305 __le64 frames_tx_less_than_64b;
2306 __le64 frames_tx_64b;
2307 __le64 frames_tx_65b_127b;
2308 __le64 frames_tx_128b_255b;
2309 __le64 frames_tx_256b_511b;
2310 __le64 frames_tx_512b_1023b;
2311 __le64 frames_tx_1024b_1518b;
2312 __le64 frames_tx_1519b_2047b;
2313 __le64 frames_tx_2048b_4095b;
2314 __le64 frames_tx_4096b_8191b;
2315 __le64 frames_tx_8192b_9215b;
2316 __le64 frames_tx_other;
2317 __le64 frames_tx_pri_0;
2318 __le64 frames_tx_pri_1;
2319 __le64 frames_tx_pri_2;
2320 __le64 frames_tx_pri_3;
2321 __le64 frames_tx_pri_4;
2322 __le64 frames_tx_pri_5;
2323 __le64 frames_tx_pri_6;
2324 __le64 frames_tx_pri_7;
2325 __le64 frames_rx_pri_0;
2326 __le64 frames_rx_pri_1;
2327 __le64 frames_rx_pri_2;
2328 __le64 frames_rx_pri_3;
2329 __le64 frames_rx_pri_4;
2330 __le64 frames_rx_pri_5;
2331 __le64 frames_rx_pri_6;
2332 __le64 frames_rx_pri_7;
2333 __le64 tx_pripause_0_1us_count;
2334 __le64 tx_pripause_1_1us_count;
2335 __le64 tx_pripause_2_1us_count;
2336 __le64 tx_pripause_3_1us_count;
2337 __le64 tx_pripause_4_1us_count;
2338 __le64 tx_pripause_5_1us_count;
2339 __le64 tx_pripause_6_1us_count;
2340 __le64 tx_pripause_7_1us_count;
2341 __le64 rx_pripause_0_1us_count;
2342 __le64 rx_pripause_1_1us_count;
2343 __le64 rx_pripause_2_1us_count;
2344 __le64 rx_pripause_3_1us_count;
2345 __le64 rx_pripause_4_1us_count;
2346 __le64 rx_pripause_5_1us_count;
2347 __le64 rx_pripause_6_1us_count;
2348 __le64 rx_pripause_7_1us_count;
2349 __le64 rx_pause_1us_count;
2350 __le64 frames_tx_truncated;
2351 };
2352
2353 struct ionic_mgmt_port_stats {
2354 __le64 frames_rx_ok;
2355 __le64 frames_rx_all;
2356 __le64 frames_rx_bad_fcs;
2357 __le64 frames_rx_bad_all;
2358 __le64 octets_rx_ok;
2359 __le64 octets_rx_all;
2360 __le64 frames_rx_unicast;
2361 __le64 frames_rx_multicast;
2362 __le64 frames_rx_broadcast;
2363 __le64 frames_rx_pause;
2364 __le64 frames_rx_bad_length;
2365 __le64 frames_rx_undersized;
2366 __le64 frames_rx_oversized;
2367 __le64 frames_rx_fragments;
2368 __le64 frames_rx_jabber;
2369 __le64 frames_rx_64b;
2370 __le64 frames_rx_65b_127b;
2371 __le64 frames_rx_128b_255b;
2372 __le64 frames_rx_256b_511b;
2373 __le64 frames_rx_512b_1023b;
2374 __le64 frames_rx_1024b_1518b;
2375 __le64 frames_rx_gt_1518b;
2376 __le64 frames_rx_fifo_full;
2377 __le64 frames_tx_ok;
2378 __le64 frames_tx_all;
2379 __le64 frames_tx_bad;
2380 __le64 octets_tx_ok;
2381 __le64 octets_tx_total;
2382 __le64 frames_tx_unicast;
2383 __le64 frames_tx_multicast;
2384 __le64 frames_tx_broadcast;
2385 __le64 frames_tx_pause;
2386 };
2387
2388 enum ionic_pb_buffer_drop_stats {
2389 IONIC_BUFFER_INTRINSIC_DROP = 0,
2390 IONIC_BUFFER_DISCARDED,
2391 IONIC_BUFFER_ADMITTED,
2392 IONIC_BUFFER_OUT_OF_CELLS_DROP,
2393 IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2394 IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2395 IONIC_BUFFER_TRUNCATION_DROP,
2396 IONIC_BUFFER_PORT_DISABLED_DROP,
2397 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2398 IONIC_BUFFER_SPAN_TAIL_DROP,
2399 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2400 IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2401 IONIC_BUFFER_INVALID_PORT_DROP,
2402 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2403 IONIC_BUFFER_DROP_MAX,
2404 };
2405
2406 enum ionic_oflow_drop_stats {
2407 IONIC_OFLOW_OCCUPANCY_DROP,
2408 IONIC_OFLOW_EMERGENCY_STOP_DROP,
2409 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2410 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2411 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2412 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2413 IONIC_OFLOW_DROP_MAX,
2414 };
2415
2416 /**
2417 * struct port_pb_stats - packet buffers system stats
2418 * uses ionic_pb_buffer_drop_stats for drop_counts[]
2419 */
2420 struct ionic_port_pb_stats {
2421 __le64 sop_count_in;
2422 __le64 eop_count_in;
2423 __le64 sop_count_out;
2424 __le64 eop_count_out;
2425 __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2426 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2427 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2428 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2429 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2430 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2431 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2432 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2433 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2434 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2435 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2436 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2437 };
2438
2439 /**
2440 * enum ionic_port_type - Port types
2441 * @IONIC_ETH_UNKNOWN: Port type not configured
2442 * @IONIC_ETH_HOST: Port carries ethernet traffic (inband)
2443 * @IONIC_ETH_HOST_MGMT: Port carries mgmt traffic (out-of-band)
2444 * @IONIC_ETH_MNIC_OOB_MGMT:
2445 * @IONIC_ETH_MNIC_INTERNAL_MGMT:
2446 * @IONIC_ETH_MNIC_INBAND_MGMT:
2447 * @IONIC_ETH_MNIC_CPU:
2448 * @IONIC_ETH_MNIC_LEARN:
2449 * @IONIC_ETH_MNIC_CONTROL:
2450 */
2451 enum ionic_port_type {
2452 IONIC_ETH_UNKNOWN,
2453 IONIC_ETH_HOST,
2454 IONIC_ETH_HOST_MGMT,
2455 IONIC_ETH_MNIC_OOB_MGMT,
2456 IONIC_ETH_MNIC_INTERNAL_MGMT,
2457 IONIC_ETH_MNIC_INBAND_MGMT,
2458 IONIC_ETH_MNIC_CPU,
2459 IONIC_ETH_MNIC_LEARN,
2460 IONIC_ETH_MNIC_CONTROL,
2461 };
2462
2463 /**
2464 * struct ionic_port_identity - port identity structure
2465 * @version: identity structure version
2466 * @type: type of port (enum ionic_port_type)
2467 * @num_lanes: number of lanes for the port
2468 * @autoneg: autoneg supported
2469 * @min_frame_size: minimum frame size supported
2470 * @max_frame_size: maximum frame size supported
2471 * @fec_type: supported fec types
2472 * @pause_type: supported pause types
2473 * @loopback_mode: supported loopback mode
2474 * @speeds: supported speeds
2475 * @config: current port configuration
2476 */
2477 union ionic_port_identity {
2478 struct {
2479 u8 version;
2480 u8 type;
2481 u8 num_lanes;
2482 u8 autoneg;
2483 __le32 min_frame_size;
2484 __le32 max_frame_size;
2485 u8 fec_type[4];
2486 u8 pause_type[2];
2487 u8 loopback_mode[2];
2488 __le32 speeds[16];
2489 u8 rsvd2[44];
2490 union ionic_port_config config;
2491 };
2492 __le32 words[478];
2493 };
2494
2495 /**
2496 * struct ionic_port_info - port info structure
2497 * @config: Port configuration data
2498 * @status: Port status data
2499 * @stats: Port statistics data
2500 * @mgmt_stats: Port management statistics data
2501 * @port_pb_drop_stats: uplink pb drop stats
2502 */
2503 struct ionic_port_info {
2504 union ionic_port_config config;
2505 struct ionic_port_status status;
2506 union {
2507 struct ionic_port_stats stats;
2508 struct ionic_mgmt_port_stats mgmt_stats;
2509 };
2510 /* room for pb_stats to start at 2k offset */
2511 u8 rsvd[760];
2512 struct ionic_port_pb_stats pb_stats;
2513 };
2514
2515 /**
2516 * struct ionic_lif_stats - LIF statistics structure
2517 */
2518 struct ionic_lif_stats {
2519 /* RX */
2520 __le64 rx_ucast_bytes;
2521 __le64 rx_ucast_packets;
2522 __le64 rx_mcast_bytes;
2523 __le64 rx_mcast_packets;
2524 __le64 rx_bcast_bytes;
2525 __le64 rx_bcast_packets;
2526 __le64 rsvd0;
2527 __le64 rsvd1;
2528 /* RX drops */
2529 __le64 rx_ucast_drop_bytes;
2530 __le64 rx_ucast_drop_packets;
2531 __le64 rx_mcast_drop_bytes;
2532 __le64 rx_mcast_drop_packets;
2533 __le64 rx_bcast_drop_bytes;
2534 __le64 rx_bcast_drop_packets;
2535 __le64 rx_dma_error;
2536 __le64 rsvd2;
2537 /* TX */
2538 __le64 tx_ucast_bytes;
2539 __le64 tx_ucast_packets;
2540 __le64 tx_mcast_bytes;
2541 __le64 tx_mcast_packets;
2542 __le64 tx_bcast_bytes;
2543 __le64 tx_bcast_packets;
2544 __le64 rsvd3;
2545 __le64 rsvd4;
2546 /* TX drops */
2547 __le64 tx_ucast_drop_bytes;
2548 __le64 tx_ucast_drop_packets;
2549 __le64 tx_mcast_drop_bytes;
2550 __le64 tx_mcast_drop_packets;
2551 __le64 tx_bcast_drop_bytes;
2552 __le64 tx_bcast_drop_packets;
2553 __le64 tx_dma_error;
2554 __le64 rsvd5;
2555 /* Rx Queue/Ring drops */
2556 __le64 rx_queue_disabled;
2557 __le64 rx_queue_empty;
2558 __le64 rx_queue_error;
2559 __le64 rx_desc_fetch_error;
2560 __le64 rx_desc_data_error;
2561 __le64 rsvd6;
2562 __le64 rsvd7;
2563 __le64 rsvd8;
2564 /* Tx Queue/Ring drops */
2565 __le64 tx_queue_disabled;
2566 __le64 tx_queue_error;
2567 __le64 tx_desc_fetch_error;
2568 __le64 tx_desc_data_error;
2569 __le64 tx_queue_empty;
2570 __le64 rsvd10;
2571 __le64 rsvd11;
2572 __le64 rsvd12;
2573
2574 /* RDMA/ROCE TX */
2575 __le64 tx_rdma_ucast_bytes;
2576 __le64 tx_rdma_ucast_packets;
2577 __le64 tx_rdma_mcast_bytes;
2578 __le64 tx_rdma_mcast_packets;
2579 __le64 tx_rdma_cnp_packets;
2580 __le64 rsvd13;
2581 __le64 rsvd14;
2582 __le64 rsvd15;
2583
2584 /* RDMA/ROCE RX */
2585 __le64 rx_rdma_ucast_bytes;
2586 __le64 rx_rdma_ucast_packets;
2587 __le64 rx_rdma_mcast_bytes;
2588 __le64 rx_rdma_mcast_packets;
2589 __le64 rx_rdma_cnp_packets;
2590 __le64 rx_rdma_ecn_packets;
2591 __le64 rsvd16;
2592 __le64 rsvd17;
2593
2594 __le64 rsvd18;
2595 __le64 rsvd19;
2596 __le64 rsvd20;
2597 __le64 rsvd21;
2598 __le64 rsvd22;
2599 __le64 rsvd23;
2600 __le64 rsvd24;
2601 __le64 rsvd25;
2602
2603 __le64 rsvd26;
2604 __le64 rsvd27;
2605 __le64 rsvd28;
2606 __le64 rsvd29;
2607 __le64 rsvd30;
2608 __le64 rsvd31;
2609 __le64 rsvd32;
2610 __le64 rsvd33;
2611
2612 __le64 rsvd34;
2613 __le64 rsvd35;
2614 __le64 rsvd36;
2615 __le64 rsvd37;
2616 __le64 rsvd38;
2617 __le64 rsvd39;
2618 __le64 rsvd40;
2619 __le64 rsvd41;
2620
2621 __le64 rsvd42;
2622 __le64 rsvd43;
2623 __le64 rsvd44;
2624 __le64 rsvd45;
2625 __le64 rsvd46;
2626 __le64 rsvd47;
2627 __le64 rsvd48;
2628 __le64 rsvd49;
2629
2630 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
2631 __le64 rdma_req_rx_pkt_seq_err;
2632 __le64 rdma_req_rx_rnr_retry_err;
2633 __le64 rdma_req_rx_remote_access_err;
2634 __le64 rdma_req_rx_remote_inv_req_err;
2635 __le64 rdma_req_rx_remote_oper_err;
2636 __le64 rdma_req_rx_implied_nak_seq_err;
2637 __le64 rdma_req_rx_cqe_err;
2638 __le64 rdma_req_rx_cqe_flush_err;
2639
2640 __le64 rdma_req_rx_dup_responses;
2641 __le64 rdma_req_rx_invalid_packets;
2642 __le64 rdma_req_tx_local_access_err;
2643 __le64 rdma_req_tx_local_oper_err;
2644 __le64 rdma_req_tx_memory_mgmt_err;
2645 __le64 rsvd52;
2646 __le64 rsvd53;
2647 __le64 rsvd54;
2648
2649 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
2650 __le64 rdma_resp_rx_dup_requests;
2651 __le64 rdma_resp_rx_out_of_buffer;
2652 __le64 rdma_resp_rx_out_of_seq_pkts;
2653 __le64 rdma_resp_rx_cqe_err;
2654 __le64 rdma_resp_rx_cqe_flush_err;
2655 __le64 rdma_resp_rx_local_len_err;
2656 __le64 rdma_resp_rx_inv_request_err;
2657 __le64 rdma_resp_rx_local_qp_oper_err;
2658
2659 __le64 rdma_resp_rx_out_of_atomic_resource;
2660 __le64 rdma_resp_tx_pkt_seq_err;
2661 __le64 rdma_resp_tx_remote_inv_req_err;
2662 __le64 rdma_resp_tx_remote_access_err;
2663 __le64 rdma_resp_tx_remote_oper_err;
2664 __le64 rdma_resp_tx_rnr_retry_err;
2665 __le64 rsvd57;
2666 __le64 rsvd58;
2667 };
2668
2669 /**
2670 * struct ionic_lif_info - LIF info structure
2671 * @config: LIF configuration structure
2672 * @status: LIF status structure
2673 * @stats: LIF statistics structure
2674 */
2675 struct ionic_lif_info {
2676 union ionic_lif_config config;
2677 struct ionic_lif_status status;
2678 struct ionic_lif_stats stats;
2679 };
2680
2681 union ionic_dev_cmd {
2682 u32 words[16];
2683 struct ionic_admin_cmd cmd;
2684 struct ionic_nop_cmd nop;
2685
2686 struct ionic_dev_identify_cmd identify;
2687 struct ionic_dev_init_cmd init;
2688 struct ionic_dev_reset_cmd reset;
2689 struct ionic_dev_getattr_cmd getattr;
2690 struct ionic_dev_setattr_cmd setattr;
2691
2692 struct ionic_port_identify_cmd port_identify;
2693 struct ionic_port_init_cmd port_init;
2694 struct ionic_port_reset_cmd port_reset;
2695 struct ionic_port_getattr_cmd port_getattr;
2696 struct ionic_port_setattr_cmd port_setattr;
2697
2698 struct ionic_vf_setattr_cmd vf_setattr;
2699 struct ionic_vf_getattr_cmd vf_getattr;
2700
2701 struct ionic_lif_identify_cmd lif_identify;
2702 struct ionic_lif_init_cmd lif_init;
2703 struct ionic_lif_reset_cmd lif_reset;
2704
2705 struct ionic_qos_identify_cmd qos_identify;
2706 struct ionic_qos_init_cmd qos_init;
2707 struct ionic_qos_reset_cmd qos_reset;
2708 struct ionic_qos_clear_stats_cmd qos_clear_stats;
2709
2710 struct ionic_q_identify_cmd q_identify;
2711 struct ionic_q_init_cmd q_init;
2712 struct ionic_q_control_cmd q_control;
2713 };
2714
2715 union ionic_dev_cmd_comp {
2716 u32 words[4];
2717 u8 status;
2718 struct ionic_admin_comp comp;
2719 struct ionic_nop_comp nop;
2720
2721 struct ionic_dev_identify_comp identify;
2722 struct ionic_dev_init_comp init;
2723 struct ionic_dev_reset_comp reset;
2724 struct ionic_dev_getattr_comp getattr;
2725 struct ionic_dev_setattr_comp setattr;
2726
2727 struct ionic_port_identify_comp port_identify;
2728 struct ionic_port_init_comp port_init;
2729 struct ionic_port_reset_comp port_reset;
2730 struct ionic_port_getattr_comp port_getattr;
2731 struct ionic_port_setattr_comp port_setattr;
2732
2733 struct ionic_vf_setattr_comp vf_setattr;
2734 struct ionic_vf_getattr_comp vf_getattr;
2735
2736 struct ionic_lif_identify_comp lif_identify;
2737 struct ionic_lif_init_comp lif_init;
2738 ionic_lif_reset_comp lif_reset;
2739
2740 struct ionic_qos_identify_comp qos_identify;
2741 ionic_qos_init_comp qos_init;
2742 ionic_qos_reset_comp qos_reset;
2743
2744 struct ionic_q_identify_comp q_identify;
2745 struct ionic_q_init_comp q_init;
2746 };
2747
2748 /**
2749 * union ionic_dev_info_regs - Device info register format (read-only)
2750 * @signature: Signature value of 0x44455649 ('DEVI')
2751 * @version: Current version of info
2752 * @asic_type: Asic type
2753 * @asic_rev: Asic revision
2754 * @fw_status: Firmware status
2755 * @fw_heartbeat: Firmware heartbeat counter
2756 * @serial_num: Serial number
2757 * @fw_version: Firmware version
2758 */
2759 union ionic_dev_info_regs {
2760 #define IONIC_DEVINFO_FWVERS_BUFLEN 32
2761 #define IONIC_DEVINFO_SERIAL_BUFLEN 32
2762 struct {
2763 u32 signature;
2764 u8 version;
2765 u8 asic_type;
2766 u8 asic_rev;
2767 #define IONIC_FW_STS_F_RUNNING 0x1
2768 u8 fw_status;
2769 u32 fw_heartbeat;
2770 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2771 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2772 };
2773 u32 words[512];
2774 };
2775
2776 /**
2777 * union ionic_dev_cmd_regs - Device command register format (read-write)
2778 * @doorbell: Device Cmd Doorbell, write-only
2779 * Write a 1 to signal device to process cmd,
2780 * poll done for completion.
2781 * @done: Done indicator, bit 0 == 1 when command is complete
2782 * @cmd: Opcode-specific command bytes
2783 * @comp: Opcode-specific response bytes
2784 * @data: Opcode-specific side-data
2785 */
2786 union ionic_dev_cmd_regs {
2787 struct {
2788 u32 doorbell;
2789 u32 done;
2790 union ionic_dev_cmd cmd;
2791 union ionic_dev_cmd_comp comp;
2792 u8 rsvd[48];
2793 u32 data[478];
2794 } __rte_packed;
2795 u32 words[512];
2796 };
2797
2798 /**
2799 * union ionic_dev_regs - Device register format for bar 0 page 0
2800 * @info: Device info registers
2801 * @devcmd: Device command registers
2802 */
2803 union ionic_dev_regs {
2804 struct {
2805 union ionic_dev_info_regs info;
2806 union ionic_dev_cmd_regs devcmd;
2807 } __rte_packed;
2808 __le32 words[1024];
2809 };
2810
2811 union ionic_adminq_cmd {
2812 struct ionic_admin_cmd cmd;
2813 struct ionic_nop_cmd nop;
2814 struct ionic_q_identify_cmd q_identify;
2815 struct ionic_q_init_cmd q_init;
2816 struct ionic_q_control_cmd q_control;
2817 struct ionic_lif_setattr_cmd lif_setattr;
2818 struct ionic_lif_getattr_cmd lif_getattr;
2819 struct ionic_rx_mode_set_cmd rx_mode_set;
2820 struct ionic_rx_filter_add_cmd rx_filter_add;
2821 struct ionic_rx_filter_del_cmd rx_filter_del;
2822 struct ionic_rdma_reset_cmd rdma_reset;
2823 struct ionic_rdma_queue_cmd rdma_queue;
2824 struct ionic_fw_download_cmd fw_download;
2825 struct ionic_fw_control_cmd fw_control;
2826 };
2827
2828 union ionic_adminq_comp {
2829 struct ionic_admin_comp comp;
2830 struct ionic_nop_comp nop;
2831 struct ionic_q_identify_comp q_identify;
2832 struct ionic_q_init_comp q_init;
2833 struct ionic_lif_setattr_comp lif_setattr;
2834 struct ionic_lif_getattr_comp lif_getattr;
2835 struct ionic_rx_filter_add_comp rx_filter_add;
2836 struct ionic_fw_control_comp fw_control;
2837 };
2838
2839 #define IONIC_BARS_MAX 6
2840 #define IONIC_PCI_BAR_DBELL 1
2841
2842 /* BAR0 */
2843 #define IONIC_BAR0_SIZE 0x8000
2844
2845 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
2846 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
2847 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
2848 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
2849 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
2850 #define IONIC_DEV_CMD_DONE 0x00000001
2851
2852 #define IONIC_ASIC_TYPE_CAPRI 0
2853
2854 /**
2855 * struct ionic_doorbell - Doorbell register layout
2856 * @p_index: Producer index
2857 * @ring: Selects the specific ring of the queue to update
2858 * Type-specific meaning:
2859 * ring=0: Default producer/consumer queue
2860 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
2861 * send events to EQs when armed. EQs send
2862 * interrupts when armed.
2863 * @qid_lo: Queue destination for the producer index and flags (low bits)
2864 * @qid_hi: Queue destination for the producer index and flags (high bits)
2865 */
2866 struct ionic_doorbell {
2867 __le16 p_index;
2868 u8 ring;
2869 u8 qid_lo;
2870 __le16 qid_hi;
2871 u16 rsvd2;
2872 };
2873
2874 /**
2875 * struct ionic_intr_ctrl - Interrupt control register
2876 * @coalescing_init: Coalescing timer initial value, in
2877 * device units. Use @identity->intr_coal_mult
2878 * and @identity->intr_coal_div to convert from
2879 * usecs to device units:
2880 *
2881 * coal_init = coal_usecs * coal_mult / coal_div
2882 *
2883 * When an interrupt is sent the interrupt
2884 * coalescing timer current value
2885 * (@coalescing_curr) is initialized with this
2886 * value and begins counting down. No more
2887 * interrupts are sent until the coalescing
2888 * timer reaches 0. When @coalescing_init=0
2889 * interrupt coalescing is effectively disabled
2890 * and every interrupt assert results in an
2891 * interrupt. Reset value: 0
2892 * @mask: Interrupt mask. When @mask=1 the interrupt
2893 * resource will not send an interrupt. When
2894 * @mask=0 the interrupt resource will send an
2895 * interrupt if an interrupt event is pending
2896 * or on the next interrupt assertion event.
2897 * Reset value: 1
2898 * @int_credits: Interrupt credits. This register indicates
2899 * how many interrupt events the hardware has
2900 * sent. When written by software this
2901 * register atomically decrements @int_credits
2902 * by the value written. When @int_credits
2903 * becomes 0 then the "pending interrupt" bit
2904 * in the Interrupt Status register is cleared
2905 * by the hardware and any pending but unsent
2906 * interrupts are cleared.
2907 * !!!IMPORTANT!!! This is a signed register.
2908 * @flags: Interrupt control flags
2909 * @unmask -- When this bit is written with a 1
2910 * the interrupt resource will set mask=0.
2911 * @coal_timer_reset -- When this
2912 * bit is written with a 1 the
2913 * @coalescing_curr will be reloaded with
2914 * @coalescing_init to reset the coalescing
2915 * timer.
2916 * @mask_on_assert: Automatically mask on assertion. When
2917 * @mask_on_assert=1 the interrupt resource
2918 * will set @mask=1 whenever an interrupt is
2919 * sent. When using interrupts in Legacy
2920 * Interrupt mode the driver must select
2921 * @mask_on_assert=0 for proper interrupt
2922 * operation.
2923 * @coalescing_curr: Coalescing timer current value, in
2924 * microseconds. When this value reaches 0
2925 * the interrupt resource is again eligible to
2926 * send an interrupt. If an interrupt event
2927 * is already pending when @coalescing_curr
2928 * reaches 0 the pending interrupt will be
2929 * sent, otherwise an interrupt will be sent
2930 * on the next interrupt assertion event.
2931 */
2932 struct ionic_intr_ctrl {
2933 u8 coalescing_init;
2934 u8 rsvd[3];
2935 u8 mask;
2936 u8 rsvd2[3];
2937 u16 int_credits;
2938 u16 flags;
2939 #define INTR_F_UNMASK 0x0001
2940 #define INTR_F_TIMER_RESET 0x0002
2941 u8 mask_on_assert;
2942 u8 rsvd3[3];
2943 u8 coalescing_curr;
2944 u8 rsvd4[3];
2945 u32 rsvd6[3];
2946 };
2947
2948 #define IONIC_INTR_CTRL_REGS_MAX 2048
2949 #define IONIC_INTR_CTRL_COAL_MAX 0x3F
2950
2951 #define intr_to_coal(intr_ctrl) \
2952 ((void __iomem *)&(intr_ctrl)->coalescing_init)
2953 #define intr_to_mask(intr_ctrl) \
2954 ((void __iomem *)&(intr_ctrl)->mask)
2955 #define intr_to_credits(intr_ctrl) \
2956 ((void __iomem *)&(intr_ctrl)->int_credits)
2957 #define intr_to_mask_on_assert(intr_ctrl)\
2958 ((void __iomem *)&(intr_ctrl)->mask_on_assert)
2959
2960 struct ionic_intr_status {
2961 u32 status[2];
2962 };
2963
2964 struct ionic_notifyq_cmd {
2965 __le32 data; /* Not used but needed for qcq structure */
2966 };
2967
2968 union ionic_notifyq_comp {
2969 struct ionic_notifyq_event event;
2970 struct ionic_link_change_event link_change;
2971 struct ionic_reset_event reset;
2972 struct ionic_heartbeat_event heartbeat;
2973 struct ionic_log_event log;
2974 };
2975
2976 /**
2977 * struct ionic_eq_comp - Event queue completion descriptor
2978 *
2979 * @code: Event code, see enum ionic_eq_comp_code
2980 * @lif_index: To which LIF the event pertains
2981 * @qid: To which queue id the event pertains
2982 * @gen_color: Event queue wrap counter, init 1, incr each wrap
2983 */
2984 struct ionic_eq_comp {
2985 __le16 code;
2986 __le16 lif_index;
2987 __le32 qid;
2988 u8 rsvd[7];
2989 u8 gen_color;
2990 };
2991
2992 enum ionic_eq_comp_code {
2993 IONIC_EQ_COMP_CODE_NONE = 0,
2994 IONIC_EQ_COMP_CODE_RX_COMP = 1,
2995 IONIC_EQ_COMP_CODE_TX_COMP = 2,
2996 };
2997
2998 /* Deprecate */
2999 struct ionic_identity {
3000 union ionic_drv_identity drv;
3001 union ionic_dev_identity dev;
3002 union ionic_lif_identity lif;
3003 union ionic_port_identity port;
3004 union ionic_qos_identity qos;
3005 union ionic_q_identity txq;
3006 };
3007
3008 #endif /* _IONIC_IF_H_ */
3009