| /dpdk/drivers/net/hns3/ |
| H A D | hns3_intr.c | 2021 int num, uint64_t *levels, in hns3_handle_hw_error() argument
2076 hns3_atomic_set_bit(req_level, levels); in hns3_handle_hw_error()
2532 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels); in hns3_clear_reset_level()
2535 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels); in hns3_clear_reset_level()
2539 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels); in hns3_clear_reset_level()
2544 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels); in hns3_clear_reset_level()
2547 hns3_atomic_clear_bit(HNS3_VF_RESET, levels); in hns3_clear_reset_level()
2554 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels); in hns3_clear_reset_level()
2559 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels); in hns3_clear_reset_level()
2564 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels); in hns3_clear_reset_level()
[all …]
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| H A D | hns3_intr.h | 174 void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
175 void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);
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| H A D | hns3_ethdev_vf.c | 40 uint64_t *levels);
2116 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) in hns3vf_get_reset_level() argument
2121 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) in hns3vf_get_reset_level()
2123 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) in hns3vf_get_reset_level()
2125 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) in hns3vf_get_reset_level()
2127 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) in hns3vf_get_reset_level()
2129 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) in hns3vf_get_reset_level()
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| H A D | hns3_ethdev.c | 91 uint64_t *levels);
5717 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) in hns3_get_reset_level() argument
5723 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) in hns3_get_reset_level()
5725 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) in hns3_get_reset_level()
5727 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) in hns3_get_reset_level()
5729 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) in hns3_get_reset_level()
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| /dpdk/lib/eal/linux/ |
| H A D | eal_vfio.h | 50 uint32_t levels; member
66 uint32_t levels; member
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| H A D | eal_vfio.c | 1753 create.levels = 1; in vfio_spapr_create_dma_window()
1765 uint32_t levels; in vfio_spapr_create_dma_window() local
1767 for (levels = create.levels + 1; in vfio_spapr_create_dma_window()
1768 ret && levels <= info.ddw.levels; levels++) { in vfio_spapr_create_dma_window()
1769 create.levels = levels; in vfio_spapr_create_dma_window()
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| /dpdk/doc/guides/prog_guide/ |
| H A D | lpm6_lib.rst | 52 In this case, instead of using two levels, one with a tbl24 and a second with a tbl8, 14 levels are…
57 This effectively means that the trie has 14 levels at the most, depending on the rules that are add…
75 or the subsequent tbl8s we might need to continue the lookup process in deeper levels of the tree.
81 By splitting the process in different tables/levels and limiting the number of tbl8s,
87 Table split into different levels
191 which is the number of levels minus one, since the first three bytes are resolved in the tbl24. How…
198 This might happen again in deeper levels, so, effectively,
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| H A D | timer_lib.rst | 31 The skiplist used has ten levels and each entry in the table appears in each level with probability…
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| H A D | lpm_lib.rst | 65 By splitting the process in two different tables/levels and limiting the number of tbl8s,
71 Table split into different levels
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| H A D | fib_lib.rst | 119 By splitting the process into two different tables/levels and limiting the number of tbl8s,
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| H A D | rte_flow.rst | 40 Support for different priority levels on a rule basis is provided, for
44 available priority levels is usually low, which is why they can also be
45 implemented in software by PMDs (e.g. missing priority levels may be
169 Priority levels are arbitrary and up to the application, they do
1143 range of threshold and map to different accuracy levels that device support.
3981 relative to other flow rules, by adjusting priority levels.
4384 predictable behavior is only guaranteed by using different priority levels.
4386 Priority levels are not necessarily implemented in hardware, or may be
4389 For these reasons, priority levels may be implemented purely in software by
4399 - In order to save priority levels, PMDs may evaluate whether rules are
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| H A D | switch_representation.rst | 699 pass-through and use priority levels.
702 rules of varying priority levels is prohibitively difficult to implement
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| H A D | qos_framework.rst | 66 …| 8 | Hierarchical Scheduler | 5-level hierarchical scheduler (levels are: output port, subport, p…
68 …| | | Implements traffic shaping (for subport and pipe levels), strict pr…
131 with subsequent hierarchy levels defined as subport, pipe, traffic class and queue.
747 The traffic classes at the pipe and subport levels are not traffic shaped,
750 pipe levels is enforced by periodically refilling the subport / pipe traffic class credit counter,
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| H A D | traffic_management.rst | 42 levels, maximum number of shapers, maximum number of private shapers, type of
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| H A D | bbdev.rst | 85 Configuration of a device has two different levels: configuration that applies
255 capabilities. The ``rte_bbdev_info`` structure provides two levels of
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| /dpdk/doc/guides/compressdevs/ |
| H A D | isal.rst | 59 The ISA-L levels have been mapped to somewhat correspond to the same ZLIB level,
65 The compressdev API has 10 levels, 0-9. ISA-L has 4 levels of compression, 0-3.
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| /dpdk/doc/guides/nics/ |
| H A D | ngbe.rst | 47 One may leverage EAL option "--log-level" to change default levels
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| H A D | txgbe.rst | 73 One may leverage EAL option "--log-level" to change default levels
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| H A D | cnxk.rst | 124 - ``Flow priority levels`` (default ``3``)
126 RTE Flow priority levels can be configured during runtime using
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| H A D | sfc_efx.rst | 503 One may leverage EAL option "--log-level" to change default levels
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| H A D | mvpp2.rst | 666 - Maximum number of levels in hierarchy is 2
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| /dpdk/lib/timer/ |
| H A D | rte_timer.c | 317 static uint32_t levels[MAX_SKIPLIST_DEPTH] = {0}; in timer_get_skiplist_level() local
336 levels[level]++; in timer_get_skiplist_level()
339 printf("Level %u: %u\n", (unsigned)i, (unsigned)levels[i]); in timer_get_skiplist_level()
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| /dpdk/doc/guides/vdpadevs/ |
| H A D | sfc.rst | 82 One may leverage EAL option "--log-level" to change default levels
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| /dpdk/doc/guides/eventdevs/ |
| H A D | dlb2.rst | 252 DLB supports 4 event and queue service priority levels. For both priority types,
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| /dpdk/doc/guides/platform/ |
| H A D | mlx5.rst | 34 There are different levels of objects and bypassing abilities
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