1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #ifndef _IXGBE_RXTX_H_ 6 #define _IXGBE_RXTX_H_ 7 8 /* 9 * Rings setup and release. 10 * 11 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 12 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 13 * also optimize cache line size effect. H/W supports up to cache line size 128. 14 */ 15 #define IXGBE_ALIGN 128 16 17 #define IXGBE_RXD_ALIGN (IXGBE_ALIGN / sizeof(union ixgbe_adv_rx_desc)) 18 #define IXGBE_TXD_ALIGN (IXGBE_ALIGN / sizeof(union ixgbe_adv_tx_desc)) 19 20 /* 21 * Maximum number of Ring Descriptors. 22 * 23 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring 24 * descriptors should meet the following condition: 25 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0 26 */ 27 #define IXGBE_MIN_RING_DESC 32 28 #define IXGBE_MAX_RING_DESC 4096 29 30 #define RTE_PMD_IXGBE_TX_MAX_BURST 32 31 #define RTE_PMD_IXGBE_RX_MAX_BURST 32 32 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64 33 34 #define RTE_IXGBE_DESCS_PER_LOOP 4 35 36 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM) 37 #define RTE_IXGBE_RXQ_REARM_THRESH 32 38 #define RTE_IXGBE_MAX_RX_BURST RTE_IXGBE_RXQ_REARM_THRESH 39 #endif 40 41 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_PMD_IXGBE_RX_MAX_BURST) * \ 42 sizeof(union ixgbe_adv_rx_desc)) 43 44 #ifdef RTE_PMD_PACKET_PREFETCH 45 #define rte_packet_prefetch(p) rte_prefetch1(p) 46 #else 47 #define rte_packet_prefetch(p) do {} while(0) 48 #endif 49 50 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10 51 #define RTE_IXGBE_WAIT_100_US 100 52 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2 53 54 #define IXGBE_TX_MAX_SEG 40 55 56 #define IXGBE_TX_MIN_PKT_LEN 14 57 58 #define IXGBE_PACKET_TYPE_MASK_82599 0X7F 59 #define IXGBE_PACKET_TYPE_MASK_X550 0X10FF 60 #define IXGBE_PACKET_TYPE_MASK_TUNNEL 0XFF 61 #define IXGBE_PACKET_TYPE_TUNNEL_BIT 0X1000 62 63 #define IXGBE_PACKET_TYPE_MAX 0X80 64 #define IXGBE_PACKET_TYPE_TN_MAX 0X100 65 #define IXGBE_PACKET_TYPE_SHIFT 0X04 66 67 /** 68 * Structure associated with each descriptor of the RX ring of a RX queue. 69 */ 70 struct ixgbe_rx_entry { 71 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */ 72 }; 73 74 struct ixgbe_scattered_rx_entry { 75 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */ 76 }; 77 78 /** 79 * Structure associated with each descriptor of the TX ring of a TX queue. 80 */ 81 struct ixgbe_tx_entry { 82 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ 83 uint16_t next_id; /**< Index of next descriptor in ring. */ 84 uint16_t last_id; /**< Index of last scattered descriptor. */ 85 }; 86 87 /** 88 * Structure associated with each descriptor of the TX ring of a TX queue. 89 */ 90 struct ixgbe_tx_entry_v { 91 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ 92 }; 93 94 /** 95 * Structure associated with each RX queue. 96 */ 97 struct ixgbe_rx_queue { 98 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ 99 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */ 100 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */ 101 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */ 102 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */ 103 struct ixgbe_rx_entry *sw_ring; /**< address of RX software ring. */ 104 struct ixgbe_scattered_rx_entry *sw_sc_ring; /**< address of scattered Rx software ring. */ 105 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */ 106 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */ 107 uint64_t mbuf_initializer; /**< value to init mbufs */ 108 uint16_t nb_rx_desc; /**< number of RX descriptors. */ 109 uint16_t rx_tail; /**< current value of RDT register. */ 110 uint16_t nb_rx_hold; /**< number of held free RX desc. */ 111 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */ 112 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */ 113 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ 114 uint8_t rx_using_sse; 115 /**< indicates that vector RX is in use */ 116 #ifdef RTE_LIB_SECURITY 117 uint8_t using_ipsec; 118 /**< indicates that IPsec RX feature is in use */ 119 #endif 120 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM) 121 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */ 122 uint16_t rxrearm_start; /**< the idx we start the re-arming from */ 123 #endif 124 uint16_t rx_free_thresh; /**< max free RX desc to hold. */ 125 uint16_t queue_id; /**< RX queue index. */ 126 uint16_t reg_idx; /**< RX queue register index. */ 127 uint16_t pkt_type_mask; /**< Packet type mask for different NICs. */ 128 uint16_t port_id; /**< Device port identifier. */ 129 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */ 130 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */ 131 uint8_t rx_deferred_start; /**< not in global dev start. */ 132 /** UDP frames with a 0 checksum can be marked as checksum errors. */ 133 uint8_t rx_udp_csum_zero_err; 134 /** flags to set in mbuf when a vlan is detected. */ 135 uint64_t vlan_flags; 136 uint64_t offloads; /**< Rx offloads with RTE_ETH_RX_OFFLOAD_* */ 137 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */ 138 struct rte_mbuf fake_mbuf; 139 /** hold packets to return to application */ 140 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2]; 141 const struct rte_memzone *mz; 142 }; 143 144 /** 145 * IXGBE CTX Constants 146 */ 147 enum ixgbe_advctx_num { 148 IXGBE_CTX_0 = 0, /**< CTX0 */ 149 IXGBE_CTX_1 = 1, /**< CTX1 */ 150 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */ 151 }; 152 153 /** Offload features */ 154 union ixgbe_tx_offload { 155 uint64_t data[2]; 156 struct { 157 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ 158 uint64_t l3_len:9; /**< L3 (IP) Header Length. */ 159 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ 160 uint64_t tso_segsz:16; /**< TCP TSO segment size */ 161 uint64_t vlan_tci:16; 162 /**< VLAN Tag Control Identifier (CPU order). */ 163 164 /* fields for TX offloading of tunnels */ 165 uint64_t outer_l3_len:8; /**< Outer L3 (IP) Hdr Length. */ 166 uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */ 167 #ifdef RTE_LIB_SECURITY 168 /* inline ipsec related*/ 169 uint64_t sa_idx:8; /**< TX SA database entry index */ 170 uint64_t sec_pad_len:4; /**< padding length */ 171 #endif 172 }; 173 }; 174 175 /* 176 * Compare mask for vlan_macip_len.data, 177 * should be in sync with ixgbe_vlan_macip.f layout. 178 * */ 179 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */ 180 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */ 181 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */ 182 /** MAC+IP length. */ 183 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK) 184 185 /** 186 * Structure to check if new context need be built 187 */ 188 189 struct ixgbe_advctx_info { 190 uint64_t flags; /**< ol_flags for context build. */ 191 /**< tx offload: vlan, tso, l2-l3-l4 lengths. */ 192 union ixgbe_tx_offload tx_offload; 193 /** compare mask for tx offload. */ 194 union ixgbe_tx_offload tx_offload_mask; 195 }; 196 197 /** 198 * Structure associated with each TX queue. 199 */ 200 struct ixgbe_tx_queue { 201 /** TX ring virtual address. */ 202 volatile union ixgbe_adv_tx_desc *tx_ring; 203 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ 204 union { 205 struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD. */ 206 struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */ 207 }; 208 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ 209 uint16_t nb_tx_desc; /**< number of TX descriptors. */ 210 uint16_t tx_tail; /**< current value of TDT reg. */ 211 /**< Start freeing TX buffers if there are less free descriptors than 212 this value. */ 213 uint16_t tx_free_thresh; 214 /** Number of TX descriptors to use before RS bit is set. */ 215 uint16_t tx_rs_thresh; 216 /** Number of TX descriptors used since RS bit was set. */ 217 uint16_t nb_tx_used; 218 /** Index to last TX descriptor to have been cleaned. */ 219 uint16_t last_desc_cleaned; 220 /** Total number of TX descriptors ready to be allocated. */ 221 uint16_t nb_tx_free; 222 uint16_t tx_next_dd; /**< next desc to scan for DD bit */ 223 uint16_t tx_next_rs; /**< next desc to set RS bit */ 224 uint16_t queue_id; /**< TX queue index. */ 225 uint16_t reg_idx; /**< TX queue register index. */ 226 uint16_t port_id; /**< Device port identifier. */ 227 uint8_t pthresh; /**< Prefetch threshold register. */ 228 uint8_t hthresh; /**< Host threshold register. */ 229 uint8_t wthresh; /**< Write-back threshold reg. */ 230 uint64_t offloads; /**< Tx offload flags of RTE_ETH_TX_OFFLOAD_* */ 231 uint32_t ctx_curr; /**< Hardware context states. */ 232 /** Hardware context0 history. */ 233 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM]; 234 const struct ixgbe_txq_ops *ops; /**< txq ops */ 235 uint8_t tx_deferred_start; /**< not in global dev start. */ 236 #ifdef RTE_LIB_SECURITY 237 uint8_t using_ipsec; 238 /**< indicates that IPsec TX feature is in use */ 239 #endif 240 const struct rte_memzone *mz; 241 }; 242 243 struct ixgbe_txq_ops { 244 void (*release_mbufs)(struct ixgbe_tx_queue *txq); 245 void (*free_swring)(struct ixgbe_tx_queue *txq); 246 void (*reset)(struct ixgbe_tx_queue *txq); 247 }; 248 249 /* 250 * Populate descriptors with the following info: 251 * 1.) buffer_addr = phys_addr + headroom 252 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len 253 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT 254 */ 255 256 /* Defines for Tx descriptor */ 257 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\ 258 IXGBE_ADVTXD_DCMD_IFCS |\ 259 IXGBE_ADVTXD_DCMD_DEXT |\ 260 IXGBE_ADVTXD_DCMD_EOP) 261 262 263 /* Takes an ethdev and a queue and sets up the tx function to be used based on 264 * the queue parameters. Used in tx_queue_setup by primary process and then 265 * in dev_init by secondary process when attaching to an existing ethdev. 266 */ 267 void ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq); 268 269 /** 270 * Sets the rx_pkt_burst callback in the ixgbe rte_eth_dev instance. 271 * 272 * Sets the callback based on the device parameters: 273 * - ixgbe_hw.rx_bulk_alloc_allowed 274 * - rte_eth_dev_data.scattered_rx 275 * - rte_eth_dev_data.lro 276 * - conditions checked in ixgbe_rx_vec_condition_check() 277 * 278 * This means that the parameters above have to be configured prior to calling 279 * to this function. 280 * 281 * @dev rte_eth_dev handle 282 */ 283 void ixgbe_set_rx_function(struct rte_eth_dev *dev); 284 285 int ixgbe_check_supported_loopback_mode(struct rte_eth_dev *dev); 286 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, 287 uint16_t nb_pkts); 288 uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue, 289 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 290 int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev); 291 int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq); 292 void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq); 293 int ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt); 294 295 extern const uint32_t ptype_table[IXGBE_PACKET_TYPE_MAX]; 296 extern const uint32_t ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX]; 297 298 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts, 299 uint16_t nb_pkts); 300 int ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq); 301 302 uint64_t ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev); 303 uint64_t ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev); 304 uint64_t ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev); 305 uint64_t ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev); 306 int ixgbe_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); 307 308 #endif /* _IXGBE_RXTX_H_ */ 309