1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
4 */
5
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
8
9 #include <unistd.h>
10
11 #include <rte_vect.h>
12 #include <rte_byteorder.h>
13
14 #include <mlx5_glue.h>
15 #include "mlx5_autoconf.h"
16
17 /* RSS hash key size. */
18 #define MLX5_RSS_HASH_KEY_LEN 40
19
20 /* Get CQE owner bit. */
21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
22
23 /* Get CQE format. */
24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
25
26 /* Get CQE opcode. */
27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
28
29 /* Get CQE solicited event. */
30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
31
32 /* Invalidate a CQE. */
33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
34
35 /* Hardware index widths. */
36 #define MLX5_CQ_INDEX_WIDTH 24
37 #define MLX5_WQ_INDEX_WIDTH 16
38
39 /* WQE Segment sizes in bytes. */
40 #define MLX5_WSEG_SIZE 16u
41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
44
45 /* WQE/WQEBB size in bytes. */
46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
47
48 /*
49 * Max size of a WQE session.
50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
51 * the WQE size field in Control Segment is 6 bits wide.
52 */
53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
54
55 /*
56 * Default minimum number of Tx queues for inlining packets.
57 * If there are less queues as specified we assume we have
58 * no enough CPU resources (cycles) to perform inlining,
59 * the PCIe throughput is not supposed as bottleneck and
60 * inlining is disabled.
61 */
62 #define MLX5_INLINE_MAX_TXQS 8u
63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
64
65 /*
66 * Default packet length threshold to be inlined with
67 * enhanced MPW. If packet length exceeds the threshold
68 * the data are not inlined. Should be aligned in WQEBB
69 * boundary with accounting the title Control and Ethernet
70 * segments.
71 */
72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
73 MLX5_DSEG_MIN_INLINE_SIZE)
74 /*
75 * Maximal inline data length sent with enhanced MPW.
76 * Is based on maximal WQE size.
77 */
78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
79 MLX5_WQE_CSEG_SIZE - \
80 MLX5_WQE_ESEG_SIZE - \
81 MLX5_WQE_DSEG_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
83 /*
84 * Minimal amount of packets to be sent with EMPW.
85 * This limits the minimal required size of sent EMPW.
86 * If there are no enough resources to built minimal
87 * EMPW the sending loop exits.
88 */
89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
90 /*
91 * Maximal amount of packets to be sent with EMPW.
92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
94 * without CQE generation request, being multiplied by
95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
96 * in tx burst routine at the moment of freeing multiple mbufs.
97 */
98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
99 #define MLX5_MPW_MAX_PACKETS 6
100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
101
102 /*
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
106 * CPU cycles.
107 */
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
112 MLX5_WQE_DSEG_SIZE)
113 /*
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
116 */
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
122
123 /* Missed in mlx5dv.h, should define here. */
124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
126 #endif
127
128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
129 #define MLX5_OPCODE_SEND_EN 0x17u
130 #endif
131
132 #ifndef HAVE_MLX5_OPCODE_WAIT
133 #define MLX5_OPCODE_WAIT 0x0fu
134 #endif
135
136 #define MLX5_OPC_MOD_WAIT_CQ_PI 0u
137 #define MLX5_OPC_MOD_WAIT_DATA 1u
138 #define MLX5_OPC_MOD_WAIT_TIME 2u
139
140
141 #define MLX5_WAIT_COND_INVERT 0x10u
142 #define MLX5_WAIT_COND_ALWAYS_TRUE 0u
143 #define MLX5_WAIT_COND_EQUAL 1u
144 #define MLX5_WAIT_COND_BIGGER 2u
145 #define MLX5_WAIT_COND_SMALLER 3u
146 #define MLX5_WAIT_COND_CYCLIC_BIGGER 4u
147 #define MLX5_WAIT_COND_CYCLIC_SMALLER 5u
148
149 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
150 #define MLX5_OPCODE_ACCESS_ASO 0x2du
151 #endif
152
153 /* CQE value to inform that VLAN is stripped. */
154 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
155
156 /* IPv4 options. */
157 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
158
159 /* IPv6 packet. */
160 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
161
162 /* IPv4 packet. */
163 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
164
165 /* TCP packet. */
166 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
167
168 /* UDP packet. */
169 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
170
171 /* IP is fragmented. */
172 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
173
174 /* L2 header is valid. */
175 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
176
177 /* L3 header is valid. */
178 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
179
180 /* L4 header is valid. */
181 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
182
183 /* Outer packet, 0 IPv4, 1 IPv6. */
184 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
185
186 /* Tunnel packet bit in the CQE. */
187 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
188
189 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
190 #define MLX5_CQE_LRO_PUSH_MASK 0x40
191
192 /* Mask for L4 type in the CQE hdr_type_etc field. */
193 #define MLX5_CQE_L4_TYPE_MASK 0x70
194
195 /* The bit index of L4 type in CQE hdr_type_etc field. */
196 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
197
198 /* L4 type to indicate TCP packet without acknowledgment. */
199 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
200
201 /* L4 type to indicate TCP packet with acknowledgment. */
202 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
203
204 /* Inner L3 checksum offload (Tunneled packets only). */
205 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
206
207 /* Inner L4 checksum offload (Tunneled packets only). */
208 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
209
210 /* Outer L4 type is TCP. */
211 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
212
213 /* Outer L4 type is UDP. */
214 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
215
216 /* Outer L3 type is IPV4. */
217 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
218
219 /* Outer L3 type is IPV6. */
220 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
221
222 /* Inner L4 type is TCP. */
223 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
224
225 /* Inner L4 type is UDP. */
226 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
227
228 /* Inner L3 type is IPV4. */
229 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
230
231 /* Inner L3 type is IPV6. */
232 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
233
234 /* VLAN insertion flag. */
235 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
236
237 /* Data inline segment flag. */
238 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
239
240 /* Is flow mark valid. */
241 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
242 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
243 #else
244 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
245 #endif
246
247 /* INVALID is used by packets matching no flow rules. */
248 #define MLX5_FLOW_MARK_INVALID 0
249
250 /* Maximum allowed value to mark a packet. */
251 #define MLX5_FLOW_MARK_MAX 0xfffff0
252
253 /* Default mark value used when none is provided. */
254 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
255
256 /* Default mark mask for metadata legacy mode. */
257 #define MLX5_FLOW_MARK_MASK 0xffffff
258
259 /* Byte length mask when mark is enable in miniCQE */
260 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
261
262 /* Maximum number of DS in WQE. Limited by 6-bit field. */
263 #define MLX5_DSEG_MAX 63
264
265 /* The 32 bit syndrome offset in struct mlx5_err_cqe. */
266 #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52
267
268 /* The completion mode offset in the WQE control segment line 2. */
269 #define MLX5_COMP_MODE_OFFSET 2
270
271 /* Amount of data bytes in minimal inline data segment. */
272 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
273
274 /* Amount of data bytes in minimal inline eth segment. */
275 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
276
277 /* Amount of data bytes after eth data segment. */
278 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
279
280 /* The maximum log value of segments per RQ WQE. */
281 #define MLX5_MAX_LOG_RQ_SEGS 5u
282
283 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */
284 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U
285
286 /* The alignment needed for WQ buffer. */
287 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
288
289 /* The alignment needed for CQ buffer. */
290 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
291
292 /* Completion mode. */
293 enum mlx5_completion_mode {
294 MLX5_COMP_ONLY_ERR = 0x0,
295 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
296 MLX5_COMP_ALWAYS = 0x2,
297 MLX5_COMP_CQE_AND_EQE = 0x3,
298 };
299
300 /* MPW mode. */
301 enum mlx5_mpw_mode {
302 MLX5_MPW_DISABLED,
303 MLX5_MPW,
304 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
305 };
306
307 /* WQE Control segment. */
308 struct mlx5_wqe_cseg {
309 uint32_t opcode;
310 uint32_t sq_ds;
311 uint32_t flags;
312 uint32_t misc;
313 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
314
315 /*
316 * WQE CSEG opcode field size is 32 bits, divided:
317 * Bits 31:24 OPC_MOD
318 * Bits 23:8 wqe_index
319 * Bits 7:0 OPCODE
320 */
321 #define WQE_CSEG_OPC_MOD_OFFSET 24
322 #define WQE_CSEG_WQE_INDEX_OFFSET 8
323
324 /* Header of data segment. Minimal size Data Segment */
325 struct mlx5_wqe_dseg {
326 uint32_t bcount;
327 union {
328 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
329 struct {
330 uint32_t lkey;
331 uint64_t pbuf;
332 } __rte_packed;
333 };
334 } __rte_packed;
335
336 /* Subset of struct WQE Ethernet Segment. */
337 struct mlx5_wqe_eseg {
338 union {
339 struct {
340 uint32_t swp_offs;
341 uint8_t cs_flags;
342 uint8_t swp_flags;
343 uint16_t mss;
344 uint32_t metadata;
345 uint16_t inline_hdr_sz;
346 union {
347 uint16_t inline_data;
348 uint16_t vlan_tag;
349 };
350 } __rte_packed;
351 struct {
352 uint32_t offsets;
353 uint32_t flags;
354 uint32_t flow_metadata;
355 uint32_t inline_hdr;
356 } __rte_packed;
357 };
358 } __rte_packed;
359
360 struct mlx5_wqe_qseg {
361 uint32_t reserved0;
362 uint32_t reserved1;
363 uint32_t max_index;
364 uint32_t qpn_cqn;
365 } __rte_packed;
366
367 struct mlx5_wqe_wseg {
368 uint32_t operation;
369 uint32_t lkey;
370 uint32_t va_high;
371 uint32_t va_low;
372 uint64_t value;
373 uint64_t mask;
374 } __rte_packed;
375
376 /* The title WQEBB, header of WQE. */
377 struct mlx5_wqe {
378 union {
379 struct mlx5_wqe_cseg cseg;
380 uint32_t ctrl[4];
381 };
382 struct mlx5_wqe_eseg eseg;
383 union {
384 struct mlx5_wqe_dseg dseg[2];
385 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
386 };
387 } __rte_packed;
388
389 /* WQE for Multi-Packet RQ. */
390 struct mlx5_wqe_mprq {
391 struct mlx5_wqe_srq_next_seg next_seg;
392 struct mlx5_wqe_data_seg dseg;
393 };
394
395 #define MLX5_MPRQ_LEN_MASK 0x000ffff
396 #define MLX5_MPRQ_LEN_SHIFT 0
397 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
398 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
399 #define MLX5_MPRQ_FILLER_MASK 0x80000000
400 #define MLX5_MPRQ_FILLER_SHIFT 31
401
402 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
403
404 /* CQ element structure - should be equal to the cache line size */
405 struct mlx5_cqe {
406 #if (RTE_CACHE_LINE_SIZE == 128)
407 uint8_t padding[64];
408 #endif
409 uint8_t pkt_info;
410 uint8_t rsvd0;
411 uint16_t wqe_id;
412 uint8_t lro_tcppsh_abort_dupack;
413 uint8_t lro_min_ttl;
414 uint16_t lro_tcp_win;
415 uint32_t lro_ack_seq_num;
416 uint32_t rx_hash_res;
417 uint8_t rx_hash_type;
418 uint8_t rsvd1[3];
419 uint16_t csum;
420 uint8_t rsvd2[6];
421 uint16_t hdr_type_etc;
422 uint16_t vlan_info;
423 uint8_t lro_num_seg;
424 union {
425 uint8_t user_index_bytes[3];
426 struct {
427 uint8_t user_index_hi;
428 uint16_t user_index_low;
429 } __rte_packed;
430 };
431 uint32_t flow_table_metadata;
432 uint8_t rsvd4[4];
433 uint32_t byte_cnt;
434 uint64_t timestamp;
435 uint32_t sop_drop_qpn;
436 uint16_t wqe_counter;
437 uint8_t rsvd5;
438 uint8_t op_own;
439 };
440
441 struct mlx5_cqe_ts {
442 uint64_t timestamp;
443 uint32_t sop_drop_qpn;
444 uint16_t wqe_counter;
445 uint8_t rsvd5;
446 uint8_t op_own;
447 };
448
449 struct mlx5_wqe_rseg {
450 uint64_t raddr;
451 uint32_t rkey;
452 uint32_t reserved;
453 } __rte_packed;
454
455 #define MLX5_UMRC_IF_OFFSET 31u
456 #define MLX5_UMRC_KO_OFFSET 16u
457 #define MLX5_UMRC_TO_BS_OFFSET 0u
458
459 struct mlx5_wqe_umr_cseg {
460 uint32_t if_cf_toe_cq_res;
461 uint32_t ko_to_bs;
462 uint64_t mkey_mask;
463 uint32_t rsvd1[8];
464 } __rte_packed;
465
466 struct mlx5_wqe_mkey_cseg {
467 uint32_t fr_res_af_sf;
468 uint32_t qpn_mkey;
469 uint32_t reserved2;
470 uint32_t flags_pd;
471 uint64_t start_addr;
472 uint64_t len;
473 uint32_t bsf_octword_size;
474 uint32_t reserved3[4];
475 uint32_t translations_octword_size;
476 uint32_t res4_lps;
477 uint32_t reserved;
478 } __rte_packed;
479
480 enum {
481 MLX5_BSF_SIZE_16B = 0x0,
482 MLX5_BSF_SIZE_32B = 0x1,
483 MLX5_BSF_SIZE_64B = 0x2,
484 MLX5_BSF_SIZE_128B = 0x3,
485 };
486
487 enum {
488 MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
489 MLX5_BSF_P_TYPE_CRYPTO = 0x1,
490 };
491
492 enum {
493 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
494 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
495 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
496 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
497 };
498
499 enum {
500 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
501 };
502
503 enum {
504 MLX5_BLOCK_SIZE_512B = 0x1,
505 MLX5_BLOCK_SIZE_520B = 0x2,
506 MLX5_BLOCK_SIZE_4096B = 0x3,
507 MLX5_BLOCK_SIZE_4160B = 0x4,
508 MLX5_BLOCK_SIZE_1MB = 0x5,
509 MLX5_BLOCK_SIZE_4048B = 0x6,
510 };
511
512 #define MLX5_BSF_SIZE_OFFSET 30
513 #define MLX5_BSF_P_TYPE_OFFSET 24
514 #define MLX5_ENCRYPTION_ORDER_OFFSET 16
515 #define MLX5_BLOCK_SIZE_OFFSET 24
516
517 struct mlx5_wqe_umr_bsf_seg {
518 /*
519 * bs_bpt_eo_es contains:
520 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET
521 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET
522 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
523 * es encryption_standard 4 bits at offset 0
524 */
525 uint32_t bs_bpt_eo_es;
526 uint32_t raw_data_size;
527 /*
528 * bsp_res contains:
529 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET
530 * res reserved 24 bits
531 */
532 uint32_t bsp_res;
533 uint32_t reserved0;
534 uint8_t xts_initial_tweak[16];
535 /*
536 * res_dp contains:
537 * res reserved 8 bits
538 * dp dek_pointer 24 bits at offset 0
539 */
540 uint32_t res_dp;
541 uint32_t reserved1;
542 uint64_t keytag;
543 uint32_t reserved2[4];
544 } __rte_packed;
545
546 #ifdef PEDANTIC
547 #pragma GCC diagnostic ignored "-Wpedantic"
548 #endif
549
550 struct mlx5_umr_wqe {
551 struct mlx5_wqe_cseg ctr;
552 struct mlx5_wqe_umr_cseg ucseg;
553 struct mlx5_wqe_mkey_cseg mkc;
554 union {
555 struct mlx5_wqe_dseg kseg[0];
556 struct mlx5_wqe_umr_bsf_seg bsf[0];
557 };
558 } __rte_packed;
559
560 struct mlx5_rdma_write_wqe {
561 struct mlx5_wqe_cseg ctr;
562 struct mlx5_wqe_rseg rseg;
563 struct mlx5_wqe_dseg dseg[0];
564 } __rte_packed;
565
566 #ifdef PEDANTIC
567 #pragma GCC diagnostic error "-Wpedantic"
568 #endif
569
570 /* GGA */
571 /* MMO metadata segment */
572
573 #define MLX5_OPCODE_MMO 0x2fu
574 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
575 #define MLX5_OPC_MOD_MMO_COMP 0x2u
576 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
577 #define MLX5_OPC_MOD_MMO_DMA 0x1u
578
579 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
580 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
581 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
582 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
583 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
584 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
585 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
586 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
587 #define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084
588 #define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011
589
590 struct mlx5_wqe_metadata_seg {
591 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
592 uint32_t lkey;
593 uint64_t addr;
594 };
595
596 struct mlx5_gga_wqe {
597 uint32_t opcode;
598 uint32_t sq_ds;
599 uint32_t flags;
600 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */
601 uint32_t gga_ctrl2;
602 uint32_t opaque_lkey;
603 uint64_t opaque_vaddr;
604 struct mlx5_wqe_dseg gather;
605 struct mlx5_wqe_dseg scatter;
606 } __rte_packed;
607
608 struct mlx5_gga_compress_opaque {
609 uint32_t syndrom;
610 uint32_t reserved0;
611 uint32_t scattered_length;
612 uint32_t gathered_length;
613 uint64_t scatter_crc;
614 uint64_t gather_crc;
615 uint32_t crc32;
616 uint32_t adler32;
617 uint8_t reserved1[216];
618 } __rte_packed;
619
620 struct mlx5_ifc_regexp_mmo_control_bits {
621 uint8_t reserved_at_31[0x2];
622 uint8_t le[0x1];
623 uint8_t reserved_at_28[0x1];
624 uint8_t subset_id_0[0xc];
625 uint8_t reserved_at_16[0x4];
626 uint8_t subset_id_1[0xc];
627 uint8_t ctrl[0x4];
628 uint8_t subset_id_2[0xc];
629 uint8_t reserved_at_16_1[0x4];
630 uint8_t subset_id_3[0xc];
631 };
632
633 struct mlx5_ifc_regexp_metadata_bits {
634 uint8_t rof_version[0x10];
635 uint8_t latency_count[0x10];
636 uint8_t instruction_count[0x10];
637 uint8_t primary_thread_count[0x10];
638 uint8_t match_count[0x8];
639 uint8_t detected_match_count[0x8];
640 uint8_t status[0x10];
641 uint8_t job_id[0x20];
642 uint8_t reserved[0x80];
643 };
644
645 struct mlx5_ifc_regexp_match_tuple_bits {
646 uint8_t length[0x10];
647 uint8_t start_ptr[0x10];
648 uint8_t rule_id[0x20];
649 };
650
651 /* Adding direct verbs to data-path. */
652
653 /* CQ sequence number mask. */
654 #define MLX5_CQ_SQN_MASK 0x3
655
656 /* CQ sequence number index. */
657 #define MLX5_CQ_SQN_OFFSET 28
658
659 /* CQ doorbell index mask. */
660 #define MLX5_CI_MASK 0xffffff
661
662 /* CQ doorbell offset. */
663 #define MLX5_CQ_ARM_DB 1
664
665 /* CQ doorbell offset*/
666 #define MLX5_CQ_DOORBELL 0x20
667
668 /* CQE format value. */
669 #define MLX5_COMPRESSED 0x3
670
671 /* CQ doorbell cmd types. */
672 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
673 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
674
675 /* Action type of header modification. */
676 enum {
677 MLX5_MODIFICATION_TYPE_SET = 0x1,
678 MLX5_MODIFICATION_TYPE_ADD = 0x2,
679 MLX5_MODIFICATION_TYPE_COPY = 0x3,
680 };
681
682 /* The field of packet to be modified. */
683 enum mlx5_modification_field {
684 MLX5_MODI_OUT_NONE = -1,
685 MLX5_MODI_OUT_SMAC_47_16 = 1,
686 MLX5_MODI_OUT_SMAC_15_0,
687 MLX5_MODI_OUT_ETHERTYPE,
688 MLX5_MODI_OUT_DMAC_47_16,
689 MLX5_MODI_OUT_DMAC_15_0,
690 MLX5_MODI_OUT_IP_DSCP,
691 MLX5_MODI_OUT_TCP_FLAGS,
692 MLX5_MODI_OUT_TCP_SPORT,
693 MLX5_MODI_OUT_TCP_DPORT,
694 MLX5_MODI_OUT_IPV4_TTL,
695 MLX5_MODI_OUT_UDP_SPORT,
696 MLX5_MODI_OUT_UDP_DPORT,
697 MLX5_MODI_OUT_SIPV6_127_96,
698 MLX5_MODI_OUT_SIPV6_95_64,
699 MLX5_MODI_OUT_SIPV6_63_32,
700 MLX5_MODI_OUT_SIPV6_31_0,
701 MLX5_MODI_OUT_DIPV6_127_96,
702 MLX5_MODI_OUT_DIPV6_95_64,
703 MLX5_MODI_OUT_DIPV6_63_32,
704 MLX5_MODI_OUT_DIPV6_31_0,
705 MLX5_MODI_OUT_SIPV4,
706 MLX5_MODI_OUT_DIPV4,
707 MLX5_MODI_OUT_FIRST_VID,
708 MLX5_MODI_IN_SMAC_47_16 = 0x31,
709 MLX5_MODI_IN_SMAC_15_0,
710 MLX5_MODI_IN_ETHERTYPE,
711 MLX5_MODI_IN_DMAC_47_16,
712 MLX5_MODI_IN_DMAC_15_0,
713 MLX5_MODI_IN_IP_DSCP,
714 MLX5_MODI_IN_TCP_FLAGS,
715 MLX5_MODI_IN_TCP_SPORT,
716 MLX5_MODI_IN_TCP_DPORT,
717 MLX5_MODI_IN_IPV4_TTL,
718 MLX5_MODI_IN_UDP_SPORT,
719 MLX5_MODI_IN_UDP_DPORT,
720 MLX5_MODI_IN_SIPV6_127_96,
721 MLX5_MODI_IN_SIPV6_95_64,
722 MLX5_MODI_IN_SIPV6_63_32,
723 MLX5_MODI_IN_SIPV6_31_0,
724 MLX5_MODI_IN_DIPV6_127_96,
725 MLX5_MODI_IN_DIPV6_95_64,
726 MLX5_MODI_IN_DIPV6_63_32,
727 MLX5_MODI_IN_DIPV6_31_0,
728 MLX5_MODI_IN_SIPV4,
729 MLX5_MODI_IN_DIPV4,
730 MLX5_MODI_OUT_IPV6_HOPLIMIT,
731 MLX5_MODI_IN_IPV6_HOPLIMIT,
732 MLX5_MODI_META_DATA_REG_A,
733 MLX5_MODI_META_DATA_REG_B = 0x50,
734 MLX5_MODI_META_REG_C_0,
735 MLX5_MODI_META_REG_C_1,
736 MLX5_MODI_META_REG_C_2,
737 MLX5_MODI_META_REG_C_3,
738 MLX5_MODI_META_REG_C_4,
739 MLX5_MODI_META_REG_C_5,
740 MLX5_MODI_META_REG_C_6,
741 MLX5_MODI_META_REG_C_7,
742 MLX5_MODI_OUT_TCP_SEQ_NUM,
743 MLX5_MODI_IN_TCP_SEQ_NUM,
744 MLX5_MODI_OUT_TCP_ACK_NUM,
745 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
746 MLX5_MODI_GTP_TEID = 0x6E,
747 };
748
749 /* Total number of metadata reg_c's. */
750 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
751
752 enum modify_reg {
753 REG_NON = 0,
754 REG_A,
755 REG_B,
756 REG_C_0,
757 REG_C_1,
758 REG_C_2,
759 REG_C_3,
760 REG_C_4,
761 REG_C_5,
762 REG_C_6,
763 REG_C_7,
764 };
765
766 /* Modification sub command. */
767 struct mlx5_modification_cmd {
768 union {
769 uint32_t data0;
770 struct {
771 unsigned int length:5;
772 unsigned int rsvd0:3;
773 unsigned int offset:5;
774 unsigned int rsvd1:3;
775 unsigned int field:12;
776 unsigned int action_type:4;
777 };
778 };
779 union {
780 uint32_t data1;
781 uint8_t data[4];
782 struct {
783 unsigned int rsvd2:8;
784 unsigned int dst_offset:5;
785 unsigned int rsvd3:3;
786 unsigned int dst_field:12;
787 unsigned int rsvd4:4;
788 };
789 };
790 };
791
792 typedef uint64_t u64;
793 typedef uint32_t u32;
794 typedef uint16_t u16;
795 typedef uint8_t u8;
796
797 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
798 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
799 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
800 (&(__mlx5_nullp(typ)->fld)))
801 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
802 (__mlx5_bit_off(typ, fld) & 0x1f))
803 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
804 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
805 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
806 __mlx5_dw_bit_off(typ, fld))
807 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
808 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
809 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
810 (__mlx5_bit_off(typ, fld) & 0xf))
811 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
812 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
813 __mlx5_16_bit_off(typ, fld))
814 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
815 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
816 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
817 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
818
819 /* insert a value to a struct */
820 #define MLX5_SET(typ, p, fld, v) \
821 do { \
822 u32 _v = v; \
823 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
824 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
825 __mlx5_dw_off(typ, fld))) & \
826 (~__mlx5_dw_mask(typ, fld))) | \
827 (((_v) & __mlx5_mask(typ, fld)) << \
828 __mlx5_dw_bit_off(typ, fld))); \
829 } while (0)
830
831 #define MLX5_SET64(typ, p, fld, v) \
832 do { \
833 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
834 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
835 rte_cpu_to_be_64(v); \
836 } while (0)
837
838 #define MLX5_SET16(typ, p, fld, v) \
839 do { \
840 u16 _v = v; \
841 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
842 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
843 __mlx5_16_off(typ, fld))) & \
844 (~__mlx5_16_mask(typ, fld))) | \
845 (((_v) & __mlx5_mask16(typ, fld)) << \
846 __mlx5_16_bit_off(typ, fld))); \
847 } while (0)
848
849 #define MLX5_GET_VOLATILE(typ, p, fld) \
850 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
851 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
852 __mlx5_mask(typ, fld))
853 #define MLX5_GET(typ, p, fld) \
854 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
855 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
856 __mlx5_mask(typ, fld))
857 #define MLX5_GET16(typ, p, fld) \
858 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
859 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
860 __mlx5_mask16(typ, fld))
861 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
862 __mlx5_64_off(typ, fld)))
863 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
864 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
865
866 struct mlx5_ifc_fte_match_set_misc_bits {
867 u8 gre_c_present[0x1];
868 u8 reserved_at_1[0x1];
869 u8 gre_k_present[0x1];
870 u8 gre_s_present[0x1];
871 u8 source_vhci_port[0x4];
872 u8 source_sqn[0x18];
873 u8 reserved_at_20[0x10];
874 u8 source_port[0x10];
875 u8 outer_second_prio[0x3];
876 u8 outer_second_cfi[0x1];
877 u8 outer_second_vid[0xc];
878 u8 inner_second_prio[0x3];
879 u8 inner_second_cfi[0x1];
880 u8 inner_second_vid[0xc];
881 u8 outer_second_cvlan_tag[0x1];
882 u8 inner_second_cvlan_tag[0x1];
883 u8 outer_second_svlan_tag[0x1];
884 u8 inner_second_svlan_tag[0x1];
885 u8 reserved_at_64[0xc];
886 u8 gre_protocol[0x10];
887 u8 gre_key_h[0x18];
888 u8 gre_key_l[0x8];
889 u8 vxlan_vni[0x18];
890 u8 reserved_at_b8[0x8];
891 u8 geneve_vni[0x18];
892 u8 reserved_at_e4[0x6];
893 u8 geneve_tlv_option_0_exist[0x1];
894 u8 geneve_oam[0x1];
895 u8 reserved_at_e0[0xc];
896 u8 outer_ipv6_flow_label[0x14];
897 u8 reserved_at_100[0xc];
898 u8 inner_ipv6_flow_label[0x14];
899 u8 reserved_at_120[0xa];
900 u8 geneve_opt_len[0x6];
901 u8 geneve_protocol_type[0x10];
902 u8 reserved_at_140[0x20];
903 u8 inner_esp_spi[0x20];
904 u8 outer_esp_spi[0x20];
905 u8 reserved_at_1a0[0x60];
906 };
907
908 struct mlx5_ifc_ipv4_layout_bits {
909 u8 reserved_at_0[0x60];
910 u8 ipv4[0x20];
911 };
912
913 struct mlx5_ifc_ipv6_layout_bits {
914 u8 ipv6[16][0x8];
915 };
916
917 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
918 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
919 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
920 u8 reserved_at_0[0x80];
921 };
922
923 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
924 u8 smac_47_16[0x20];
925 u8 smac_15_0[0x10];
926 u8 ethertype[0x10];
927 u8 dmac_47_16[0x20];
928 u8 dmac_15_0[0x10];
929 u8 first_prio[0x3];
930 u8 first_cfi[0x1];
931 u8 first_vid[0xc];
932 u8 ip_protocol[0x8];
933 u8 ip_dscp[0x6];
934 u8 ip_ecn[0x2];
935 u8 cvlan_tag[0x1];
936 u8 svlan_tag[0x1];
937 u8 frag[0x1];
938 u8 ip_version[0x4];
939 u8 tcp_flags[0x9];
940 u8 tcp_sport[0x10];
941 u8 tcp_dport[0x10];
942 u8 reserved_at_c0[0x10];
943 u8 ipv4_ihl[0x4];
944 u8 l3_ok[0x1];
945 u8 l4_ok[0x1];
946 u8 ipv4_checksum_ok[0x1];
947 u8 l4_checksum_ok[0x1];
948 u8 ip_ttl_hoplimit[0x8];
949 u8 udp_sport[0x10];
950 u8 udp_dport[0x10];
951 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
952 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
953 };
954
955 struct mlx5_ifc_fte_match_mpls_bits {
956 u8 mpls_label[0x14];
957 u8 mpls_exp[0x3];
958 u8 mpls_s_bos[0x1];
959 u8 mpls_ttl[0x8];
960 };
961
962 struct mlx5_ifc_fte_match_set_misc2_bits {
963 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
964 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
965 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
966 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
967 u8 metadata_reg_c_7[0x20];
968 u8 metadata_reg_c_6[0x20];
969 u8 metadata_reg_c_5[0x20];
970 u8 metadata_reg_c_4[0x20];
971 u8 metadata_reg_c_3[0x20];
972 u8 metadata_reg_c_2[0x20];
973 u8 metadata_reg_c_1[0x20];
974 u8 metadata_reg_c_0[0x20];
975 u8 metadata_reg_a[0x20];
976 u8 metadata_reg_b[0x20];
977 u8 reserved_at_1c0[0x40];
978 };
979
980 struct mlx5_ifc_fte_match_set_misc3_bits {
981 u8 inner_tcp_seq_num[0x20];
982 u8 outer_tcp_seq_num[0x20];
983 u8 inner_tcp_ack_num[0x20];
984 u8 outer_tcp_ack_num[0x20];
985 u8 reserved_at_auto1[0x8];
986 u8 outer_vxlan_gpe_vni[0x18];
987 u8 outer_vxlan_gpe_next_protocol[0x8];
988 u8 outer_vxlan_gpe_flags[0x8];
989 u8 reserved_at_a8[0x10];
990 u8 icmp_header_data[0x20];
991 u8 icmpv6_header_data[0x20];
992 u8 icmp_type[0x8];
993 u8 icmp_code[0x8];
994 u8 icmpv6_type[0x8];
995 u8 icmpv6_code[0x8];
996 u8 geneve_tlv_option_0_data[0x20];
997 u8 gtpu_teid[0x20];
998 u8 gtpu_msg_type[0x08];
999 u8 gtpu_msg_flags[0x08];
1000 u8 reserved_at_170[0x10];
1001 u8 gtpu_dw_2[0x20];
1002 u8 gtpu_first_ext_dw_0[0x20];
1003 u8 gtpu_dw_0[0x20];
1004 u8 reserved_at_240[0x20];
1005
1006 };
1007
1008 struct mlx5_ifc_fte_match_set_misc4_bits {
1009 u8 prog_sample_field_value_0[0x20];
1010 u8 prog_sample_field_id_0[0x20];
1011 u8 prog_sample_field_value_1[0x20];
1012 u8 prog_sample_field_id_1[0x20];
1013 u8 prog_sample_field_value_2[0x20];
1014 u8 prog_sample_field_id_2[0x20];
1015 u8 prog_sample_field_value_3[0x20];
1016 u8 prog_sample_field_id_3[0x20];
1017 u8 prog_sample_field_value_4[0x20];
1018 u8 prog_sample_field_id_4[0x20];
1019 u8 prog_sample_field_value_5[0x20];
1020 u8 prog_sample_field_id_5[0x20];
1021 u8 prog_sample_field_value_6[0x20];
1022 u8 prog_sample_field_id_6[0x20];
1023 u8 prog_sample_field_value_7[0x20];
1024 u8 prog_sample_field_id_7[0x20];
1025 };
1026
1027 struct mlx5_ifc_fte_match_set_misc5_bits {
1028 u8 macsec_tag_0[0x20];
1029 u8 macsec_tag_1[0x20];
1030 u8 macsec_tag_2[0x20];
1031 u8 macsec_tag_3[0x20];
1032 u8 tunnel_header_0[0x20];
1033 u8 tunnel_header_1[0x20];
1034 u8 tunnel_header_2[0x20];
1035 u8 tunnel_header_3[0x20];
1036 u8 reserved[0x100];
1037 };
1038
1039 /* Flow matcher. */
1040 struct mlx5_ifc_fte_match_param_bits {
1041 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1042 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1043 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1044 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1045 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1046 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1047 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1048 /*
1049 * Add reserved bit to match the struct size with the size defined in PRM.
1050 * This extension is not required in Linux.
1051 */
1052 #ifndef HAVE_INFINIBAND_VERBS_H
1053 u8 reserved_0[0x200];
1054 #endif
1055 };
1056
1057 struct mlx5_ifc_dest_format_struct_bits {
1058 u8 destination_type[0x8];
1059 u8 destination_id[0x18];
1060 u8 reserved_0[0x20];
1061 };
1062
1063 enum {
1064 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1065 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1066 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1067 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1068 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1069 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1070 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1071 };
1072
1073 enum {
1074 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1075 MLX5_CMD_OP_CREATE_MKEY = 0x200,
1076 MLX5_CMD_OP_CREATE_CQ = 0x400,
1077 MLX5_CMD_OP_CREATE_QP = 0x500,
1078 MLX5_CMD_OP_RST2INIT_QP = 0x502,
1079 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1080 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1081 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1082 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1083 MLX5_CMD_OP_QP_2ERR = 0x507,
1084 MLX5_CMD_OP_QP_2RST = 0x50A,
1085 MLX5_CMD_OP_QUERY_QP = 0x50B,
1086 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1087 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1088 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1089 MLX5_CMD_OP_RESUME_QP = 0x510,
1090 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1091 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1092 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1093 MLX5_CMD_OP_ALLOC_PD = 0x800,
1094 MLX5_CMD_OP_DEALLOC_PD = 0x801,
1095 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1096 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1097 MLX5_CMD_OP_QUERY_LAG = 0x842,
1098 MLX5_CMD_OP_CREATE_TIR = 0x900,
1099 MLX5_CMD_OP_MODIFY_TIR = 0x901,
1100 MLX5_CMD_OP_CREATE_SQ = 0X904,
1101 MLX5_CMD_OP_MODIFY_SQ = 0X905,
1102 MLX5_CMD_OP_CREATE_RQ = 0x908,
1103 MLX5_CMD_OP_MODIFY_RQ = 0x909,
1104 MLX5_CMD_OP_QUERY_RQ = 0x90b,
1105 MLX5_CMD_OP_CREATE_RMP = 0x90c,
1106 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
1107 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
1108 MLX5_CMD_OP_QUERY_RMP = 0x90f,
1109 MLX5_CMD_OP_CREATE_TIS = 0x912,
1110 MLX5_CMD_OP_QUERY_TIS = 0x915,
1111 MLX5_CMD_OP_CREATE_RQT = 0x916,
1112 MLX5_CMD_OP_MODIFY_RQT = 0x917,
1113 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1114 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1115 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1116 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1117 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1118 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1119 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1120 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1121 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1122 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1123 };
1124
1125 enum {
1126 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
1127 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
1128 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1129 };
1130
1131 #define MLX5_ADAPTER_PAGE_SHIFT 12
1132 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1133 /**
1134 * The batch counter dcs id starts from 0x800000 and none batch counter
1135 * starts from 0. As currently, the counter is changed to be indexed by
1136 * pool index and the offset of the counter in the pool counters_raw array.
1137 * It means now the counter index is same for batch and none batch counter.
1138 * Add the 0x800000 batch counter offset to the batch counter index helps
1139 * indicate the counter index is from batch or none batch container pool.
1140 */
1141 #define MLX5_CNT_BATCH_OFFSET 0x800000
1142
1143 /* The counter batch query requires ID align with 4. */
1144 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1145
1146 /* Flow counters. */
1147 struct mlx5_ifc_alloc_flow_counter_out_bits {
1148 u8 status[0x8];
1149 u8 reserved_at_8[0x18];
1150 u8 syndrome[0x20];
1151 u8 flow_counter_id[0x20];
1152 u8 reserved_at_60[0x20];
1153 };
1154
1155 struct mlx5_ifc_alloc_flow_counter_in_bits {
1156 u8 opcode[0x10];
1157 u8 reserved_at_10[0x10];
1158 u8 reserved_at_20[0x10];
1159 u8 op_mod[0x10];
1160 u8 flow_counter_id[0x20];
1161 u8 reserved_at_40[0x18];
1162 u8 flow_counter_bulk[0x8];
1163 };
1164
1165 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1166 u8 status[0x8];
1167 u8 reserved_at_8[0x18];
1168 u8 syndrome[0x20];
1169 u8 reserved_at_40[0x40];
1170 };
1171
1172 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1173 u8 opcode[0x10];
1174 u8 reserved_at_10[0x10];
1175 u8 reserved_at_20[0x10];
1176 u8 op_mod[0x10];
1177 u8 flow_counter_id[0x20];
1178 u8 reserved_at_60[0x20];
1179 };
1180
1181 struct mlx5_ifc_traffic_counter_bits {
1182 u8 packets[0x40];
1183 u8 octets[0x40];
1184 };
1185
1186 struct mlx5_ifc_query_flow_counter_out_bits {
1187 u8 status[0x8];
1188 u8 reserved_at_8[0x18];
1189 u8 syndrome[0x20];
1190 u8 reserved_at_40[0x40];
1191 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1192 };
1193
1194 struct mlx5_ifc_query_flow_counter_in_bits {
1195 u8 opcode[0x10];
1196 u8 reserved_at_10[0x10];
1197 u8 reserved_at_20[0x10];
1198 u8 op_mod[0x10];
1199 u8 reserved_at_40[0x20];
1200 u8 mkey[0x20];
1201 u8 address[0x40];
1202 u8 clear[0x1];
1203 u8 dump_to_memory[0x1];
1204 u8 num_of_counters[0x1e];
1205 u8 flow_counter_id[0x20];
1206 };
1207
1208 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1209 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1210
1211 struct mlx5_ifc_klm_bits {
1212 u8 byte_count[0x20];
1213 u8 mkey[0x20];
1214 u8 address[0x40];
1215 };
1216
1217 struct mlx5_ifc_mkc_bits {
1218 u8 reserved_at_0[0x1];
1219 u8 free[0x1];
1220 u8 reserved_at_2[0x1];
1221 u8 access_mode_4_2[0x3];
1222 u8 reserved_at_6[0x7];
1223 u8 relaxed_ordering_write[0x1];
1224 u8 reserved_at_e[0x1];
1225 u8 small_fence_on_rdma_read_response[0x1];
1226 u8 umr_en[0x1];
1227 u8 a[0x1];
1228 u8 rw[0x1];
1229 u8 rr[0x1];
1230 u8 lw[0x1];
1231 u8 lr[0x1];
1232 u8 access_mode_1_0[0x2];
1233 u8 reserved_at_18[0x8];
1234 u8 qpn[0x18];
1235 u8 mkey_7_0[0x8];
1236 u8 reserved_at_40[0x20];
1237 u8 length64[0x1];
1238 u8 bsf_en[0x1];
1239 u8 sync_umr[0x1];
1240 u8 reserved_at_63[0x2];
1241 u8 expected_sigerr_count[0x1];
1242 u8 reserved_at_66[0x1];
1243 u8 en_rinval[0x1];
1244 u8 pd[0x18];
1245 u8 start_addr[0x40];
1246 u8 len[0x40];
1247 u8 bsf_octword_size[0x20];
1248 u8 reserved_at_120[0x80];
1249 u8 translations_octword_size[0x20];
1250 u8 reserved_at_1c0[0x19];
1251 u8 relaxed_ordering_read[0x1];
1252 u8 reserved_at_1da[0x1];
1253 u8 log_page_size[0x5];
1254 u8 reserved_at_1e0[0x3];
1255 u8 crypto_en[0x2];
1256 u8 reserved_at_1e5[0x1b];
1257 };
1258
1259 /* Range of values for MKEY context crypto_en field. */
1260 enum {
1261 MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1262 MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1263 };
1264
1265 struct mlx5_ifc_create_mkey_out_bits {
1266 u8 status[0x8];
1267 u8 reserved_at_8[0x18];
1268 u8 syndrome[0x20];
1269 u8 reserved_at_40[0x8];
1270 u8 mkey_index[0x18];
1271 u8 reserved_at_60[0x20];
1272 };
1273
1274 struct mlx5_ifc_create_mkey_in_bits {
1275 u8 opcode[0x10];
1276 u8 reserved_at_10[0x10];
1277 u8 reserved_at_20[0x10];
1278 u8 op_mod[0x10];
1279 u8 reserved_at_40[0x20];
1280 u8 pg_access[0x1];
1281 u8 reserved_at_61[0x1f];
1282 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1283 u8 reserved_at_280[0x80];
1284 u8 translations_octword_actual_size[0x20];
1285 u8 mkey_umem_id[0x20];
1286 u8 mkey_umem_offset[0x40];
1287 u8 reserved_at_380[0x500];
1288 u8 klm_pas_mtt[][0x20];
1289 };
1290
1291 enum {
1292 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1293 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1294 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1295 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1296 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1297 MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,
1298 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1299 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
1300 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1301 };
1302
1303 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1304 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1305 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1306 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1307 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1308 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1309 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1310 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1311 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1312 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1313 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1314 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1315 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1316 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1317 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1318 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1319 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1320 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1321 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1322 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1323 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1324 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1325
1326 enum {
1327 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1328 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1329 };
1330
1331 enum {
1332 MLX5_CAP_INLINE_MODE_L2,
1333 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1334 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1335 };
1336
1337 enum {
1338 MLX5_INLINE_MODE_NONE,
1339 MLX5_INLINE_MODE_L2,
1340 MLX5_INLINE_MODE_IP,
1341 MLX5_INLINE_MODE_TCP_UDP,
1342 MLX5_INLINE_MODE_RESERVED4,
1343 MLX5_INLINE_MODE_INNER_L2,
1344 MLX5_INLINE_MODE_INNER_IP,
1345 MLX5_INLINE_MODE_INNER_TCP_UDP,
1346 };
1347
1348 /* The supported timestamp formats reported in HCA attributes. */
1349 enum {
1350 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1351 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1352 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1353 };
1354
1355 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1356 enum {
1357 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1358 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
1359 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
1360 };
1361
1362 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1363 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1364 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1365 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1366 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1367 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1368 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1369 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1370 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1371 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1372 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1373
1374 /* The device steering logic format. */
1375 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
1376 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
1377
1378 struct mlx5_ifc_cmd_hca_cap_bits {
1379 u8 reserved_at_0[0x20];
1380 u8 hca_cap_2[0x1];
1381 u8 reserved_at_21[0xf];
1382 u8 vhca_id[0x10];
1383 u8 reserved_at_40[0x20];
1384 u8 reserved_at_60[0x3];
1385 u8 log_regexp_scatter_gather_size[0x5];
1386 u8 reserved_at_68[0x3];
1387 u8 log_dma_mmo_size[0x5];
1388 u8 reserved_at_70[0x3];
1389 u8 log_compress_mmo_size[0x5];
1390 u8 reserved_at_78[0x3];
1391 u8 log_decompress_mmo_size[0x5];
1392 u8 log_max_srq_sz[0x8];
1393 u8 log_max_qp_sz[0x8];
1394 u8 reserved_at_90[0x9];
1395 u8 wqe_index_ignore_cap[0x1];
1396 u8 dynamic_qp_allocation[0x1];
1397 u8 log_max_qp[0x5];
1398 u8 reserved_at_a0[0x4];
1399 u8 regexp_num_of_engines[0x4];
1400 u8 reserved_at_a8[0x1];
1401 u8 reg_c_preserve[0x1];
1402 u8 reserved_at_aa[0x1];
1403 u8 log_max_srq[0x5];
1404 u8 reserved_at_b0[0xb];
1405 u8 scatter_fcs_w_decap_disable[0x1];
1406 u8 reserved_at_bc[0x4];
1407 u8 reserved_at_c0[0x8];
1408 u8 log_max_cq_sz[0x8];
1409 u8 reserved_at_d0[0x2];
1410 u8 access_register_user[0x1];
1411 u8 reserved_at_d3[0x8];
1412 u8 log_max_cq[0x5];
1413 u8 log_max_eq_sz[0x8];
1414 u8 relaxed_ordering_write[0x1];
1415 u8 relaxed_ordering_read[0x1];
1416 u8 log_max_mkey[0x6];
1417 u8 reserved_at_f0[0x8];
1418 u8 dump_fill_mkey[0x1];
1419 u8 reserved_at_f9[0x3];
1420 u8 log_max_eq[0x4];
1421 u8 max_indirection[0x8];
1422 u8 fixed_buffer_size[0x1];
1423 u8 log_max_mrw_sz[0x7];
1424 u8 force_teardown[0x1];
1425 u8 reserved_at_111[0x1];
1426 u8 log_max_bsf_list_size[0x6];
1427 u8 umr_extended_translation_offset[0x1];
1428 u8 null_mkey[0x1];
1429 u8 log_max_klm_list_size[0x6];
1430 u8 non_wire_sq[0x1];
1431 u8 reserved_at_121[0x9];
1432 u8 log_max_ra_req_dc[0x6];
1433 u8 reserved_at_130[0x3];
1434 u8 log_max_static_sq_wq[0x5];
1435 u8 reserved_at_138[0x2];
1436 u8 log_max_ra_res_dc[0x6];
1437 u8 reserved_at_140[0xa];
1438 u8 log_max_ra_req_qp[0x6];
1439 u8 rtr2rts_qp_counters_set_id[0x1];
1440 u8 rts2rts_udp_sport[0x1];
1441 u8 rts2rts_lag_tx_port_affinity[0x1];
1442 u8 dma_mmo_sq[0x1];
1443 u8 compress_min_block_size[0x4];
1444 u8 compress_mmo_sq[0x1];
1445 u8 decompress_mmo_sq[0x1];
1446 u8 log_max_ra_res_qp[0x6];
1447 u8 end_pad[0x1];
1448 u8 cc_query_allowed[0x1];
1449 u8 cc_modify_allowed[0x1];
1450 u8 start_pad[0x1];
1451 u8 cache_line_128byte[0x1];
1452 u8 reserved_at_165[0xa];
1453 u8 qcam_reg[0x1];
1454 u8 gid_table_size[0x10];
1455 u8 out_of_seq_cnt[0x1];
1456 u8 vport_counters[0x1];
1457 u8 retransmission_q_counters[0x1];
1458 u8 debug[0x1];
1459 u8 modify_rq_counter_set_id[0x1];
1460 u8 rq_delay_drop[0x1];
1461 u8 max_qp_cnt[0xa];
1462 u8 pkey_table_size[0x10];
1463 u8 vport_group_manager[0x1];
1464 u8 vhca_group_manager[0x1];
1465 u8 ib_virt[0x1];
1466 u8 eth_virt[0x1];
1467 u8 vnic_env_queue_counters[0x1];
1468 u8 ets[0x1];
1469 u8 nic_flow_table[0x1];
1470 u8 eswitch_manager[0x1];
1471 u8 device_memory[0x1];
1472 u8 mcam_reg[0x1];
1473 u8 pcam_reg[0x1];
1474 u8 local_ca_ack_delay[0x5];
1475 u8 port_module_event[0x1];
1476 u8 enhanced_error_q_counters[0x1];
1477 u8 ports_check[0x1];
1478 u8 reserved_at_1b3[0x1];
1479 u8 disable_link_up[0x1];
1480 u8 beacon_led[0x1];
1481 u8 port_type[0x2];
1482 u8 num_ports[0x8];
1483 u8 reserved_at_1c0[0x1];
1484 u8 pps[0x1];
1485 u8 pps_modify[0x1];
1486 u8 log_max_msg[0x5];
1487 u8 reserved_at_1c8[0x4];
1488 u8 max_tc[0x4];
1489 u8 temp_warn_event[0x1];
1490 u8 dcbx[0x1];
1491 u8 general_notification_event[0x1];
1492 u8 reserved_at_1d3[0x2];
1493 u8 fpga[0x1];
1494 u8 rol_s[0x1];
1495 u8 rol_g[0x1];
1496 u8 reserved_at_1d8[0x1];
1497 u8 wol_s[0x1];
1498 u8 wol_g[0x1];
1499 u8 wol_a[0x1];
1500 u8 wol_b[0x1];
1501 u8 wol_m[0x1];
1502 u8 wol_u[0x1];
1503 u8 wol_p[0x1];
1504 u8 stat_rate_support[0x10];
1505 u8 reserved_at_1f0[0xc];
1506 u8 cqe_version[0x4];
1507 u8 compact_address_vector[0x1];
1508 u8 striding_rq[0x1];
1509 u8 reserved_at_202[0x1];
1510 u8 ipoib_enhanced_offloads[0x1];
1511 u8 ipoib_basic_offloads[0x1];
1512 u8 reserved_at_205[0x1];
1513 u8 repeated_block_disabled[0x1];
1514 u8 umr_modify_entity_size_disabled[0x1];
1515 u8 umr_modify_atomic_disabled[0x1];
1516 u8 umr_indirect_mkey_disabled[0x1];
1517 u8 umr_fence[0x2];
1518 u8 reserved_at_20c[0x3];
1519 u8 drain_sigerr[0x1];
1520 u8 cmdif_checksum[0x2];
1521 u8 sigerr_cqe[0x1];
1522 u8 reserved_at_213[0x1];
1523 u8 wq_signature[0x1];
1524 u8 sctr_data_cqe[0x1];
1525 u8 reserved_at_216[0x1];
1526 u8 sho[0x1];
1527 u8 tph[0x1];
1528 u8 rf[0x1];
1529 u8 dct[0x1];
1530 u8 qos[0x1];
1531 u8 eth_net_offloads[0x1];
1532 u8 roce[0x1];
1533 u8 atomic[0x1];
1534 u8 reserved_at_21f[0x1];
1535 u8 cq_oi[0x1];
1536 u8 cq_resize[0x1];
1537 u8 cq_moderation[0x1];
1538 u8 reserved_at_223[0x3];
1539 u8 cq_eq_remap[0x1];
1540 u8 pg[0x1];
1541 u8 block_lb_mc[0x1];
1542 u8 reserved_at_229[0x1];
1543 u8 scqe_break_moderation[0x1];
1544 u8 cq_period_start_from_cqe[0x1];
1545 u8 cd[0x1];
1546 u8 reserved_at_22d[0x1];
1547 u8 apm[0x1];
1548 u8 vector_calc[0x1];
1549 u8 umr_ptr_rlky[0x1];
1550 u8 imaicl[0x1];
1551 u8 reserved_at_232[0x4];
1552 u8 qkv[0x1];
1553 u8 pkv[0x1];
1554 u8 set_deth_sqpn[0x1];
1555 u8 reserved_at_239[0x3];
1556 u8 xrc[0x1];
1557 u8 ud[0x1];
1558 u8 uc[0x1];
1559 u8 rc[0x1];
1560 u8 uar_4k[0x1];
1561 u8 reserved_at_241[0x8];
1562 u8 regexp_params[0x1];
1563 u8 uar_sz[0x6];
1564 u8 port_selection_cap[0x1];
1565 u8 reserved_at_251[0x7];
1566 u8 log_pg_sz[0x8];
1567 u8 bf[0x1];
1568 u8 driver_version[0x1];
1569 u8 pad_tx_eth_packet[0x1];
1570 u8 reserved_at_263[0x8];
1571 u8 log_bf_reg_size[0x5];
1572 u8 reserved_at_270[0xb];
1573 u8 lag_master[0x1];
1574 u8 num_lag_ports[0x4];
1575 u8 reserved_at_280[0x10];
1576 u8 max_wqe_sz_sq[0x10];
1577 u8 reserved_at_2a0[0xc];
1578 u8 regexp_mmo_sq[0x1];
1579 u8 regexp_version[0x3];
1580 u8 max_wqe_sz_rq[0x10];
1581 u8 max_flow_counter_31_16[0x10];
1582 u8 max_wqe_sz_sq_dc[0x10];
1583 u8 reserved_at_2e0[0x7];
1584 u8 max_qp_mcg[0x19];
1585 u8 reserved_at_300[0x10];
1586 u8 flow_counter_bulk_alloc[0x08];
1587 u8 log_max_mcg[0x8];
1588 u8 reserved_at_320[0x3];
1589 u8 log_max_transport_domain[0x5];
1590 u8 reserved_at_328[0x3];
1591 u8 log_max_pd[0x5];
1592 u8 reserved_at_330[0xb];
1593 u8 log_max_xrcd[0x5];
1594 u8 nic_receive_steering_discard[0x1];
1595 u8 receive_discard_vport_down[0x1];
1596 u8 transmit_discard_vport_down[0x1];
1597 u8 reserved_at_343[0x5];
1598 u8 log_max_flow_counter_bulk[0x8];
1599 u8 max_flow_counter_15_0[0x10];
1600 u8 modify_tis[0x1];
1601 u8 flow_counters_dump[0x1];
1602 u8 reserved_at_360[0x1];
1603 u8 log_max_rq[0x5];
1604 u8 reserved_at_368[0x3];
1605 u8 log_max_sq[0x5];
1606 u8 reserved_at_370[0x3];
1607 u8 log_max_tir[0x5];
1608 u8 reserved_at_378[0x3];
1609 u8 log_max_tis[0x5];
1610 u8 basic_cyclic_rcv_wqe[0x1];
1611 u8 reserved_at_381[0x1];
1612 u8 mem_rq_rmp[0x1];
1613 u8 log_max_rmp[0x5];
1614 u8 reserved_at_388[0x3];
1615 u8 log_max_rqt[0x5];
1616 u8 reserved_at_390[0x3];
1617 u8 log_max_rqt_size[0x5];
1618 u8 reserved_at_398[0x3];
1619 u8 log_max_tis_per_sq[0x5];
1620 u8 ext_stride_num_range[0x1];
1621 u8 reserved_at_3a1[0x2];
1622 u8 log_max_stride_sz_rq[0x5];
1623 u8 reserved_at_3a8[0x3];
1624 u8 log_min_stride_sz_rq[0x5];
1625 u8 reserved_at_3b0[0x3];
1626 u8 log_max_stride_sz_sq[0x5];
1627 u8 reserved_at_3b8[0x3];
1628 u8 log_min_stride_sz_sq[0x5];
1629 u8 hairpin[0x1];
1630 u8 reserved_at_3c1[0x2];
1631 u8 log_max_hairpin_queues[0x5];
1632 u8 reserved_at_3c8[0x3];
1633 u8 log_max_hairpin_wq_data_sz[0x5];
1634 u8 reserved_at_3d0[0x3];
1635 u8 log_max_hairpin_num_packets[0x5];
1636 u8 reserved_at_3d8[0x3];
1637 u8 log_max_wq_sz[0x5];
1638 u8 nic_vport_change_event[0x1];
1639 u8 disable_local_lb_uc[0x1];
1640 u8 disable_local_lb_mc[0x1];
1641 u8 log_min_hairpin_wq_data_sz[0x5];
1642 u8 reserved_at_3e8[0x3];
1643 u8 log_max_vlan_list[0x5];
1644 u8 reserved_at_3f0[0x3];
1645 u8 log_max_current_mc_list[0x5];
1646 u8 reserved_at_3f8[0x3];
1647 u8 log_max_current_uc_list[0x5];
1648 u8 general_obj_types[0x40];
1649 u8 sq_ts_format[0x2];
1650 u8 rq_ts_format[0x2];
1651 u8 steering_format_version[0x4];
1652 u8 reserved_at_448[0x18];
1653 u8 reserved_at_460[0x8];
1654 u8 aes_xts[0x1];
1655 u8 crypto[0x1];
1656 u8 reserved_at_46a[0x6];
1657 u8 max_num_eqs[0x10];
1658 u8 reserved_at_480[0x3];
1659 u8 log_max_l2_table[0x5];
1660 u8 reserved_at_488[0x8];
1661 u8 log_uar_page_sz[0x10];
1662 u8 reserved_at_4a0[0x20];
1663 u8 device_frequency_mhz[0x20];
1664 u8 device_frequency_khz[0x20];
1665 u8 reserved_at_500[0x20];
1666 u8 num_of_uars_per_page[0x20];
1667 u8 flex_parser_protocols[0x20];
1668 u8 max_geneve_tlv_options[0x8];
1669 u8 reserved_at_568[0x3];
1670 u8 max_geneve_tlv_option_data_len[0x5];
1671 u8 reserved_at_570[0x49];
1672 u8 mini_cqe_resp_l3_l4_tag[0x1];
1673 u8 mini_cqe_resp_flow_tag[0x1];
1674 u8 enhanced_cqe_compression[0x1];
1675 u8 mini_cqe_resp_stride_index[0x1];
1676 u8 cqe_128_always[0x1];
1677 u8 cqe_compression_128[0x1];
1678 u8 cqe_compression[0x1];
1679 u8 cqe_compression_timeout[0x10];
1680 u8 cqe_compression_max_num[0x10];
1681 u8 reserved_at_5e0[0x10];
1682 u8 tag_matching[0x1];
1683 u8 rndv_offload_rc[0x1];
1684 u8 rndv_offload_dc[0x1];
1685 u8 log_tag_matching_list_sz[0x5];
1686 u8 reserved_at_5f8[0x3];
1687 u8 log_max_xrq[0x5];
1688 u8 affiliate_nic_vport_criteria[0x8];
1689 u8 native_port_num[0x8];
1690 u8 num_vhca_ports[0x8];
1691 u8 reserved_at_618[0x6];
1692 u8 sw_owner_id[0x1];
1693 u8 reserved_at_61f[0x6C];
1694 u8 wait_on_data[0x1];
1695 u8 wait_on_time[0x1];
1696 u8 reserved_at_68d[0xBB];
1697 u8 dma_mmo_qp[0x1];
1698 u8 regexp_mmo_qp[0x1];
1699 u8 compress_mmo_qp[0x1];
1700 u8 decompress_mmo_qp[0x1];
1701 u8 reserved_at_624[0xd4];
1702 };
1703
1704 struct mlx5_ifc_qos_cap_bits {
1705 u8 packet_pacing[0x1];
1706 u8 esw_scheduling[0x1];
1707 u8 esw_bw_share[0x1];
1708 u8 esw_rate_limit[0x1];
1709 u8 reserved_at_4[0x1];
1710 u8 packet_pacing_burst_bound[0x1];
1711 u8 packet_pacing_typical_size[0x1];
1712 u8 flow_meter_old[0x1];
1713 u8 reserved_at_8[0x8];
1714 u8 log_max_flow_meter[0x8];
1715 u8 flow_meter_reg_id[0x8];
1716 u8 wqe_rate_pp[0x1];
1717 u8 reserved_at_25[0x7];
1718 u8 flow_meter[0x1];
1719 u8 reserved_at_2e[0x17];
1720 u8 packet_pacing_max_rate[0x20];
1721 u8 packet_pacing_min_rate[0x20];
1722 u8 reserved_at_80[0x10];
1723 u8 packet_pacing_rate_table_size[0x10];
1724 u8 esw_element_type[0x10];
1725 u8 esw_tsar_type[0x10];
1726 u8 reserved_at_c0[0x10];
1727 u8 max_qos_para_vport[0x10];
1728 u8 max_tsar_bw_share[0x20];
1729 u8 nic_element_type[0x10];
1730 u8 nic_tsar_type[0x10];
1731 u8 reserved_at_120[0x3];
1732 u8 log_meter_aso_granularity[0x5];
1733 u8 reserved_at_128[0x3];
1734 u8 log_meter_aso_max_alloc[0x5];
1735 u8 reserved_at_130[0x3];
1736 u8 log_max_num_meter_aso[0x5];
1737 u8 reserved_at_138[0x6b0];
1738 };
1739
1740 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1741 u8 csum_cap[0x1];
1742 u8 vlan_cap[0x1];
1743 u8 lro_cap[0x1];
1744 u8 lro_psh_flag[0x1];
1745 u8 lro_time_stamp[0x1];
1746 u8 lro_max_msg_sz_mode[0x2];
1747 u8 wqe_vlan_insert[0x1];
1748 u8 self_lb_en_modifiable[0x1];
1749 u8 self_lb_mc[0x1];
1750 u8 self_lb_uc[0x1];
1751 u8 max_lso_cap[0x5];
1752 u8 multi_pkt_send_wqe[0x2];
1753 u8 wqe_inline_mode[0x2];
1754 u8 rss_ind_tbl_cap[0x4];
1755 u8 reg_umr_sq[0x1];
1756 u8 scatter_fcs[0x1];
1757 u8 enhanced_multi_pkt_send_wqe[0x1];
1758 u8 tunnel_lso_const_out_ip_id[0x1];
1759 u8 tunnel_lro_gre[0x1];
1760 u8 tunnel_lro_vxlan[0x1];
1761 u8 tunnel_stateless_gre[0x1];
1762 u8 tunnel_stateless_vxlan[0x1];
1763 u8 swp[0x1];
1764 u8 swp_csum[0x1];
1765 u8 swp_lso[0x1];
1766 u8 reserved_at_23[0x8];
1767 u8 tunnel_stateless_gtp[0x1];
1768 u8 reserved_at_25[0x4];
1769 u8 max_vxlan_udp_ports[0x8];
1770 u8 reserved_at_38[0x6];
1771 u8 max_geneve_opt_len[0x1];
1772 u8 tunnel_stateless_geneve_rx[0x1];
1773 u8 reserved_at_40[0x10];
1774 u8 lro_min_mss_size[0x10];
1775 u8 reserved_at_60[0x120];
1776 u8 lro_timer_supported_periods[4][0x20];
1777 u8 reserved_at_200[0x600];
1778 };
1779
1780 enum {
1781 MLX5_VIRTQ_TYPE_SPLIT = 0,
1782 MLX5_VIRTQ_TYPE_PACKED = 1,
1783 };
1784
1785 enum {
1786 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1787 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1788 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1789 };
1790
1791 struct mlx5_ifc_virtio_emulation_cap_bits {
1792 u8 desc_tunnel_offload_type[0x1];
1793 u8 eth_frame_offload_type[0x1];
1794 u8 virtio_version_1_0[0x1];
1795 u8 tso_ipv4[0x1];
1796 u8 tso_ipv6[0x1];
1797 u8 tx_csum[0x1];
1798 u8 rx_csum[0x1];
1799 u8 reserved_at_7[0x1][0x9];
1800 u8 event_mode[0x8];
1801 u8 virtio_queue_type[0x8];
1802 u8 reserved_at_20[0x13];
1803 u8 log_doorbell_stride[0x5];
1804 u8 reserved_at_3b[0x3];
1805 u8 log_doorbell_bar_size[0x5];
1806 u8 doorbell_bar_offset[0x40];
1807 u8 reserved_at_80[0x8];
1808 u8 max_num_virtio_queues[0x18];
1809 u8 reserved_at_a0[0x60];
1810 u8 umem_1_buffer_param_a[0x20];
1811 u8 umem_1_buffer_param_b[0x20];
1812 u8 umem_2_buffer_param_a[0x20];
1813 u8 umem_2_buffer_param_b[0x20];
1814 u8 umem_3_buffer_param_a[0x20];
1815 u8 umem_3_buffer_param_b[0x20];
1816 u8 reserved_at_1c0[0x620];
1817 };
1818
1819 /**
1820 * PARSE_GRAPH_NODE Capabilities Field Descriptions
1821 */
1822 struct mlx5_ifc_parse_graph_node_cap_bits {
1823 u8 node_in[0x20];
1824 u8 node_out[0x20];
1825 u8 header_length_mode[0x10];
1826 u8 sample_offset_mode[0x10];
1827 u8 max_num_arc_in[0x08];
1828 u8 max_num_arc_out[0x08];
1829 u8 max_num_sample[0x08];
1830 u8 reserved_at_78[0x07];
1831 u8 sample_id_in_out[0x1];
1832 u8 max_base_header_length[0x10];
1833 u8 reserved_at_90[0x08];
1834 u8 max_sample_base_offset[0x08];
1835 u8 max_next_header_offset[0x10];
1836 u8 reserved_at_b0[0x08];
1837 u8 header_length_mask_width[0x08];
1838 };
1839
1840 struct mlx5_ifc_flow_table_prop_layout_bits {
1841 u8 ft_support[0x1];
1842 u8 flow_tag[0x1];
1843 u8 flow_counter[0x1];
1844 u8 flow_modify_en[0x1];
1845 u8 modify_root[0x1];
1846 u8 identified_miss_table[0x1];
1847 u8 flow_table_modify[0x1];
1848 u8 reformat[0x1];
1849 u8 decap[0x1];
1850 u8 reset_root_to_default[0x1];
1851 u8 pop_vlan[0x1];
1852 u8 push_vlan[0x1];
1853 u8 fpga_vendor_acceleration[0x1];
1854 u8 pop_vlan_2[0x1];
1855 u8 push_vlan_2[0x1];
1856 u8 reformat_and_vlan_action[0x1];
1857 u8 modify_and_vlan_action[0x1];
1858 u8 sw_owner[0x1];
1859 u8 reformat_l3_tunnel_to_l2[0x1];
1860 u8 reformat_l2_to_l3_tunnel[0x1];
1861 u8 reformat_and_modify_action[0x1];
1862 u8 reserved_at_15[0x9];
1863 u8 sw_owner_v2[0x1];
1864 u8 reserved_at_1f[0x1];
1865 u8 reserved_at_20[0x2];
1866 u8 log_max_ft_size[0x6];
1867 u8 log_max_modify_header_context[0x8];
1868 u8 max_modify_header_actions[0x8];
1869 u8 max_ft_level[0x8];
1870 u8 reserved_at_40[0x8];
1871 u8 log_max_ft_sampler_num[8];
1872 u8 metadata_reg_b_width[0x8];
1873 u8 metadata_reg_a_width[0x8];
1874 u8 reserved_at_60[0x18];
1875 u8 log_max_ft_num[0x8];
1876 u8 reserved_at_80[0x10];
1877 u8 log_max_flow_counter[0x8];
1878 u8 log_max_destination[0x8];
1879 u8 reserved_at_a0[0x18];
1880 u8 log_max_flow[0x8];
1881 u8 reserved_at_c0[0x140];
1882 };
1883
1884 struct mlx5_ifc_roce_caps_bits {
1885 u8 reserved_0[0x1e];
1886 u8 qp_ts_format[0x2];
1887 u8 reserved_at_20[0x7e0];
1888 };
1889
1890 /*
1891 * Table 1872 - Flow Table Fields Supported 2 Format
1892 */
1893 struct mlx5_ifc_ft_fields_support_2_bits {
1894 u8 reserved_at_0[0xf];
1895 u8 tunnel_header_2_3[0x1];
1896 u8 tunnel_header_0_1[0x1];
1897 u8 macsec_syndrome[0x1];
1898 u8 macsec_tag[0x1];
1899 u8 outer_lrh_sl[0x1];
1900 u8 inner_ipv4_ihl[0x1];
1901 u8 outer_ipv4_ihl[0x1];
1902 u8 psp_syndrome[0x1];
1903 u8 inner_l3_ok[0x1];
1904 u8 inner_l4_ok[0x1];
1905 u8 outer_l3_ok[0x1];
1906 u8 outer_l4_ok[0x1];
1907 u8 psp_header[0x1];
1908 u8 inner_ipv4_checksum_ok[0x1];
1909 u8 inner_l4_checksum_ok[0x1];
1910 u8 outer_ipv4_checksum_ok[0x1];
1911 u8 outer_l4_checksum_ok[0x1];
1912 u8 reserved_at_20[0x60];
1913 };
1914
1915 struct mlx5_ifc_flow_table_nic_cap_bits {
1916 u8 reserved_at_0[0x200];
1917 struct mlx5_ifc_flow_table_prop_layout_bits
1918 flow_table_properties_nic_receive;
1919 struct mlx5_ifc_flow_table_prop_layout_bits
1920 flow_table_properties_nic_receive_rdma;
1921 struct mlx5_ifc_flow_table_prop_layout_bits
1922 flow_table_properties_nic_receive_sniffer;
1923 struct mlx5_ifc_flow_table_prop_layout_bits
1924 flow_table_properties_nic_transmit;
1925 struct mlx5_ifc_flow_table_prop_layout_bits
1926 flow_table_properties_nic_transmit_rdma;
1927 struct mlx5_ifc_flow_table_prop_layout_bits
1928 flow_table_properties_nic_transmit_sniffer;
1929 u8 reserved_at_e00[0x600];
1930 struct mlx5_ifc_ft_fields_support_2_bits
1931 ft_field_support_2_nic_receive;
1932 };
1933
1934 /*
1935 * HCA Capabilities 2
1936 */
1937 struct mlx5_ifc_cmd_hca_cap_2_bits {
1938 u8 reserved_at_0[0x80]; /* End of DW4. */
1939 u8 reserved_at_80[0x3];
1940 u8 max_num_prog_sample_field[0x5];
1941 u8 reserved_at_88[0x3];
1942 u8 log_max_num_reserved_qpn[0x5];
1943 u8 reserved_at_90[0x3];
1944 u8 log_reserved_qpn_granularity[0x5];
1945 u8 reserved_at_98[0x3];
1946 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1947 u8 max_reformat_insert_size[0x8];
1948 u8 max_reformat_insert_offset[0x8];
1949 u8 max_reformat_remove_size[0x8];
1950 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1951 u8 reserved_at_c0[0x3];
1952 u8 log_min_stride_wqe_sz[0x5];
1953 u8 reserved_at_c8[0x3];
1954 u8 log_conn_track_granularity[0x5];
1955 u8 reserved_at_d0[0x3];
1956 u8 log_conn_track_max_alloc[0x5];
1957 u8 reserved_at_d8[0x3];
1958 u8 log_max_conn_track_offload[0x5];
1959 u8 reserved_at_e0[0x20]; /* End of DW7. */
1960 u8 reserved_at_100[0x700];
1961 };
1962
1963 struct mlx5_ifc_esw_cap_bits {
1964 u8 reserved_at_0[0x60];
1965
1966 u8 esw_manager_vport_number_valid[0x1];
1967 u8 reserved_at_61[0xf];
1968 u8 esw_manager_vport_number[0x10];
1969
1970 u8 reserved_at_80[0x780];
1971 };
1972
1973 union mlx5_ifc_hca_cap_union_bits {
1974 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1975 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
1976 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1977 per_protocol_networking_offload_caps;
1978 struct mlx5_ifc_qos_cap_bits qos_cap;
1979 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1980 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1981 struct mlx5_ifc_esw_cap_bits esw_cap;
1982 struct mlx5_ifc_roce_caps_bits roce_caps;
1983 u8 reserved_at_0[0x8000];
1984 };
1985
1986 struct mlx5_ifc_set_action_in_bits {
1987 u8 action_type[0x4];
1988 u8 field[0xc];
1989 u8 reserved_at_10[0x3];
1990 u8 offset[0x5];
1991 u8 reserved_at_18[0x3];
1992 u8 length[0x5];
1993 u8 data[0x20];
1994 };
1995
1996 struct mlx5_ifc_query_hca_cap_out_bits {
1997 u8 status[0x8];
1998 u8 reserved_at_8[0x18];
1999 u8 syndrome[0x20];
2000 u8 reserved_at_40[0x40];
2001 union mlx5_ifc_hca_cap_union_bits capability;
2002 };
2003
2004 struct mlx5_ifc_query_hca_cap_in_bits {
2005 u8 opcode[0x10];
2006 u8 reserved_at_10[0x10];
2007 u8 reserved_at_20[0x10];
2008 u8 op_mod[0x10];
2009 u8 reserved_at_40[0x40];
2010 };
2011
2012 struct mlx5_ifc_mac_address_layout_bits {
2013 u8 reserved_at_0[0x10];
2014 u8 mac_addr_47_32[0x10];
2015 u8 mac_addr_31_0[0x20];
2016 };
2017
2018 struct mlx5_ifc_nic_vport_context_bits {
2019 u8 reserved_at_0[0x5];
2020 u8 min_wqe_inline_mode[0x3];
2021 u8 reserved_at_8[0x15];
2022 u8 disable_mc_local_lb[0x1];
2023 u8 disable_uc_local_lb[0x1];
2024 u8 roce_en[0x1];
2025 u8 arm_change_event[0x1];
2026 u8 reserved_at_21[0x1a];
2027 u8 event_on_mtu[0x1];
2028 u8 event_on_promisc_change[0x1];
2029 u8 event_on_vlan_change[0x1];
2030 u8 event_on_mc_address_change[0x1];
2031 u8 event_on_uc_address_change[0x1];
2032 u8 reserved_at_40[0xc];
2033 u8 affiliation_criteria[0x4];
2034 u8 affiliated_vhca_id[0x10];
2035 u8 reserved_at_60[0xd0];
2036 u8 mtu[0x10];
2037 u8 system_image_guid[0x40];
2038 u8 port_guid[0x40];
2039 u8 node_guid[0x40];
2040 u8 reserved_at_200[0x140];
2041 u8 qkey_violation_counter[0x10];
2042 u8 reserved_at_350[0x430];
2043 u8 promisc_uc[0x1];
2044 u8 promisc_mc[0x1];
2045 u8 promisc_all[0x1];
2046 u8 reserved_at_783[0x2];
2047 u8 allowed_list_type[0x3];
2048 u8 reserved_at_788[0xc];
2049 u8 allowed_list_size[0xc];
2050 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2051 u8 reserved_at_7e0[0x20];
2052 };
2053
2054 struct mlx5_ifc_query_nic_vport_context_out_bits {
2055 u8 status[0x8];
2056 u8 reserved_at_8[0x18];
2057 u8 syndrome[0x20];
2058 u8 reserved_at_40[0x40];
2059 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
2060 };
2061
2062 struct mlx5_ifc_query_nic_vport_context_in_bits {
2063 u8 opcode[0x10];
2064 u8 reserved_at_10[0x10];
2065 u8 reserved_at_20[0x10];
2066 u8 op_mod[0x10];
2067 u8 other_vport[0x1];
2068 u8 reserved_at_41[0xf];
2069 u8 vport_number[0x10];
2070 u8 reserved_at_60[0x5];
2071 u8 allowed_list_type[0x3];
2072 u8 reserved_at_68[0x18];
2073 };
2074
2075 /*
2076 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
2077 * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
2078 * Once LAG enabled, we create multiple TISs and bind each one to
2079 * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
2080 */
2081 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
2082 (index) % (num) + 1 : 0)
2083 struct mlx5_ifc_tisc_bits {
2084 u8 strict_lag_tx_port_affinity[0x1];
2085 u8 reserved_at_1[0x3];
2086 u8 lag_tx_port_affinity[0x04];
2087 u8 reserved_at_8[0x4];
2088 u8 prio[0x4];
2089 u8 reserved_at_10[0x10];
2090 u8 reserved_at_20[0x100];
2091 u8 reserved_at_120[0x8];
2092 u8 transport_domain[0x18];
2093 u8 reserved_at_140[0x8];
2094 u8 underlay_qpn[0x18];
2095 u8 reserved_at_160[0x3a0];
2096 };
2097
2098 struct mlx5_ifc_query_tis_out_bits {
2099 u8 status[0x8];
2100 u8 reserved_at_8[0x18];
2101 u8 syndrome[0x20];
2102 u8 reserved_at_40[0x40];
2103 struct mlx5_ifc_tisc_bits tis_context;
2104 };
2105
2106 struct mlx5_ifc_query_tis_in_bits {
2107 u8 opcode[0x10];
2108 u8 reserved_at_10[0x10];
2109 u8 reserved_at_20[0x10];
2110 u8 op_mod[0x10];
2111 u8 reserved_at_40[0x8];
2112 u8 tisn[0x18];
2113 u8 reserved_at_60[0x20];
2114 };
2115
2116 /* port_select_mode definition. */
2117 enum mlx5_lag_mode_type {
2118 MLX5_LAG_MODE_TIS = 0,
2119 MLX5_LAG_MODE_HASH = 1,
2120 };
2121
2122 struct mlx5_ifc_lag_context_bits {
2123 u8 fdb_selection_mode[0x1];
2124 u8 reserved_at_1[0x14];
2125 u8 port_select_mode[0x3];
2126 u8 reserved_at_18[0x5];
2127 u8 lag_state[0x3];
2128 u8 reserved_at_20[0x14];
2129 u8 tx_remap_affinity_2[0x4];
2130 u8 reserved_at_38[0x4];
2131 u8 tx_remap_affinity_1[0x4];
2132 };
2133
2134 struct mlx5_ifc_query_lag_in_bits {
2135 u8 opcode[0x10];
2136 u8 uid[0x10];
2137 u8 reserved_at_20[0x10];
2138 u8 op_mod[0x10];
2139 u8 reserved_at_40[0x40];
2140 };
2141
2142 struct mlx5_ifc_query_lag_out_bits {
2143 u8 status[0x8];
2144 u8 reserved_at_8[0x18];
2145 u8 syndrome[0x20];
2146 struct mlx5_ifc_lag_context_bits context;
2147 };
2148
2149 struct mlx5_ifc_alloc_transport_domain_out_bits {
2150 u8 status[0x8];
2151 u8 reserved_at_8[0x18];
2152 u8 syndrome[0x20];
2153 u8 reserved_at_40[0x8];
2154 u8 transport_domain[0x18];
2155 u8 reserved_at_60[0x20];
2156 };
2157
2158 struct mlx5_ifc_alloc_transport_domain_in_bits {
2159 u8 opcode[0x10];
2160 u8 reserved_at_10[0x10];
2161 u8 reserved_at_20[0x10];
2162 u8 op_mod[0x10];
2163 u8 reserved_at_40[0x40];
2164 };
2165
2166 enum {
2167 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
2168 MLX5_WQ_TYPE_CYCLIC = 0x1,
2169 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
2170 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
2171 };
2172
2173 enum {
2174 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
2175 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2176 };
2177
2178 struct mlx5_ifc_wq_bits {
2179 u8 wq_type[0x4];
2180 u8 wq_signature[0x1];
2181 u8 end_padding_mode[0x2];
2182 u8 cd_slave[0x1];
2183 u8 reserved_at_8[0x18];
2184 u8 hds_skip_first_sge[0x1];
2185 u8 log2_hds_buf_size[0x3];
2186 u8 reserved_at_24[0x7];
2187 u8 page_offset[0x5];
2188 u8 lwm[0x10];
2189 u8 reserved_at_40[0x8];
2190 u8 pd[0x18];
2191 u8 reserved_at_60[0x8];
2192 u8 uar_page[0x18];
2193 u8 dbr_addr[0x40];
2194 u8 hw_counter[0x20];
2195 u8 sw_counter[0x20];
2196 u8 reserved_at_100[0xc];
2197 u8 log_wq_stride[0x4];
2198 u8 reserved_at_110[0x3];
2199 u8 log_wq_pg_sz[0x5];
2200 u8 reserved_at_118[0x3];
2201 u8 log_wq_sz[0x5];
2202 u8 dbr_umem_valid[0x1];
2203 u8 wq_umem_valid[0x1];
2204 u8 reserved_at_122[0x1];
2205 u8 log_hairpin_num_packets[0x5];
2206 u8 reserved_at_128[0x3];
2207 u8 log_hairpin_data_sz[0x5];
2208 u8 reserved_at_130[0x4];
2209 u8 single_wqe_log_num_of_strides[0x4];
2210 u8 two_byte_shift_en[0x1];
2211 u8 reserved_at_139[0x4];
2212 u8 single_stride_log_num_of_bytes[0x3];
2213 u8 dbr_umem_id[0x20];
2214 u8 wq_umem_id[0x20];
2215 u8 wq_umem_offset[0x40];
2216 u8 reserved_at_1c0[0x440];
2217 };
2218
2219 enum {
2220 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2221 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2222 };
2223
2224 enum {
2225 MLX5_RQC_STATE_RST = 0x0,
2226 MLX5_RQC_STATE_RDY = 0x1,
2227 MLX5_RQC_STATE_ERR = 0x3,
2228 };
2229
2230 struct mlx5_ifc_rqc_bits {
2231 u8 rlky[0x1];
2232 u8 delay_drop_en[0x1];
2233 u8 scatter_fcs[0x1];
2234 u8 vsd[0x1];
2235 u8 mem_rq_type[0x4];
2236 u8 state[0x4];
2237 u8 reserved_at_c[0x1];
2238 u8 flush_in_error_en[0x1];
2239 u8 hairpin[0x1];
2240 u8 reserved_at_f[0xB];
2241 u8 ts_format[0x02];
2242 u8 reserved_at_1c[0x4];
2243 u8 reserved_at_20[0x8];
2244 u8 user_index[0x18];
2245 u8 reserved_at_40[0x8];
2246 u8 cqn[0x18];
2247 u8 counter_set_id[0x8];
2248 u8 reserved_at_68[0x18];
2249 u8 reserved_at_80[0x8];
2250 u8 rmpn[0x18];
2251 u8 reserved_at_a0[0x8];
2252 u8 hairpin_peer_sq[0x18];
2253 u8 reserved_at_c0[0x10];
2254 u8 hairpin_peer_vhca[0x10];
2255 u8 reserved_at_e0[0xa0];
2256 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2257 };
2258
2259 struct mlx5_ifc_create_rq_out_bits {
2260 u8 status[0x8];
2261 u8 reserved_at_8[0x18];
2262 u8 syndrome[0x20];
2263 u8 reserved_at_40[0x8];
2264 u8 rqn[0x18];
2265 u8 reserved_at_60[0x20];
2266 };
2267
2268 struct mlx5_ifc_create_rq_in_bits {
2269 u8 opcode[0x10];
2270 u8 uid[0x10];
2271 u8 reserved_at_20[0x10];
2272 u8 op_mod[0x10];
2273 u8 reserved_at_40[0xc0];
2274 struct mlx5_ifc_rqc_bits ctx;
2275 };
2276
2277 struct mlx5_ifc_modify_rq_out_bits {
2278 u8 status[0x8];
2279 u8 reserved_at_8[0x18];
2280 u8 syndrome[0x20];
2281 u8 reserved_at_40[0x40];
2282 };
2283
2284 struct mlx5_ifc_query_rq_out_bits {
2285 u8 status[0x8];
2286 u8 reserved_at_8[0x18];
2287 u8 syndrome[0x20];
2288 u8 reserved_at_40[0xc0];
2289 struct mlx5_ifc_rqc_bits rq_context;
2290 };
2291
2292 struct mlx5_ifc_query_rq_in_bits {
2293 u8 opcode[0x10];
2294 u8 reserved_at_10[0x10];
2295 u8 reserved_at_20[0x10];
2296 u8 op_mod[0x10];
2297 u8 reserved_at_40[0x8];
2298 u8 rqn[0x18];
2299 u8 reserved_at_60[0x20];
2300 };
2301
2302 enum {
2303 MLX5_RMPC_STATE_RDY = 0x1,
2304 MLX5_RMPC_STATE_ERR = 0x3,
2305 };
2306
2307 struct mlx5_ifc_rmpc_bits {
2308 u8 reserved_at_0[0x8];
2309 u8 state[0x4];
2310 u8 reserved_at_c[0x14];
2311 u8 basic_cyclic_rcv_wqe[0x1];
2312 u8 reserved_at_21[0x1f];
2313 u8 reserved_at_40[0x140];
2314 struct mlx5_ifc_wq_bits wq;
2315 };
2316
2317 struct mlx5_ifc_query_rmp_out_bits {
2318 u8 status[0x8];
2319 u8 reserved_at_8[0x18];
2320 u8 syndrome[0x20];
2321 u8 reserved_at_40[0xc0];
2322 struct mlx5_ifc_rmpc_bits rmp_context;
2323 };
2324
2325 struct mlx5_ifc_query_rmp_in_bits {
2326 u8 opcode[0x10];
2327 u8 reserved_at_10[0x10];
2328 u8 reserved_at_20[0x10];
2329 u8 op_mod[0x10];
2330 u8 reserved_at_40[0x8];
2331 u8 rmpn[0x18];
2332 u8 reserved_at_60[0x20];
2333 };
2334
2335 struct mlx5_ifc_modify_rmp_out_bits {
2336 u8 status[0x8];
2337 u8 reserved_at_8[0x18];
2338 u8 syndrome[0x20];
2339 u8 reserved_at_40[0x40];
2340 };
2341
2342 struct mlx5_ifc_rmp_bitmask_bits {
2343 u8 reserved_at_0[0x20];
2344 u8 reserved_at_20[0x1f];
2345 u8 lwm[0x1];
2346 };
2347
2348 struct mlx5_ifc_modify_rmp_in_bits {
2349 u8 opcode[0x10];
2350 u8 uid[0x10];
2351 u8 reserved_at_20[0x10];
2352 u8 op_mod[0x10];
2353 u8 rmp_state[0x4];
2354 u8 reserved_at_44[0x4];
2355 u8 rmpn[0x18];
2356 u8 reserved_at_60[0x20];
2357 struct mlx5_ifc_rmp_bitmask_bits bitmask;
2358 u8 reserved_at_c0[0x40];
2359 struct mlx5_ifc_rmpc_bits ctx;
2360 };
2361
2362 struct mlx5_ifc_create_rmp_out_bits {
2363 u8 status[0x8];
2364 u8 reserved_at_8[0x18];
2365 u8 syndrome[0x20];
2366 u8 reserved_at_40[0x8];
2367 u8 rmpn[0x18];
2368 u8 reserved_at_60[0x20];
2369 };
2370
2371 struct mlx5_ifc_create_rmp_in_bits {
2372 u8 opcode[0x10];
2373 u8 uid[0x10];
2374 u8 reserved_at_20[0x10];
2375 u8 op_mod[0x10];
2376 u8 reserved_at_40[0xc0];
2377 struct mlx5_ifc_rmpc_bits ctx;
2378 };
2379
2380 struct mlx5_ifc_create_tis_out_bits {
2381 u8 status[0x8];
2382 u8 reserved_at_8[0x18];
2383 u8 syndrome[0x20];
2384 u8 reserved_at_40[0x8];
2385 u8 tisn[0x18];
2386 u8 reserved_at_60[0x20];
2387 };
2388
2389 struct mlx5_ifc_create_tis_in_bits {
2390 u8 opcode[0x10];
2391 u8 uid[0x10];
2392 u8 reserved_at_20[0x10];
2393 u8 op_mod[0x10];
2394 u8 reserved_at_40[0xc0];
2395 struct mlx5_ifc_tisc_bits ctx;
2396 };
2397
2398 enum {
2399 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2400 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2401 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2402 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2403 };
2404
2405 struct mlx5_ifc_modify_rq_in_bits {
2406 u8 opcode[0x10];
2407 u8 uid[0x10];
2408 u8 reserved_at_20[0x10];
2409 u8 op_mod[0x10];
2410 u8 rq_state[0x4];
2411 u8 reserved_at_44[0x4];
2412 u8 rqn[0x18];
2413 u8 reserved_at_60[0x20];
2414 u8 modify_bitmask[0x40];
2415 u8 reserved_at_c0[0x40];
2416 struct mlx5_ifc_rqc_bits ctx;
2417 };
2418
2419 enum {
2420 MLX5_L3_PROT_TYPE_IPV4 = 0,
2421 MLX5_L3_PROT_TYPE_IPV6 = 1,
2422 };
2423
2424 enum {
2425 MLX5_L4_PROT_TYPE_TCP = 0,
2426 MLX5_L4_PROT_TYPE_UDP = 1,
2427 };
2428
2429 enum {
2430 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2431 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2432 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2433 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2434 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2435 };
2436
2437 struct mlx5_ifc_rx_hash_field_select_bits {
2438 u8 l3_prot_type[0x1];
2439 u8 l4_prot_type[0x1];
2440 u8 selected_fields[0x1e];
2441 };
2442
2443 enum {
2444 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2445 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2446 };
2447
2448 enum {
2449 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2450 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2451 };
2452
2453 enum {
2454 MLX5_RX_HASH_FN_NONE = 0x0,
2455 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2456 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2457 };
2458
2459 enum {
2460 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2461 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2462 };
2463
2464 enum {
2465 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
2466 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
2467 };
2468
2469 struct mlx5_ifc_tirc_bits {
2470 u8 reserved_at_0[0x20];
2471 u8 disp_type[0x4];
2472 u8 reserved_at_24[0x1c];
2473 u8 reserved_at_40[0x40];
2474 u8 reserved_at_80[0x4];
2475 u8 lro_timeout_period_usecs[0x10];
2476 u8 lro_enable_mask[0x4];
2477 u8 lro_max_msg_sz[0x8];
2478 u8 reserved_at_a0[0x40];
2479 u8 reserved_at_e0[0x8];
2480 u8 inline_rqn[0x18];
2481 u8 rx_hash_symmetric[0x1];
2482 u8 reserved_at_101[0x1];
2483 u8 tunneled_offload_en[0x1];
2484 u8 reserved_at_103[0x5];
2485 u8 indirect_table[0x18];
2486 u8 rx_hash_fn[0x4];
2487 u8 reserved_at_124[0x2];
2488 u8 self_lb_block[0x2];
2489 u8 transport_domain[0x18];
2490 u8 rx_hash_toeplitz_key[10][0x20];
2491 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2492 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2493 u8 reserved_at_2c0[0x4c0];
2494 };
2495
2496 struct mlx5_ifc_create_tir_out_bits {
2497 u8 status[0x8];
2498 u8 reserved_at_8[0x18];
2499 u8 syndrome[0x20];
2500 u8 reserved_at_40[0x8];
2501 u8 tirn[0x18];
2502 u8 reserved_at_60[0x20];
2503 };
2504
2505 struct mlx5_ifc_create_tir_in_bits {
2506 u8 opcode[0x10];
2507 u8 uid[0x10];
2508 u8 reserved_at_20[0x10];
2509 u8 op_mod[0x10];
2510 u8 reserved_at_40[0xc0];
2511 struct mlx5_ifc_tirc_bits ctx;
2512 };
2513
2514 enum {
2515 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2516 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2517 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2518 /* bit 3 - tunneled_offload_en modify not supported. */
2519 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2520 };
2521
2522 struct mlx5_ifc_modify_tir_out_bits {
2523 u8 status[0x8];
2524 u8 reserved_at_8[0x18];
2525 u8 syndrome[0x20];
2526 u8 reserved_at_40[0x40];
2527 };
2528
2529 struct mlx5_ifc_modify_tir_in_bits {
2530 u8 opcode[0x10];
2531 u8 uid[0x10];
2532 u8 reserved_at_20[0x10];
2533 u8 op_mod[0x10];
2534 u8 reserved_at_40[0x8];
2535 u8 tirn[0x18];
2536 u8 reserved_at_60[0x20];
2537 u8 modify_bitmask[0x40];
2538 u8 reserved_at_c0[0x40];
2539 struct mlx5_ifc_tirc_bits ctx;
2540 };
2541
2542 enum {
2543 MLX5_INLINE_Q_TYPE_RQ = 0x0,
2544 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2545 };
2546
2547 struct mlx5_ifc_rq_num_bits {
2548 u8 reserved_at_0[0x8];
2549 u8 rq_num[0x18];
2550 };
2551
2552 struct mlx5_ifc_rqtc_bits {
2553 u8 reserved_at_0[0xa5];
2554 u8 list_q_type[0x3];
2555 u8 reserved_at_a8[0x8];
2556 u8 rqt_max_size[0x10];
2557 u8 reserved_at_c0[0x10];
2558 u8 rqt_actual_size[0x10];
2559 u8 reserved_at_e0[0x6a0];
2560 struct mlx5_ifc_rq_num_bits rq_num[];
2561 };
2562
2563 struct mlx5_ifc_create_rqt_out_bits {
2564 u8 status[0x8];
2565 u8 reserved_at_8[0x18];
2566 u8 syndrome[0x20];
2567 u8 reserved_at_40[0x8];
2568 u8 rqtn[0x18];
2569 u8 reserved_at_60[0x20];
2570 };
2571
2572 #ifdef PEDANTIC
2573 #pragma GCC diagnostic ignored "-Wpedantic"
2574 #endif
2575 struct mlx5_ifc_create_rqt_in_bits {
2576 u8 opcode[0x10];
2577 u8 uid[0x10];
2578 u8 reserved_at_20[0x10];
2579 u8 op_mod[0x10];
2580 u8 reserved_at_40[0xc0];
2581 struct mlx5_ifc_rqtc_bits rqt_context;
2582 };
2583
2584 struct mlx5_ifc_modify_rqt_in_bits {
2585 u8 opcode[0x10];
2586 u8 uid[0x10];
2587 u8 reserved_at_20[0x10];
2588 u8 op_mod[0x10];
2589 u8 reserved_at_40[0x8];
2590 u8 rqtn[0x18];
2591 u8 reserved_at_60[0x20];
2592 u8 modify_bitmask[0x40];
2593 u8 reserved_at_c0[0x40];
2594 struct mlx5_ifc_rqtc_bits rqt_context;
2595 };
2596 #ifdef PEDANTIC
2597 #pragma GCC diagnostic error "-Wpedantic"
2598 #endif
2599
2600 struct mlx5_ifc_modify_rqt_out_bits {
2601 u8 status[0x8];
2602 u8 reserved_at_8[0x18];
2603 u8 syndrome[0x20];
2604 u8 reserved_at_40[0x40];
2605 };
2606
2607 enum {
2608 MLX5_SQC_STATE_RST = 0x0,
2609 MLX5_SQC_STATE_RDY = 0x1,
2610 MLX5_SQC_STATE_ERR = 0x3,
2611 };
2612
2613 struct mlx5_ifc_sqc_bits {
2614 u8 rlky[0x1];
2615 u8 cd_master[0x1];
2616 u8 fre[0x1];
2617 u8 flush_in_error_en[0x1];
2618 u8 allow_multi_pkt_send_wqe[0x1];
2619 u8 min_wqe_inline_mode[0x3];
2620 u8 state[0x4];
2621 u8 reg_umr[0x1];
2622 u8 allow_swp[0x1];
2623 u8 hairpin[0x1];
2624 u8 non_wire[0x1];
2625 u8 static_sq_wq[0x1];
2626 u8 reserved_at_11[0x9];
2627 u8 ts_format[0x02];
2628 u8 reserved_at_1c[0x4];
2629 u8 reserved_at_20[0x8];
2630 u8 user_index[0x18];
2631 u8 reserved_at_40[0x8];
2632 u8 cqn[0x18];
2633 u8 reserved_at_60[0x8];
2634 u8 hairpin_peer_rq[0x18];
2635 u8 reserved_at_80[0x10];
2636 u8 hairpin_peer_vhca[0x10];
2637 u8 reserved_at_a0[0x50];
2638 u8 packet_pacing_rate_limit_index[0x10];
2639 u8 tis_lst_sz[0x10];
2640 u8 reserved_at_110[0x10];
2641 u8 reserved_at_120[0x40];
2642 u8 reserved_at_160[0x8];
2643 u8 tis_num_0[0x18];
2644 struct mlx5_ifc_wq_bits wq;
2645 };
2646
2647 struct mlx5_ifc_query_sq_in_bits {
2648 u8 opcode[0x10];
2649 u8 reserved_at_10[0x10];
2650 u8 reserved_at_20[0x10];
2651 u8 op_mod[0x10];
2652 u8 reserved_at_40[0x8];
2653 u8 sqn[0x18];
2654 u8 reserved_at_60[0x20];
2655 };
2656
2657 struct mlx5_ifc_modify_sq_out_bits {
2658 u8 status[0x8];
2659 u8 reserved_at_8[0x18];
2660 u8 syndrome[0x20];
2661 u8 reserved_at_40[0x40];
2662 };
2663
2664 struct mlx5_ifc_modify_sq_in_bits {
2665 u8 opcode[0x10];
2666 u8 uid[0x10];
2667 u8 reserved_at_20[0x10];
2668 u8 op_mod[0x10];
2669 u8 sq_state[0x4];
2670 u8 reserved_at_44[0x4];
2671 u8 sqn[0x18];
2672 u8 reserved_at_60[0x20];
2673 u8 modify_bitmask[0x40];
2674 u8 reserved_at_c0[0x40];
2675 struct mlx5_ifc_sqc_bits ctx;
2676 };
2677
2678 struct mlx5_ifc_create_sq_out_bits {
2679 u8 status[0x8];
2680 u8 reserved_at_8[0x18];
2681 u8 syndrome[0x20];
2682 u8 reserved_at_40[0x8];
2683 u8 sqn[0x18];
2684 u8 reserved_at_60[0x20];
2685 };
2686
2687 struct mlx5_ifc_create_sq_in_bits {
2688 u8 opcode[0x10];
2689 u8 uid[0x10];
2690 u8 reserved_at_20[0x10];
2691 u8 op_mod[0x10];
2692 u8 reserved_at_40[0xc0];
2693 struct mlx5_ifc_sqc_bits ctx;
2694 };
2695
2696 enum {
2697 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2698 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2699 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2700 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2701 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2702 };
2703
2704 struct mlx5_ifc_flow_meter_parameters_bits {
2705 u8 valid[0x1];
2706 u8 bucket_overflow[0x1];
2707 u8 start_color[0x2];
2708 u8 both_buckets_on_green[0x1];
2709 u8 meter_mode[0x2];
2710 u8 reserved_at_1[0x19];
2711 u8 reserved_at_2[0x20];
2712 u8 reserved_at_3[0x3];
2713 u8 cbs_exponent[0x5];
2714 u8 cbs_mantissa[0x8];
2715 u8 reserved_at_4[0x3];
2716 u8 cir_exponent[0x5];
2717 u8 cir_mantissa[0x8];
2718 u8 reserved_at_5[0x20];
2719 u8 reserved_at_6[0x3];
2720 u8 ebs_exponent[0x5];
2721 u8 ebs_mantissa[0x8];
2722 u8 reserved_at_7[0x3];
2723 u8 eir_exponent[0x5];
2724 u8 eir_mantissa[0x8];
2725 u8 reserved_at_8[0x60];
2726 };
2727 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2728 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2729
2730 enum {
2731 MLX5_METER_MODE_IP_LEN = 0x0,
2732 MLX5_METER_MODE_L2_LEN = 0x1,
2733 MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2734 MLX5_METER_MODE_PKT = 0x3,
2735 };
2736
2737 enum {
2738 MLX5_CQE_SIZE_64B = 0x0,
2739 MLX5_CQE_SIZE_128B = 0x1,
2740 };
2741
2742 struct mlx5_ifc_cqc_bits {
2743 u8 status[0x4];
2744 u8 as_notify[0x1];
2745 u8 initiator_src_dct[0x1];
2746 u8 dbr_umem_valid[0x1];
2747 u8 reserved_at_7[0x1];
2748 u8 cqe_sz[0x3];
2749 u8 cc[0x1];
2750 u8 reserved_at_c[0x1];
2751 u8 scqe_break_moderation_en[0x1];
2752 u8 oi[0x1];
2753 u8 cq_period_mode[0x2];
2754 u8 cqe_comp_en[0x1];
2755 u8 mini_cqe_res_format[0x2];
2756 u8 st[0x4];
2757 u8 reserved_at_18[0x1];
2758 u8 cqe_comp_layout[0x7];
2759 u8 dbr_umem_id[0x20];
2760 u8 reserved_at_40[0x14];
2761 u8 page_offset[0x6];
2762 u8 reserved_at_5a[0x2];
2763 u8 mini_cqe_res_format_ext[0x2];
2764 u8 cq_timestamp_format[0x2];
2765 u8 reserved_at_60[0x3];
2766 u8 log_cq_size[0x5];
2767 u8 uar_page[0x18];
2768 u8 reserved_at_80[0x4];
2769 u8 cq_period[0xc];
2770 u8 cq_max_count[0x10];
2771 u8 reserved_at_a0[0x18];
2772 u8 c_eqn[0x8];
2773 u8 reserved_at_c0[0x3];
2774 u8 log_page_size[0x5];
2775 u8 reserved_at_c8[0x18];
2776 u8 reserved_at_e0[0x20];
2777 u8 reserved_at_100[0x8];
2778 u8 last_notified_index[0x18];
2779 u8 reserved_at_120[0x8];
2780 u8 last_solicit_index[0x18];
2781 u8 reserved_at_140[0x8];
2782 u8 consumer_counter[0x18];
2783 u8 reserved_at_160[0x8];
2784 u8 producer_counter[0x18];
2785 u8 local_partition_id[0xc];
2786 u8 process_id[0x14];
2787 u8 reserved_at_1A0[0x20];
2788 u8 dbr_addr[0x40];
2789 };
2790
2791 struct mlx5_ifc_health_buffer_bits {
2792 u8 reserved_0[0x100];
2793 u8 assert_existptr[0x20];
2794 u8 assert_callra[0x20];
2795 u8 reserved_1[0x40];
2796 u8 fw_version[0x20];
2797 u8 hw_id[0x20];
2798 u8 reserved_2[0x20];
2799 u8 irisc_index[0x8];
2800 u8 synd[0x8];
2801 u8 ext_synd[0x10];
2802 };
2803
2804 struct mlx5_ifc_initial_seg_bits {
2805 u8 fw_rev_minor[0x10];
2806 u8 fw_rev_major[0x10];
2807 u8 cmd_interface_rev[0x10];
2808 u8 fw_rev_subminor[0x10];
2809 u8 reserved_0[0x40];
2810 u8 cmdq_phy_addr_63_32[0x20];
2811 u8 cmdq_phy_addr_31_12[0x14];
2812 u8 reserved_1[0x2];
2813 u8 nic_interface[0x2];
2814 u8 log_cmdq_size[0x4];
2815 u8 log_cmdq_stride[0x4];
2816 u8 command_doorbell_vector[0x20];
2817 u8 reserved_2[0xf00];
2818 u8 initializing[0x1];
2819 u8 nic_interface_supported[0x7];
2820 u8 reserved_4[0x18];
2821 struct mlx5_ifc_health_buffer_bits health_buffer;
2822 u8 no_dram_nic_offset[0x20];
2823 u8 reserved_5[0x6de0];
2824 u8 internal_timer_h[0x20];
2825 u8 internal_timer_l[0x20];
2826 u8 reserved_6[0x20];
2827 u8 reserved_7[0x1f];
2828 u8 clear_int[0x1];
2829 u8 health_syndrome[0x8];
2830 u8 health_counter[0x18];
2831 u8 reserved_8[0x17fc0];
2832 };
2833
2834 struct mlx5_ifc_create_cq_out_bits {
2835 u8 status[0x8];
2836 u8 reserved_at_8[0x18];
2837 u8 syndrome[0x20];
2838 u8 reserved_at_40[0x8];
2839 u8 cqn[0x18];
2840 u8 reserved_at_60[0x20];
2841 };
2842
2843 struct mlx5_ifc_create_cq_in_bits {
2844 u8 opcode[0x10];
2845 u8 uid[0x10];
2846 u8 reserved_at_20[0x10];
2847 u8 op_mod[0x10];
2848 u8 reserved_at_40[0x40];
2849 struct mlx5_ifc_cqc_bits cq_context;
2850 u8 cq_umem_offset[0x40];
2851 u8 cq_umem_id[0x20];
2852 u8 cq_umem_valid[0x1];
2853 u8 reserved_at_2e1[0x1f];
2854 u8 reserved_at_300[0x580];
2855 u8 pas[];
2856 };
2857
2858 enum {
2859 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2860 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2861 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2862 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2863 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2864 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2865 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2866 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2867 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2868 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2869 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2870 };
2871
2872 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2873 u8 opcode[0x10];
2874 u8 reserved_at_10[0x20];
2875 u8 obj_type[0x10];
2876 u8 obj_id[0x20];
2877 u8 reserved_at_60[0x3];
2878 u8 log_obj_range[0x5];
2879 u8 reserved_at_58[0x18];
2880 };
2881
2882 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2883 u8 status[0x8];
2884 u8 reserved_at_8[0x18];
2885 u8 syndrome[0x20];
2886 u8 obj_id[0x20];
2887 u8 reserved_at_60[0x20];
2888 };
2889
2890 struct mlx5_ifc_virtio_q_counters_bits {
2891 u8 modify_field_select[0x40];
2892 u8 reserved_at_40[0x40];
2893 u8 received_desc[0x40];
2894 u8 completed_desc[0x40];
2895 u8 error_cqes[0x20];
2896 u8 bad_desc_errors[0x20];
2897 u8 exceed_max_chain[0x20];
2898 u8 invalid_buffer[0x20];
2899 u8 reserved_at_180[0x50];
2900 };
2901
2902 struct mlx5_ifc_geneve_tlv_option_bits {
2903 u8 modify_field_select[0x40];
2904 u8 reserved_at_40[0x18];
2905 u8 geneve_option_fte_index[0x8];
2906 u8 option_class[0x10];
2907 u8 option_type[0x8];
2908 u8 reserved_at_78[0x3];
2909 u8 option_data_length[0x5];
2910 u8 reserved_at_80[0x180];
2911 };
2912
2913 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2914 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2915 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2916 };
2917
2918 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2919 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2920 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2921 };
2922
2923 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2924 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2925 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2926 };
2927
2928 enum {
2929 MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2930 MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2931 };
2932
2933 enum {
2934 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1,
2935 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2,
2936 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2937 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4,
2938 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5,
2939 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6,
2940 };
2941
2942 struct mlx5_ifc_dek_bits {
2943 u8 modify_field_select[0x40];
2944 u8 state[0x8];
2945 u8 reserved_at_48[0xc];
2946 u8 key_size[0x4];
2947 u8 has_keytag[0x1];
2948 u8 reserved_at_59[0x3];
2949 u8 key_purpose[0x4];
2950 u8 reserved_at_60[0x8];
2951 u8 pd[0x18];
2952 u8 reserved_at_80[0x100];
2953 u8 opaque[0x40];
2954 u8 reserved_at_1c0[0x40];
2955 u8 key[0x400];
2956 u8 reserved_at_600[0x200];
2957 };
2958
2959 struct mlx5_ifc_create_dek_in_bits {
2960 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2961 struct mlx5_ifc_dek_bits dek;
2962 };
2963
2964 struct mlx5_ifc_import_kek_bits {
2965 u8 modify_field_select[0x40];
2966 u8 state[0x8];
2967 u8 reserved_at_48[0xc];
2968 u8 key_size[0x4];
2969 u8 reserved_at_58[0x1a8];
2970 u8 key[0x400];
2971 u8 reserved_at_600[0x200];
2972 };
2973
2974 struct mlx5_ifc_create_import_kek_in_bits {
2975 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2976 struct mlx5_ifc_import_kek_bits import_kek;
2977 };
2978
2979 enum {
2980 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2981 MLX5_CREDENTIAL_ROLE_USER = 0x1,
2982 };
2983
2984 struct mlx5_ifc_credential_bits {
2985 u8 modify_field_select[0x40];
2986 u8 state[0x8];
2987 u8 reserved_at_48[0x10];
2988 u8 credential_role[0x8];
2989 u8 reserved_at_60[0x1a0];
2990 u8 credential[0x180];
2991 u8 reserved_at_380[0x480];
2992 };
2993
2994 struct mlx5_ifc_create_credential_in_bits {
2995 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2996 struct mlx5_ifc_credential_bits credential;
2997 };
2998
2999 struct mlx5_ifc_crypto_login_bits {
3000 u8 modify_field_select[0x40];
3001 u8 reserved_at_40[0x48];
3002 u8 credential_pointer[0x18];
3003 u8 reserved_at_a0[0x8];
3004 u8 session_import_kek_ptr[0x18];
3005 u8 reserved_at_c0[0x140];
3006 u8 credential[0x180];
3007 u8 reserved_at_380[0x480];
3008 };
3009
3010 struct mlx5_ifc_create_crypto_login_in_bits {
3011 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3012 struct mlx5_ifc_crypto_login_bits crypto_login;
3013 };
3014
3015 enum {
3016 MLX5_VIRTQ_STATE_INIT = 0,
3017 MLX5_VIRTQ_STATE_RDY = 1,
3018 MLX5_VIRTQ_STATE_SUSPEND = 2,
3019 MLX5_VIRTQ_STATE_ERROR = 3,
3020 };
3021
3022 enum {
3023 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
3024 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
3025 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
3026 };
3027
3028 struct mlx5_ifc_virtio_q_bits {
3029 u8 virtio_q_type[0x8];
3030 u8 reserved_at_8[0x5];
3031 u8 event_mode[0x3];
3032 u8 queue_index[0x10];
3033 u8 full_emulation[0x1];
3034 u8 virtio_version_1_0[0x1];
3035 u8 reserved_at_22[0x2];
3036 u8 offload_type[0x4];
3037 u8 event_qpn_or_msix[0x18];
3038 u8 doorbell_stride_idx[0x10];
3039 u8 queue_size[0x10];
3040 u8 device_emulation_id[0x20];
3041 u8 desc_addr[0x40];
3042 u8 used_addr[0x40];
3043 u8 available_addr[0x40];
3044 u8 virtio_q_mkey[0x20];
3045 u8 reserved_at_160[0x18];
3046 u8 error_type[0x8];
3047 u8 umem_1_id[0x20];
3048 u8 umem_1_size[0x20];
3049 u8 umem_1_offset[0x40];
3050 u8 umem_2_id[0x20];
3051 u8 umem_2_size[0x20];
3052 u8 umem_2_offset[0x40];
3053 u8 umem_3_id[0x20];
3054 u8 umem_3_size[0x20];
3055 u8 umem_3_offset[0x40];
3056 u8 counter_set_id[0x20];
3057 u8 reserved_at_320[0x8];
3058 u8 pd[0x18];
3059 u8 reserved_at_340[0x2];
3060 u8 queue_period_mode[0x2];
3061 u8 queue_period_us[0xc];
3062 u8 queue_max_count[0x10];
3063 u8 reserved_at_360[0xa0];
3064 };
3065
3066 struct mlx5_ifc_virtio_net_q_bits {
3067 u8 modify_field_select[0x40];
3068 u8 reserved_at_40[0x40];
3069 u8 tso_ipv4[0x1];
3070 u8 tso_ipv6[0x1];
3071 u8 tx_csum[0x1];
3072 u8 rx_csum[0x1];
3073 u8 reserved_at_84[0x6];
3074 u8 dirty_bitmap_dump_enable[0x1];
3075 u8 vhost_log_page[0x5];
3076 u8 reserved_at_90[0xc];
3077 u8 state[0x4];
3078 u8 reserved_at_a0[0x8];
3079 u8 tisn_or_qpn[0x18];
3080 u8 dirty_bitmap_mkey[0x20];
3081 u8 dirty_bitmap_size[0x20];
3082 u8 dirty_bitmap_addr[0x40];
3083 u8 hw_available_index[0x10];
3084 u8 hw_used_index[0x10];
3085 u8 reserved_at_160[0xa0];
3086 struct mlx5_ifc_virtio_q_bits virtio_q_context;
3087 };
3088
3089 struct mlx5_ifc_create_virtq_in_bits {
3090 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3091 struct mlx5_ifc_virtio_net_q_bits virtq;
3092 };
3093
3094 struct mlx5_ifc_query_virtq_out_bits {
3095 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3096 struct mlx5_ifc_virtio_net_q_bits virtq;
3097 };
3098
3099 struct mlx5_ifc_flow_hit_aso_bits {
3100 u8 modify_field_select[0x40];
3101 u8 reserved_at_40[0x48];
3102 u8 access_pd[0x18];
3103 u8 reserved_at_a0[0x160];
3104 u8 flag[0x200];
3105 };
3106
3107 struct mlx5_ifc_create_flow_hit_aso_in_bits {
3108 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3109 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
3110 };
3111
3112 struct mlx5_ifc_flow_meter_aso_bits {
3113 u8 modify_field_select[0x40];
3114 u8 reserved_at_40[0x48];
3115 u8 access_pd[0x18];
3116 u8 reserved_at_a0[0x160];
3117 u8 parameters[0x200];
3118 };
3119
3120 struct mlx5_ifc_create_flow_meter_aso_in_bits {
3121 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3122 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
3123 };
3124
3125 struct mlx5_ifc_tcp_window_params_bits {
3126 u8 max_ack[0x20];
3127 u8 max_win[0x20];
3128 u8 reply_end[0x20];
3129 u8 sent_end[0x20];
3130 };
3131
3132 struct mlx5_ifc_conn_track_aso_bits {
3133 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
3134 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
3135 u8 last_end[0x20]; /* End of DW8. */
3136 u8 last_ack[0x20]; /* End of DW9. */
3137 u8 last_seq[0x20]; /* End of DW10. */
3138 u8 last_win[0x10];
3139 u8 reserved_at_170[0xa];
3140 u8 last_dir[0x1];
3141 u8 last_index[0x5]; /* End of DW11. */
3142 u8 reserved_at_180[0x40]; /* End of DW13. */
3143 u8 reply_direction_tcp_scale[0x4];
3144 u8 reply_direction_tcp_close_initiated[0x1];
3145 u8 reply_direction_tcp_liberal_enabled[0x1];
3146 u8 reply_direction_tcp_data_unacked[0x1];
3147 u8 reply_direction_tcp_max_ack[0x1];
3148 u8 reserved_at_1c8[0x8];
3149 u8 original_direction_tcp_scale[0x4];
3150 u8 original_direction_tcp_close_initiated[0x1];
3151 u8 original_direction_tcp_liberal_enabled[0x1];
3152 u8 original_direction_tcp_data_unacked[0x1];
3153 u8 original_direction_tcp_max_ack[0x1];
3154 u8 reserved_at_1d8[0x8]; /* End of DW14. */
3155 u8 valid[0x1];
3156 u8 state[0x3];
3157 u8 freeze_track[0x1];
3158 u8 reserved_at_1e5[0xb];
3159 u8 reserved_at_1f0[0x1];
3160 u8 connection_assured[0x1];
3161 u8 sack_permitted[0x1];
3162 u8 challenged_acked[0x1];
3163 u8 heartbeat[0x1];
3164 u8 max_ack_window[0x3];
3165 u8 reserved_at_1f8[0x1];
3166 u8 retransmission_counter[0x3];
3167 u8 retranmission_limit_exceeded[0x1];
3168 u8 retranmission_limit[0x3]; /* End of DW15. */
3169 };
3170
3171 struct mlx5_ifc_conn_track_offload_bits {
3172 u8 modify_field_select[0x40];
3173 u8 reserved_at_40[0x40];
3174 u8 reserved_at_80[0x8];
3175 u8 conn_track_aso_access_pd[0x18];
3176 u8 reserved_at_a0[0x160];
3177 struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
3178 };
3179
3180 struct mlx5_ifc_create_conn_track_aso_in_bits {
3181 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3182 struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
3183 };
3184
3185 enum mlx5_access_aso_opc_mod {
3186 ASO_OPC_MOD_IPSEC = 0x0,
3187 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
3188 ASO_OPC_MOD_POLICER = 0x2,
3189 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
3190 ASO_OPC_MOD_FLOW_HIT = 0x4,
3191 };
3192
3193 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
3194
3195 enum mlx5_aso_data_mask_mode {
3196 BITWISE_64BIT = 0x0,
3197 BYTEWISE_64BYTE = 0x1,
3198 CALCULATED_64BYTE = 0x2,
3199 };
3200
3201 #define ASO_CSEG_COND_0_OPER_OFFSET 20
3202 #define ASO_CSEG_COND_1_OPER_OFFSET 16
3203
3204 enum mlx5_aso_pre_cond_op {
3205 ASO_OP_ALWAYS_FALSE = 0x0,
3206 ASO_OP_ALWAYS_TRUE = 0x1,
3207 ASO_OP_EQUAL = 0x2,
3208 ASO_OP_NOT_EQUAL = 0x3,
3209 ASO_OP_GREATER_OR_EQUAL = 0x4,
3210 ASO_OP_LESSER_OR_EQUAL = 0x5,
3211 ASO_OP_LESSER = 0x6,
3212 ASO_OP_GREATER = 0x7,
3213 ASO_OP_CYCLIC_GREATER = 0x8,
3214 ASO_OP_CYCLIC_LESSER = 0x9,
3215 };
3216
3217 #define ASO_CSEG_COND_OPER_OFFSET 6
3218
3219 enum mlx5_aso_op {
3220 ASO_OPER_LOGICAL_AND = 0x0,
3221 ASO_OPER_LOGICAL_OR = 0x1,
3222 };
3223
3224 /* ASO WQE CTRL segment. */
3225 struct mlx5_aso_cseg {
3226 uint32_t va_h;
3227 uint32_t va_l_r;
3228 uint32_t lkey;
3229 uint32_t operand_masks;
3230 uint32_t condition_0_data;
3231 uint32_t condition_0_mask;
3232 uint32_t condition_1_data;
3233 uint32_t condition_1_mask;
3234 uint64_t bitwise_data;
3235 uint64_t data_mask;
3236 } __rte_packed;
3237
3238 /* A meter data segment - 2 per ASO WQE. */
3239 struct mlx5_aso_mtr_dseg {
3240 uint32_t v_bo_sc_bbog_mm;
3241 /*
3242 * bit 31: valid, 30: bucket overflow, 28-29: start color,
3243 * 27: both buckets on green, 24-25: meter mode.
3244 */
3245 uint32_t reserved;
3246 uint32_t cbs_cir;
3247 /*
3248 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3249 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3250 */
3251 uint32_t c_tokens;
3252 uint32_t ebs_eir;
3253 /*
3254 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3255 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3256 */
3257 uint32_t e_tokens;
3258 uint64_t timestamp;
3259 } __rte_packed;
3260
3261 #define ASO_DSEG_VALID_OFFSET 31
3262 #define ASO_DSEG_BO_OFFSET 30
3263 #define ASO_DSEG_SC_OFFSET 28
3264 #define ASO_DSEG_BBOG_OFFSET 27
3265 #define ASO_DSEG_MTR_MODE 24
3266 #define ASO_DSEG_CBS_EXP_OFFSET 24
3267 #define ASO_DSEG_CBS_MAN_OFFSET 16
3268 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3269 #define ASO_DSEG_XIR_EXP_OFFSET 8
3270 #define ASO_DSEG_EBS_EXP_OFFSET 24
3271 #define ASO_DSEG_EBS_MAN_OFFSET 16
3272 #define ASO_DSEG_EXP_MASK 0x1F
3273 #define ASO_DSEG_MAN_MASK 0xFF
3274
3275 #define MLX5_ASO_WQE_DSEG_SIZE 0x40
3276 #define MLX5_ASO_METERS_PER_WQE 2
3277 #define MLX5_ASO_MTRS_PER_POOL 128
3278
3279 /* ASO WQE data segment. */
3280 struct mlx5_aso_dseg {
3281 union {
3282 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3283 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3284 };
3285 } __rte_packed;
3286
3287 /* ASO WQE. */
3288 struct mlx5_aso_wqe {
3289 struct mlx5_wqe_cseg general_cseg;
3290 struct mlx5_aso_cseg aso_cseg;
3291 struct mlx5_aso_dseg aso_dseg;
3292 } __rte_packed;
3293
3294 enum {
3295 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3296 };
3297
3298 enum {
3299 MLX5_QP_ST_RC = 0x0,
3300 };
3301
3302 enum {
3303 MLX5_QP_PM_MIGRATED = 0x3,
3304 };
3305
3306 enum {
3307 MLX5_NON_ZERO_RQ = 0x0,
3308 MLX5_SRQ_RQ = 0x1,
3309 MLX5_CRQ_RQ = 0x2,
3310 MLX5_ZERO_LEN_RQ = 0x3,
3311 };
3312
3313 struct mlx5_ifc_ads_bits {
3314 u8 fl[0x1];
3315 u8 free_ar[0x1];
3316 u8 reserved_at_2[0xe];
3317 u8 pkey_index[0x10];
3318 u8 reserved_at_20[0x8];
3319 u8 grh[0x1];
3320 u8 mlid[0x7];
3321 u8 rlid[0x10];
3322 u8 ack_timeout[0x5];
3323 u8 reserved_at_45[0x3];
3324 u8 src_addr_index[0x8];
3325 u8 reserved_at_50[0x4];
3326 u8 stat_rate[0x4];
3327 u8 hop_limit[0x8];
3328 u8 reserved_at_60[0x4];
3329 u8 tclass[0x8];
3330 u8 flow_label[0x14];
3331 u8 rgid_rip[16][0x8];
3332 u8 reserved_at_100[0x4];
3333 u8 f_dscp[0x1];
3334 u8 f_ecn[0x1];
3335 u8 reserved_at_106[0x1];
3336 u8 f_eth_prio[0x1];
3337 u8 ecn[0x2];
3338 u8 dscp[0x6];
3339 u8 udp_sport[0x10];
3340 u8 dei_cfi[0x1];
3341 u8 eth_prio[0x3];
3342 u8 sl[0x4];
3343 u8 vhca_port_num[0x8];
3344 u8 rmac_47_32[0x10];
3345 u8 rmac_31_0[0x20];
3346 };
3347
3348 struct mlx5_ifc_qpc_bits {
3349 u8 state[0x4];
3350 u8 lag_tx_port_affinity[0x4];
3351 u8 st[0x8];
3352 u8 reserved_at_10[0x3];
3353 u8 pm_state[0x2];
3354 u8 reserved_at_15[0x1];
3355 u8 req_e2e_credit_mode[0x2];
3356 u8 offload_type[0x4];
3357 u8 end_padding_mode[0x2];
3358 u8 reserved_at_1e[0x2];
3359 u8 wq_signature[0x1];
3360 u8 block_lb_mc[0x1];
3361 u8 atomic_like_write_en[0x1];
3362 u8 latency_sensitive[0x1];
3363 u8 reserved_at_24[0x1];
3364 u8 drain_sigerr[0x1];
3365 u8 reserved_at_26[0x2];
3366 u8 pd[0x18];
3367 u8 mtu[0x3];
3368 u8 log_msg_max[0x5];
3369 u8 reserved_at_48[0x1];
3370 u8 log_rq_size[0x4];
3371 u8 log_rq_stride[0x3];
3372 u8 no_sq[0x1];
3373 u8 log_sq_size[0x4];
3374 u8 reserved_at_55[0x3];
3375 u8 ts_format[0x2];
3376 u8 reserved_at_5a[0x1];
3377 u8 rlky[0x1];
3378 u8 ulp_stateless_offload_mode[0x4];
3379 u8 counter_set_id[0x8];
3380 u8 uar_page[0x18];
3381 u8 reserved_at_80[0x8];
3382 u8 user_index[0x18];
3383 u8 reserved_at_a0[0x3];
3384 u8 log_page_size[0x5];
3385 u8 remote_qpn[0x18];
3386 struct mlx5_ifc_ads_bits primary_address_path;
3387 struct mlx5_ifc_ads_bits secondary_address_path;
3388 u8 log_ack_req_freq[0x4];
3389 u8 reserved_at_384[0x4];
3390 u8 log_sra_max[0x3];
3391 u8 reserved_at_38b[0x2];
3392 u8 retry_count[0x3];
3393 u8 rnr_retry[0x3];
3394 u8 reserved_at_393[0x1];
3395 u8 fre[0x1];
3396 u8 cur_rnr_retry[0x3];
3397 u8 cur_retry_count[0x3];
3398 u8 reserved_at_39b[0x5];
3399 u8 reserved_at_3a0[0x20];
3400 u8 reserved_at_3c0[0x8];
3401 u8 next_send_psn[0x18];
3402 u8 reserved_at_3e0[0x8];
3403 u8 cqn_snd[0x18];
3404 u8 reserved_at_400[0x8];
3405 u8 deth_sqpn[0x18];
3406 u8 reserved_at_420[0x20];
3407 u8 reserved_at_440[0x8];
3408 u8 last_acked_psn[0x18];
3409 u8 reserved_at_460[0x8];
3410 u8 ssn[0x18];
3411 u8 reserved_at_480[0x8];
3412 u8 log_rra_max[0x3];
3413 u8 reserved_at_48b[0x1];
3414 u8 atomic_mode[0x4];
3415 u8 rre[0x1];
3416 u8 rwe[0x1];
3417 u8 rae[0x1];
3418 u8 reserved_at_493[0x1];
3419 u8 page_offset[0x6];
3420 u8 reserved_at_49a[0x3];
3421 u8 cd_slave_receive[0x1];
3422 u8 cd_slave_send[0x1];
3423 u8 cd_master[0x1];
3424 u8 reserved_at_4a0[0x3];
3425 u8 min_rnr_nak[0x5];
3426 u8 next_rcv_psn[0x18];
3427 u8 reserved_at_4c0[0x8];
3428 u8 xrcd[0x18];
3429 u8 reserved_at_4e0[0x8];
3430 u8 cqn_rcv[0x18];
3431 u8 dbr_addr[0x40];
3432 u8 q_key[0x20];
3433 u8 reserved_at_560[0x5];
3434 u8 rq_type[0x3];
3435 u8 srqn_rmpn_xrqn[0x18];
3436 u8 reserved_at_580[0x8];
3437 u8 rmsn[0x18];
3438 u8 hw_sq_wqebb_counter[0x10];
3439 u8 sw_sq_wqebb_counter[0x10];
3440 u8 hw_rq_counter[0x20];
3441 u8 sw_rq_counter[0x20];
3442 u8 reserved_at_600[0x20];
3443 u8 reserved_at_620[0xf];
3444 u8 cgs[0x1];
3445 u8 cs_req[0x8];
3446 u8 cs_res[0x8];
3447 u8 dc_access_key[0x40];
3448 u8 reserved_at_680[0x3];
3449 u8 dbr_umem_valid[0x1];
3450 u8 reserved_at_684[0x9c];
3451 u8 dbr_umem_id[0x20];
3452 };
3453
3454 struct mlx5_ifc_create_qp_out_bits {
3455 u8 status[0x8];
3456 u8 reserved_at_8[0x18];
3457 u8 syndrome[0x20];
3458 u8 reserved_at_40[0x8];
3459 u8 qpn[0x18];
3460 u8 reserved_at_60[0x20];
3461 };
3462
3463 struct mlx5_ifc_qpc_extension_bits {
3464 u8 reserved_at_0[0x2];
3465 u8 mmo[0x1];
3466 u8 reserved_at_3[0x5fd];
3467 };
3468
3469 #ifdef PEDANTIC
3470 #pragma GCC diagnostic ignored "-Wpedantic"
3471 #endif
3472 struct mlx5_ifc_qpc_pas_list_bits {
3473 u8 pas[0][0x40];
3474 };
3475
3476 #ifdef PEDANTIC
3477 #pragma GCC diagnostic ignored "-Wpedantic"
3478 #endif
3479 struct mlx5_ifc_qpc_extension_and_pas_list_bits {
3480 struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
3481 u8 pas[0][0x40];
3482 };
3483
3484
3485 #ifdef PEDANTIC
3486 #pragma GCC diagnostic ignored "-Wpedantic"
3487 #endif
3488 struct mlx5_ifc_create_qp_in_bits {
3489 u8 opcode[0x10];
3490 u8 uid[0x10];
3491 u8 reserved_at_20[0x10];
3492 u8 op_mod[0x10];
3493 u8 qpc_ext[0x1];
3494 u8 reserved_at_41[0x3f];
3495 u8 opt_param_mask[0x20];
3496 u8 reserved_at_a0[0x20];
3497 struct mlx5_ifc_qpc_bits qpc;
3498 u8 wq_umem_offset[0x40];
3499 u8 wq_umem_id[0x20];
3500 u8 wq_umem_valid[0x1];
3501 u8 reserved_at_861[0x1f];
3502 union {
3503 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
3504 struct mlx5_ifc_qpc_extension_and_pas_list_bits
3505 qpc_extension_and_pas_list;
3506 };
3507 };
3508 #ifdef PEDANTIC
3509 #pragma GCC diagnostic error "-Wpedantic"
3510 #endif
3511
3512 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3513 u8 status[0x8];
3514 u8 reserved_at_8[0x18];
3515 u8 syndrome[0x20];
3516 u8 reserved_at_40[0x40];
3517 };
3518
3519 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3520 u8 opcode[0x10];
3521 u8 uid[0x10];
3522 u8 reserved_at_20[0x10];
3523 u8 op_mod[0x10];
3524 u8 reserved_at_40[0x8];
3525 u8 qpn[0x18];
3526 u8 reserved_at_60[0x20];
3527 u8 opt_param_mask[0x20];
3528 u8 reserved_at_a0[0x20];
3529 struct mlx5_ifc_qpc_bits qpc;
3530 u8 reserved_at_800[0x80];
3531 };
3532
3533 struct mlx5_ifc_sqd2rts_qp_out_bits {
3534 u8 status[0x8];
3535 u8 reserved_at_8[0x18];
3536 u8 syndrome[0x20];
3537 u8 reserved_at_40[0x40];
3538 };
3539
3540 struct mlx5_ifc_sqd2rts_qp_in_bits {
3541 u8 opcode[0x10];
3542 u8 uid[0x10];
3543 u8 reserved_at_20[0x10];
3544 u8 op_mod[0x10];
3545 u8 reserved_at_40[0x8];
3546 u8 qpn[0x18];
3547 u8 reserved_at_60[0x20];
3548 u8 opt_param_mask[0x20];
3549 u8 reserved_at_a0[0x20];
3550 struct mlx5_ifc_qpc_bits qpc;
3551 u8 reserved_at_800[0x80];
3552 };
3553
3554 struct mlx5_ifc_rts2rts_qp_out_bits {
3555 u8 status[0x8];
3556 u8 reserved_at_8[0x18];
3557 u8 syndrome[0x20];
3558 u8 reserved_at_40[0x40];
3559 };
3560
3561 struct mlx5_ifc_rts2rts_qp_in_bits {
3562 u8 opcode[0x10];
3563 u8 uid[0x10];
3564 u8 reserved_at_20[0x10];
3565 u8 op_mod[0x10];
3566 u8 reserved_at_40[0x8];
3567 u8 qpn[0x18];
3568 u8 reserved_at_60[0x20];
3569 u8 opt_param_mask[0x20];
3570 u8 reserved_at_a0[0x20];
3571 struct mlx5_ifc_qpc_bits qpc;
3572 u8 reserved_at_800[0x80];
3573 };
3574
3575 struct mlx5_ifc_rtr2rts_qp_out_bits {
3576 u8 status[0x8];
3577 u8 reserved_at_8[0x18];
3578 u8 syndrome[0x20];
3579 u8 reserved_at_40[0x40];
3580 };
3581
3582 struct mlx5_ifc_rtr2rts_qp_in_bits {
3583 u8 opcode[0x10];
3584 u8 uid[0x10];
3585 u8 reserved_at_20[0x10];
3586 u8 op_mod[0x10];
3587 u8 reserved_at_40[0x8];
3588 u8 qpn[0x18];
3589 u8 reserved_at_60[0x20];
3590 u8 opt_param_mask[0x20];
3591 u8 reserved_at_a0[0x20];
3592 struct mlx5_ifc_qpc_bits qpc;
3593 u8 reserved_at_800[0x80];
3594 };
3595
3596 struct mlx5_ifc_rst2init_qp_out_bits {
3597 u8 status[0x8];
3598 u8 reserved_at_8[0x18];
3599 u8 syndrome[0x20];
3600 u8 reserved_at_40[0x40];
3601 };
3602
3603 struct mlx5_ifc_rst2init_qp_in_bits {
3604 u8 opcode[0x10];
3605 u8 uid[0x10];
3606 u8 reserved_at_20[0x10];
3607 u8 op_mod[0x10];
3608 u8 reserved_at_40[0x8];
3609 u8 qpn[0x18];
3610 u8 reserved_at_60[0x20];
3611 u8 opt_param_mask[0x20];
3612 u8 reserved_at_a0[0x20];
3613 struct mlx5_ifc_qpc_bits qpc;
3614 u8 reserved_at_800[0x80];
3615 };
3616
3617 struct mlx5_ifc_init2rtr_qp_out_bits {
3618 u8 status[0x8];
3619 u8 reserved_at_8[0x18];
3620 u8 syndrome[0x20];
3621 u8 reserved_at_40[0x40];
3622 };
3623
3624 struct mlx5_ifc_init2rtr_qp_in_bits {
3625 u8 opcode[0x10];
3626 u8 uid[0x10];
3627 u8 reserved_at_20[0x10];
3628 u8 op_mod[0x10];
3629 u8 reserved_at_40[0x8];
3630 u8 qpn[0x18];
3631 u8 reserved_at_60[0x20];
3632 u8 opt_param_mask[0x20];
3633 u8 reserved_at_a0[0x20];
3634 struct mlx5_ifc_qpc_bits qpc;
3635 u8 reserved_at_800[0x80];
3636 };
3637
3638 struct mlx5_ifc_init2init_qp_out_bits {
3639 u8 status[0x8];
3640 u8 reserved_at_8[0x18];
3641 u8 syndrome[0x20];
3642 u8 reserved_at_40[0x40];
3643 };
3644
3645 struct mlx5_ifc_init2init_qp_in_bits {
3646 u8 opcode[0x10];
3647 u8 uid[0x10];
3648 u8 reserved_at_20[0x10];
3649 u8 op_mod[0x10];
3650 u8 reserved_at_40[0x8];
3651 u8 qpn[0x18];
3652 u8 reserved_at_60[0x20];
3653 u8 opt_param_mask[0x20];
3654 u8 reserved_at_a0[0x20];
3655 struct mlx5_ifc_qpc_bits qpc;
3656 u8 reserved_at_800[0x80];
3657 };
3658
3659 struct mlx5_ifc_dealloc_pd_out_bits {
3660 u8 status[0x8];
3661 u8 reserved_0[0x18];
3662 u8 syndrome[0x20];
3663 u8 reserved_1[0x40];
3664 };
3665
3666 struct mlx5_ifc_dealloc_pd_in_bits {
3667 u8 opcode[0x10];
3668 u8 reserved_0[0x10];
3669 u8 reserved_1[0x10];
3670 u8 op_mod[0x10];
3671 u8 reserved_2[0x8];
3672 u8 pd[0x18];
3673 u8 reserved_3[0x20];
3674 };
3675
3676 struct mlx5_ifc_alloc_pd_out_bits {
3677 u8 status[0x8];
3678 u8 reserved_0[0x18];
3679 u8 syndrome[0x20];
3680 u8 reserved_1[0x8];
3681 u8 pd[0x18];
3682 u8 reserved_2[0x20];
3683 };
3684
3685 struct mlx5_ifc_alloc_pd_in_bits {
3686 u8 opcode[0x10];
3687 u8 reserved_0[0x10];
3688 u8 reserved_1[0x10];
3689 u8 op_mod[0x10];
3690 u8 reserved_2[0x40];
3691 };
3692
3693 #ifdef PEDANTIC
3694 #pragma GCC diagnostic ignored "-Wpedantic"
3695 #endif
3696 struct mlx5_ifc_query_qp_out_bits {
3697 u8 status[0x8];
3698 u8 reserved_at_8[0x18];
3699 u8 syndrome[0x20];
3700 u8 reserved_at_40[0x40];
3701 u8 opt_param_mask[0x20];
3702 u8 reserved_at_a0[0x20];
3703 struct mlx5_ifc_qpc_bits qpc;
3704 u8 reserved_at_800[0x80];
3705 u8 pas[0][0x40];
3706 };
3707 #ifdef PEDANTIC
3708 #pragma GCC diagnostic error "-Wpedantic"
3709 #endif
3710
3711 struct mlx5_ifc_query_qp_in_bits {
3712 u8 opcode[0x10];
3713 u8 reserved_at_10[0x10];
3714 u8 reserved_at_20[0x10];
3715 u8 op_mod[0x10];
3716 u8 reserved_at_40[0x8];
3717 u8 qpn[0x18];
3718 u8 reserved_at_60[0x20];
3719 };
3720
3721 enum {
3722 MLX5_DATA_RATE = 0x0,
3723 MLX5_WQE_RATE = 0x1,
3724 };
3725
3726 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3727 u8 rate_limit[0x20];
3728 u8 burst_upper_bound[0x20];
3729 u8 reserved_at_40[0xC];
3730 u8 rate_mode[0x4];
3731 u8 typical_packet_size[0x10];
3732 u8 reserved_at_60[0x120];
3733 };
3734
3735 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3736
3737 #ifdef PEDANTIC
3738 #pragma GCC diagnostic ignored "-Wpedantic"
3739 #endif
3740 struct mlx5_ifc_access_register_out_bits {
3741 u8 status[0x8];
3742 u8 reserved_at_8[0x18];
3743 u8 syndrome[0x20];
3744 u8 reserved_at_40[0x40];
3745 u8 register_data[0][0x20];
3746 };
3747
3748 struct mlx5_ifc_access_register_in_bits {
3749 u8 opcode[0x10];
3750 u8 reserved_at_10[0x10];
3751 u8 reserved_at_20[0x10];
3752 u8 op_mod[0x10];
3753 u8 reserved_at_40[0x10];
3754 u8 register_id[0x10];
3755 u8 argument[0x20];
3756 u8 register_data[0][0x20];
3757 };
3758 #ifdef PEDANTIC
3759 #pragma GCC diagnostic error "-Wpedantic"
3760 #endif
3761
3762 enum {
3763 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
3764 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
3765 };
3766
3767 enum {
3768 MLX5_REGISTER_ID_MTUTC = 0x9055,
3769 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3770 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3771 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3772 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3773 };
3774
3775 struct mlx5_ifc_register_mtutc_bits {
3776 u8 time_stamp_mode[0x2];
3777 u8 time_stamp_state[0x2];
3778 u8 reserved_at_4[0x18];
3779 u8 operation[0x4];
3780 u8 freq_adjustment[0x20];
3781 u8 reserved_at_40[0x40];
3782 u8 utc_sec[0x20];
3783 u8 utc_nsec[0x20];
3784 u8 time_adjustment[0x20];
3785 };
3786
3787 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3788 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3789
3790 struct mlx5_ifc_crypto_operational_register_bits {
3791 u8 wrapped_crypto_operational[0x1];
3792 u8 reserved_at_1[0x1b];
3793 u8 kek_size[0x4];
3794 u8 reserved_at_20[0x20];
3795 u8 credential[0x140];
3796 u8 kek[0x100];
3797 u8 reserved_at_280[0x180];
3798 };
3799
3800 struct mlx5_ifc_crypto_commissioning_register_bits {
3801 u8 token[0x1]; /* TODO: add size after PRM update */
3802 };
3803
3804 struct mlx5_ifc_import_kek_handle_register_bits {
3805 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3806 struct mlx5_ifc_import_kek_bits import_kek_object;
3807 u8 reserved_at_200[0x4];
3808 u8 write_operation[0x4];
3809 u8 import_kek_id[0x18];
3810 u8 reserved_at_220[0xe0];
3811 };
3812
3813 struct mlx5_ifc_credential_handle_register_bits {
3814 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3815 struct mlx5_ifc_credential_bits credential_object;
3816 u8 reserved_at_200[0x4];
3817 u8 write_operation[0x4];
3818 u8 credential_id[0x18];
3819 u8 reserved_at_220[0xe0];
3820 };
3821
3822 enum {
3823 MLX5_REGISTER_ADD_OPERATION = 0x1,
3824 MLX5_REGISTER_DELETE_OPERATION = 0x2,
3825 };
3826
3827 struct mlx5_ifc_parse_graph_arc_bits {
3828 u8 start_inner_tunnel[0x1];
3829 u8 reserved_at_1[0x7];
3830 u8 arc_parse_graph_node[0x8];
3831 u8 compare_condition_value[0x10];
3832 u8 parse_graph_node_handle[0x20];
3833 u8 reserved_at_40[0x40];
3834 };
3835
3836 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3837 u8 flow_match_sample_en[0x1];
3838 u8 reserved_at_1[0x3];
3839 u8 flow_match_sample_offset_mode[0x4];
3840 u8 reserved_at_5[0x8];
3841 u8 flow_match_sample_field_offset[0x10];
3842 u8 reserved_at_32[0x4];
3843 u8 flow_match_sample_field_offset_shift[0x4];
3844 u8 flow_match_sample_field_base_offset[0x8];
3845 u8 reserved_at_48[0xd];
3846 u8 flow_match_sample_tunnel_mode[0x3];
3847 u8 flow_match_sample_field_offset_mask[0x20];
3848 u8 flow_match_sample_field_id[0x20];
3849 };
3850
3851 struct mlx5_ifc_parse_graph_flex_bits {
3852 u8 modify_field_select[0x40];
3853 u8 reserved_at_64[0x20];
3854 u8 header_length_base_value[0x10];
3855 u8 reserved_at_112[0x4];
3856 u8 header_length_field_shift[0x4];
3857 u8 reserved_at_120[0x4];
3858 u8 header_length_mode[0x4];
3859 u8 header_length_field_offset[0x10];
3860 u8 next_header_field_offset[0x10];
3861 u8 reserved_at_160[0x1b];
3862 u8 next_header_field_size[0x5];
3863 u8 header_length_field_mask[0x20];
3864 u8 reserved_at_224[0x20];
3865 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3866 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3867 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3868 };
3869
3870 struct mlx5_ifc_create_flex_parser_in_bits {
3871 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3872 struct mlx5_ifc_parse_graph_flex_bits flex;
3873 };
3874
3875 struct mlx5_ifc_create_flex_parser_out_bits {
3876 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3877 struct mlx5_ifc_parse_graph_flex_bits flex;
3878 };
3879
3880 struct mlx5_ifc_parse_graph_flex_out_bits {
3881 u8 status[0x8];
3882 u8 reserved_at_8[0x18];
3883 u8 syndrome[0x20];
3884 u8 reserved_at_40[0x40];
3885 struct mlx5_ifc_parse_graph_flex_bits capability;
3886 };
3887
3888 struct regexp_params_field_select_bits {
3889 u8 reserved_at_0[0x1d];
3890 u8 rof_mkey[0x1];
3891 u8 stop_engine[0x1];
3892 u8 reserved_at_1f[0x1];
3893 };
3894
3895 struct mlx5_ifc_regexp_params_bits {
3896 u8 reserved_at_0[0x1f];
3897 u8 stop_engine[0x1];
3898 u8 reserved_at_20[0x60];
3899 u8 rof_mkey[0x20];
3900 u8 rof_size[0x20];
3901 u8 rof_mkey_va[0x40];
3902 u8 reserved_at_100[0x80];
3903 };
3904
3905 struct mlx5_ifc_set_regexp_params_in_bits {
3906 u8 opcode[0x10];
3907 u8 uid[0x10];
3908 u8 reserved_at_20[0x10];
3909 u8 op_mod[0x10];
3910 u8 reserved_at_40[0x18];
3911 u8 engine_id[0x8];
3912 struct regexp_params_field_select_bits field_select;
3913 struct mlx5_ifc_regexp_params_bits regexp_params;
3914 };
3915
3916 struct mlx5_ifc_set_regexp_params_out_bits {
3917 u8 status[0x8];
3918 u8 reserved_at_8[0x18];
3919 u8 syndrome[0x20];
3920 u8 reserved_at_18[0x40];
3921 };
3922
3923 struct mlx5_ifc_query_regexp_params_in_bits {
3924 u8 opcode[0x10];
3925 u8 uid[0x10];
3926 u8 reserved_at_20[0x10];
3927 u8 op_mod[0x10];
3928 u8 reserved_at_40[0x18];
3929 u8 engine_id[0x8];
3930 u8 reserved[0x20];
3931 };
3932
3933 struct mlx5_ifc_query_regexp_params_out_bits {
3934 u8 status[0x8];
3935 u8 reserved_at_8[0x18];
3936 u8 syndrome[0x20];
3937 u8 reserved[0x40];
3938 struct mlx5_ifc_regexp_params_bits regexp_params;
3939 };
3940
3941 struct mlx5_ifc_set_regexp_register_in_bits {
3942 u8 opcode[0x10];
3943 u8 uid[0x10];
3944 u8 reserved_at_20[0x10];
3945 u8 op_mod[0x10];
3946 u8 reserved_at_40[0x18];
3947 u8 engine_id[0x8];
3948 u8 register_address[0x20];
3949 u8 register_data[0x20];
3950 u8 reserved[0x60];
3951 };
3952
3953 struct mlx5_ifc_set_regexp_register_out_bits {
3954 u8 status[0x8];
3955 u8 reserved_at_8[0x18];
3956 u8 syndrome[0x20];
3957 u8 reserved[0x40];
3958 };
3959
3960 struct mlx5_ifc_query_regexp_register_in_bits {
3961 u8 opcode[0x10];
3962 u8 uid[0x10];
3963 u8 reserved_at_20[0x10];
3964 u8 op_mod[0x10];
3965 u8 reserved_at_40[0x18];
3966 u8 engine_id[0x8];
3967 u8 register_address[0x20];
3968 };
3969
3970 struct mlx5_ifc_query_regexp_register_out_bits {
3971 u8 status[0x8];
3972 u8 reserved_at_8[0x18];
3973 u8 syndrome[0x20];
3974 u8 reserved[0x20];
3975 u8 register_data[0x20];
3976 };
3977
3978 /* Queue counters. */
3979 struct mlx5_ifc_alloc_q_counter_out_bits {
3980 u8 status[0x8];
3981 u8 reserved_at_8[0x18];
3982 u8 syndrome[0x20];
3983 u8 reserved_at_40[0x18];
3984 u8 counter_set_id[0x8];
3985 u8 reserved_at_60[0x20];
3986 };
3987
3988 struct mlx5_ifc_alloc_q_counter_in_bits {
3989 u8 opcode[0x10];
3990 u8 uid[0x10];
3991 u8 reserved_at_20[0x10];
3992 u8 op_mod[0x10];
3993 u8 reserved_at_40[0x40];
3994 };
3995
3996 struct mlx5_ifc_query_q_counter_out_bits {
3997 u8 status[0x8];
3998 u8 reserved_at_8[0x18];
3999 u8 syndrome[0x20];
4000 u8 reserved_at_40[0x40];
4001 u8 rx_write_requests[0x20];
4002 u8 reserved_at_a0[0x20];
4003 u8 rx_read_requests[0x20];
4004 u8 reserved_at_e0[0x20];
4005 u8 rx_atomic_requests[0x20];
4006 u8 reserved_at_120[0x20];
4007 u8 rx_dct_connect[0x20];
4008 u8 reserved_at_160[0x20];
4009 u8 out_of_buffer[0x20];
4010 u8 reserved_at_1a0[0x20];
4011 u8 out_of_sequence[0x20];
4012 u8 reserved_at_1e0[0x20];
4013 u8 duplicate_request[0x20];
4014 u8 reserved_at_220[0x20];
4015 u8 rnr_nak_retry_err[0x20];
4016 u8 reserved_at_260[0x20];
4017 u8 packet_seq_err[0x20];
4018 u8 reserved_at_2a0[0x20];
4019 u8 implied_nak_seq_err[0x20];
4020 u8 reserved_at_2e0[0x20];
4021 u8 local_ack_timeout_err[0x20];
4022 u8 reserved_at_320[0xa0];
4023 u8 resp_local_length_error[0x20];
4024 u8 req_local_length_error[0x20];
4025 u8 resp_local_qp_error[0x20];
4026 u8 local_operation_error[0x20];
4027 u8 resp_local_protection[0x20];
4028 u8 req_local_protection[0x20];
4029 u8 resp_cqe_error[0x20];
4030 u8 req_cqe_error[0x20];
4031 u8 req_mw_binding[0x20];
4032 u8 req_bad_response[0x20];
4033 u8 req_remote_invalid_request[0x20];
4034 u8 resp_remote_invalid_request[0x20];
4035 u8 req_remote_access_errors[0x20];
4036 u8 resp_remote_access_errors[0x20];
4037 u8 req_remote_operation_errors[0x20];
4038 u8 req_transport_retries_exceeded[0x20];
4039 u8 cq_overflow[0x20];
4040 u8 resp_cqe_flush_error[0x20];
4041 u8 req_cqe_flush_error[0x20];
4042 u8 reserved_at_620[0x1e0];
4043 };
4044
4045 struct mlx5_ifc_query_q_counter_in_bits {
4046 u8 opcode[0x10];
4047 u8 uid[0x10];
4048 u8 reserved_at_20[0x10];
4049 u8 op_mod[0x10];
4050 u8 reserved_at_40[0x80];
4051 u8 clear[0x1];
4052 u8 reserved_at_c1[0x1f];
4053 u8 reserved_at_e0[0x18];
4054 u8 counter_set_id[0x8];
4055 };
4056
4057 /* CQE format mask. */
4058 #define MLX5E_CQE_FORMAT_MASK 0xc
4059
4060 /* MPW opcode. */
4061 #define MLX5_OPC_MOD_MPW 0x01
4062
4063 /* Compressed Rx CQE structure. */
4064 struct mlx5_mini_cqe8 {
4065 union {
4066 uint32_t rx_hash_result;
4067 struct {
4068 union {
4069 uint16_t checksum;
4070 uint16_t flow_tag_high;
4071 struct {
4072 uint8_t reserved;
4073 uint8_t hdr_type;
4074 };
4075 };
4076 uint16_t stride_idx;
4077 };
4078 struct {
4079 uint16_t wqe_counter;
4080 uint8_t s_wqe_opcode;
4081 uint8_t reserved;
4082 } s_wqe_info;
4083 };
4084 union {
4085 uint32_t byte_cnt_flow;
4086 uint32_t byte_cnt;
4087 };
4088 };
4089
4090 /* Mini CQE responder format. */
4091 enum {
4092 MLX5_CQE_RESP_FORMAT_HASH = 0x0,
4093 MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
4094 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
4095 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
4096 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
4097 };
4098
4099 /* srTCM PRM flow meter parameters. */
4100 enum {
4101 MLX5_FLOW_COLOR_RED = 0,
4102 MLX5_FLOW_COLOR_YELLOW,
4103 MLX5_FLOW_COLOR_GREEN,
4104 MLX5_FLOW_COLOR_UNDEFINED,
4105 };
4106
4107 /* Maximum value of srTCM & trTCM metering parameters. */
4108 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
4109 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
4110
4111 /* The bits meter color use. */
4112 #define MLX5_MTR_COLOR_BITS 8
4113
4114 /* The bit size of one register. */
4115 #define MLX5_REG_BITS 32
4116
4117 /* Idle bits for non-color usage in color register. */
4118 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
4119
4120 /* Length mode of dynamic flex parser graph node. */
4121 enum mlx5_parse_graph_node_len_mode {
4122 MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
4123 MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
4124 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
4125 };
4126
4127 /* Offset mode of the samples of flex parser. */
4128 enum mlx5_parse_graph_flow_match_sample_offset_mode {
4129 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
4130 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
4131 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
4132 };
4133
4134 enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
4135 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
4136 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
4137 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
4138 };
4139
4140 /* Node index for an input / output arc of the flex parser graph. */
4141 enum mlx5_parse_graph_arc_node_index {
4142 MLX5_GRAPH_ARC_NODE_NULL = 0x0,
4143 MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
4144 MLX5_GRAPH_ARC_NODE_MAC = 0x2,
4145 MLX5_GRAPH_ARC_NODE_IP = 0x3,
4146 MLX5_GRAPH_ARC_NODE_GRE = 0x4,
4147 MLX5_GRAPH_ARC_NODE_UDP = 0x5,
4148 MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
4149 MLX5_GRAPH_ARC_NODE_TCP = 0x7,
4150 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
4151 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
4152 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
4153 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
4154 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
4155 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
4156 };
4157
4158 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
4159 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
4160 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
4161
4162 /**
4163 * Convert a user mark to flow mark.
4164 *
4165 * @param val
4166 * Mark value to convert.
4167 *
4168 * @return
4169 * Converted mark value.
4170 */
4171 static inline uint32_t
mlx5_flow_mark_set(uint32_t val)4172 mlx5_flow_mark_set(uint32_t val)
4173 {
4174 uint32_t ret;
4175
4176 /*
4177 * Add one to the user value to differentiate un-marked flows from
4178 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
4179 * remains untouched.
4180 */
4181 if (val != MLX5_FLOW_MARK_DEFAULT)
4182 ++val;
4183 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4184 /*
4185 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
4186 * word, byte-swapped by the kernel on little-endian systems. In this
4187 * case, left-shifting the resulting big-endian value ensures the
4188 * least significant 24 bits are retained when converting it back.
4189 */
4190 ret = rte_cpu_to_be_32(val) >> 8;
4191 #else
4192 ret = val;
4193 #endif
4194 return ret;
4195 }
4196
4197 /**
4198 * Convert a mark to user mark.
4199 *
4200 * @param val
4201 * Mark value to convert.
4202 *
4203 * @return
4204 * Converted mark value.
4205 */
4206 static inline uint32_t
mlx5_flow_mark_get(uint32_t val)4207 mlx5_flow_mark_get(uint32_t val)
4208 {
4209 /*
4210 * Subtract one from the retrieved value. It was added by
4211 * mlx5_flow_mark_set() to distinguish unmarked flows.
4212 */
4213 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4214 return (val >> 8) - 1;
4215 #else
4216 return val - 1;
4217 #endif
4218 }
4219
4220 /**
4221 * Convert a timestamp format to configure settings in the queue context.
4222 *
4223 * @param val
4224 * timestamp format supported by the queue.
4225 *
4226 * @return
4227 * Converted timestamp format settings.
4228 */
4229 static inline uint32_t
mlx5_ts_format_conv(uint32_t ts_format)4230 mlx5_ts_format_conv(uint32_t ts_format)
4231 {
4232 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
4233 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
4234 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
4235 }
4236
4237 #endif /* RTE_PMD_MLX5_PRM_H_ */
4238