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/dpdk/lib/pipeline/
H A Drte_swx_pipeline_internal.h655 struct instruction *ip;
669 struct instruction { struct
935 struct instruction *ip;
936 struct instruction *ret;
1534 struct instruction *ip = t->ip; in instr_rx_exec()
2096 const struct instruction *ip) in __instr_extern_obj_exec()
2139 const struct instruction *ip) in __instr_mov_exec()
2302 const struct instruction *ip) in __instr_alu_add_mh_exec()
2312 const struct instruction *ip) in __instr_alu_add_hm_exec()
2322 const struct instruction *ip) in __instr_alu_add_hh_exec()
[all …]
H A Drte_swx_pipeline.c1551 struct instruction *instr, in instr_rx_translate()
1855 struct instruction *instr, in instr_hdr_emit_translate()
2767 struct instruction *instr, in instr_alu_add_translate()
2823 struct instruction *instr, in instr_alu_sub_translate()
2961 struct instruction *instr, in instr_alu_shl_translate()
3017 struct instruction *instr, in instr_alu_shr_translate()
3073 struct instruction *instr, in instr_alu_and_translate()
3185 struct instruction *instr, in instr_alu_xor_translate()
4926 struct instruction *instr, in instr_jmp_hit_translate()
5070 struct instruction *instr, in instr_jmp_neq_translate()
[all …]
/dpdk/lib/acl/
H A Dmeson.build18 # a. we have AVX supported in minimum instruction set baseline
19 # b. it's not minimum instruction set, but supported by compiler
42 # a. we have AVX512 supported in minimum instruction set
44 # b. it's not minimum instruction set, but supported by
/dpdk/drivers/net/hns3/
H A Dmeson.build42 # a. support SVE in minimum instruction set baseline
43 # b. it's not minimum instruction set, but compiler support
/dpdk/drivers/net/bnxt/
H A Dmeson.build52 # a. we have AVX supported in minimum instruction set baseline
53 # b. it's not minimum instruction set, but supported by compiler
/dpdk/drivers/net/iavf/
H A Dmeson.build29 # a. we have AVX supported in minimum instruction set baseline
30 # b. it's not minimum instruction set, but supported by compiler
/dpdk/drivers/net/ice/
H A Dmeson.build28 # a. we have AVX supported in minimum instruction set baseline
29 # b. it's not minimum instruction set, but supported by compiler
/dpdk/drivers/net/i40e/
H A Dmeson.build35 # a. we have AVX supported in minimum instruction set baseline
36 # b. it's not minimum instruction set, but supported by compiler
/dpdk/lib/fib/
H A Dmeson.build19 # a. we have AVX512F supported in minimum instruction set baseline
20 # b. it's not minimum instruction set, but supported by compiler
/dpdk/examples/pipeline/examples/
H A Dvarbit.spec8 ; field; this read is done with the "lookahead" instruction, which does not advance the extract
10 ; current packet, the IPv4 header is extracted by using the two-argument "extract" instruction. Then
H A Dlearner.spec86 // packet meta-data fields have to be written before the "learn" instruction is invoked.
/dpdk/doc/guides/mempool/
H A Dcnxk.rst30 - Batch dequeue of up to 512 pointers with single instruction.
31 - Batch enqueue of up to 15 pointers with single instruction.
/dpdk/doc/guides/linux_gsg/
H A Dbuild_dpdk.rst115 The instruction set will be set automatically by default according to these rules:
124 To override what instruction set will be used, set the ``cpu_instruction_set``
125 parameter to the instruction set of your choice (such as ``corei7``, ``power8``, etc.).
127 ``cpu_instruction_set`` is not used in Arm builds, as setting the instruction set
/dpdk/app/
H A Dmeson.build37 # instruction-set optimized versions of code
/dpdk/doc/guides/prog_guide/
H A Dwriting_efficient_code.rst177 On x86, atomic operations imply a lock prefix before the instruction,
178 causing the processor's LOCK# signal to be asserted during execution of the following instruction.
244 This avoids the cost of a call instruction (and the associated context saving).
266 …er version does not support the specific feature set (for example, the Intel® AVX instruction set),
275 These defines correspond to the instruction sets that the target CPU should be able to support.
H A Dtimer_lib.rst51 a Compare And Swap instruction should be used to guarantee that the status (state+owner) is modifie…
60 …done on 32-bit platforms without using either a compare-and-swap (CAS) instruction or using a lock,
H A Dpower_man.rst225 * On Linux* x86_64, `rte_power_monitor()` requires WAITPKG instruction set being
227 RTM instruction sets being supported by the CPU. RTM instruction set may also
H A Dbuild-sdk-meson.rst124 cpu_instruction_set=generic uses an instruction set that works on
130 cpu_instruction_set is not used in Arm builds, as setting the instruction set
H A Dstack_lib.rst74 compare-and-swap instruction to atomically update both the stack top pointer
/dpdk/
H A Dmeson_options.txt6 …description: 'Set the target machine ISA (instruction set architecture). Will be set according to …
/dpdk/doc/guides/rel_notes/
H A Drelease_20_08.rst18 * **rte_*mb APIs are updated to use the DMB instruction for ARMv8.**
21 atomicity. This allows for using the DMB instruction instead of DSB for IO
23 instruction to reflect this.
H A Drelease_21_02.rst34 * Power saving based on UMWAIT instruction (x86 only)
35 * Power saving based on ``rte_pause()`` (generic) or TPAUSE instruction (x86 only)
/dpdk/lib/
H A Dmeson.build122 # instruction-set optimized versions of code
/dpdk/doc/guides/sample_app_ug/
H A Dvm_power_management.rst636 possible values are ``instruction`` and ``policy`` and the expected name-value
677 {"instruction": {
900 For the ``POWER`` instruction only.
919 For the ``POWER`` instruction only.
/dpdk/doc/guides/platform/
H A Dcnxk.rst451 CPT instruction requests 0
452 CPT instruction latency 0

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