1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
3 */
4
5 #ifndef _ICE_RXTX_H_
6 #define _ICE_RXTX_H_
7
8 #include "ice_ethdev.h"
9
10 #define ICE_ALIGN_RING_DESC 32
11 #define ICE_MIN_RING_DESC 64
12 #define ICE_MAX_RING_DESC 4096
13 #define ICE_DMA_MEM_ALIGN 4096
14 #define ICE_RING_BASE_ALIGN 128
15
16 #define ICE_RX_MAX_BURST 32
17 #define ICE_TX_MAX_BURST 32
18
19 #define ICE_CHK_Q_ENA_COUNT 100
20 #define ICE_CHK_Q_ENA_INTERVAL_US 100
21
22 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
23 #define ice_rx_flex_desc ice_16b_rx_flex_desc
24 #else
25 #define ice_rx_flex_desc ice_32b_rx_flex_desc
26 #endif
27
28 #define ICE_SUPPORT_CHAIN_NUM 5
29
30 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
31
32 #define ICE_VPMD_RX_BURST 32
33 #define ICE_VPMD_TX_BURST 32
34 #define ICE_RXQ_REARM_THRESH 64
35 #define ICE_MAX_RX_BURST ICE_RXQ_REARM_THRESH
36 #define ICE_TX_MAX_FREE_BUF_SZ 64
37 #define ICE_DESCS_PER_LOOP 4
38
39 #define ICE_FDIR_PKT_LEN 512
40
41 #define ICE_RXDID_COMMS_OVS 22
42
43 extern uint64_t ice_timestamp_dynflag;
44 extern int ice_timestamp_dynfield_offset;
45
46 typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq);
47 typedef void (*ice_tx_release_mbufs_t)(struct ice_tx_queue *txq);
48 typedef void (*ice_rxd_to_pkt_fields_t)(struct ice_rx_queue *rxq,
49 struct rte_mbuf *mb,
50 volatile union ice_rx_flex_desc *rxdp);
51
52 struct ice_rx_entry {
53 struct rte_mbuf *mbuf;
54 };
55
56 struct ice_rx_queue {
57 struct rte_mempool *mp; /* mbuf pool to populate RX ring */
58 volatile union ice_rx_flex_desc *rx_ring;/* RX ring virtual address */
59 rte_iova_t rx_ring_dma; /* RX ring DMA address */
60 struct ice_rx_entry *sw_ring; /* address of RX soft ring */
61 uint16_t nb_rx_desc; /* number of RX descriptors */
62 uint16_t rx_free_thresh; /* max free RX desc to hold */
63 uint16_t rx_tail; /* current value of tail */
64 uint16_t nb_rx_hold; /* number of held free RX desc */
65 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
66 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
67 uint16_t rx_nb_avail; /**< number of staged packets ready */
68 uint16_t rx_next_avail; /**< index of next staged packets */
69 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
70 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
71 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];
72
73 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
74 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
75 uint64_t mbuf_initializer; /**< value to init mbufs */
76
77 uint16_t port_id; /* device port ID */
78 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
79 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */
80 uint16_t queue_id; /* RX queue index */
81 uint16_t reg_idx; /* RX queue register index */
82 uint8_t drop_en; /* if not 0, set register bit */
83 volatile uint8_t *qrx_tail; /* register address of tail */
84 struct ice_vsi *vsi; /* the VSI this queue belongs to */
85 uint16_t rx_buf_len; /* The packet buffer size */
86 uint16_t rx_hdr_len; /* The header buffer size */
87 uint16_t max_pkt_len; /* Maximum packet length */
88 bool q_set; /* indicate if rx queue has been configured */
89 bool rx_deferred_start; /* don't start this queue in dev start */
90 uint8_t proto_xtr; /* Protocol extraction from flexible descriptor */
91 uint64_t xtr_ol_flag; /* Protocol extraction offload flag */
92 uint32_t rxdid; /* Receive Flex Descriptor profile ID */
93 ice_rx_release_mbufs_t rx_rel_mbufs;
94 uint64_t offloads;
95 uint32_t time_high;
96 uint32_t hw_register_set;
97 const struct rte_memzone *mz;
98 };
99
100 struct ice_tx_entry {
101 struct rte_mbuf *mbuf;
102 uint16_t next_id;
103 uint16_t last_id;
104 };
105
106 struct ice_vec_tx_entry {
107 struct rte_mbuf *mbuf;
108 };
109
110 struct ice_tx_queue {
111 uint16_t nb_tx_desc; /* number of TX descriptors */
112 rte_iova_t tx_ring_dma; /* TX ring DMA address */
113 volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */
114 struct ice_tx_entry *sw_ring; /* virtual address of SW ring */
115 uint16_t tx_tail; /* current value of tail register */
116 volatile uint8_t *qtx_tail; /* register address of tail */
117 uint16_t nb_tx_used; /* number of TX desc used since RS bit set */
118 /* index to last TX descriptor to have been cleaned */
119 uint16_t last_desc_cleaned;
120 /* Total number of TX descriptors ready to be allocated. */
121 uint16_t nb_tx_free;
122 /* Start freeing TX buffers if there are less free descriptors than
123 * this value.
124 */
125 uint16_t tx_free_thresh;
126 /* Number of TX descriptors to use before RS bit is set. */
127 uint16_t tx_rs_thresh;
128 uint8_t pthresh; /**< Prefetch threshold register. */
129 uint8_t hthresh; /**< Host threshold register. */
130 uint8_t wthresh; /**< Write-back threshold reg. */
131 uint16_t port_id; /* Device port identifier. */
132 uint16_t queue_id; /* TX queue index. */
133 uint32_t q_teid; /* TX schedule node id. */
134 uint16_t reg_idx;
135 uint64_t offloads;
136 struct ice_vsi *vsi; /* the VSI this queue belongs to */
137 uint16_t tx_next_dd;
138 uint16_t tx_next_rs;
139 bool tx_deferred_start; /* don't start this queue in dev start */
140 bool q_set; /* indicate if tx queue has been configured */
141 ice_tx_release_mbufs_t tx_rel_mbufs;
142 const struct rte_memzone *mz;
143 };
144
145 /* Offload features */
146 union ice_tx_offload {
147 uint64_t data;
148 struct {
149 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
150 uint64_t l3_len:9; /* L3 (IP) Header Length. */
151 uint64_t l4_len:8; /* L4 Header Length. */
152 uint64_t tso_segsz:16; /* TCP TSO segment size */
153 uint64_t outer_l2_len:8; /* outer L2 Header Length */
154 uint64_t outer_l3_len:16; /* outer L3 Header Length */
155 };
156 };
157
158 /* Rx Flex Descriptor for Comms Package Profile
159 * RxDID Profile ID 22 (swap Hash and FlowID)
160 * Flex-field 0: Flow ID lower 16-bits
161 * Flex-field 1: Flow ID upper 16-bits
162 * Flex-field 2: RSS hash lower 16-bits
163 * Flex-field 3: RSS hash upper 16-bits
164 * Flex-field 4: AUX0
165 * Flex-field 5: AUX1
166 */
167 struct ice_32b_rx_flex_desc_comms_ovs {
168 /* Qword 0 */
169 u8 rxdid;
170 u8 mir_id_umb_cast;
171 __le16 ptype_flexi_flags0;
172 __le16 pkt_len;
173 __le16 hdr_len_sph_flex_flags1;
174
175 /* Qword 1 */
176 __le16 status_error0;
177 __le16 l2tag1;
178 __le32 flow_id;
179
180 /* Qword 2 */
181 __le16 status_error1;
182 u8 flexi_flags2;
183 u8 ts_low;
184 __le16 l2tag2_1st;
185 __le16 l2tag2_2nd;
186
187 /* Qword 3 */
188 __le32 rss_hash;
189 union {
190 struct {
191 __le16 aux0;
192 __le16 aux1;
193 } flex;
194 __le32 ts_high;
195 } flex_ts;
196 };
197
198 int ice_rx_queue_setup(struct rte_eth_dev *dev,
199 uint16_t queue_idx,
200 uint16_t nb_desc,
201 unsigned int socket_id,
202 const struct rte_eth_rxconf *rx_conf,
203 struct rte_mempool *mp);
204 int ice_tx_queue_setup(struct rte_eth_dev *dev,
205 uint16_t queue_idx,
206 uint16_t nb_desc,
207 unsigned int socket_id,
208 const struct rte_eth_txconf *tx_conf);
209 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
210 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
211 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
212 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
213 int ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
214 int ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
215 int ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
216 int ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
217 void ice_rx_queue_release(void *rxq);
218 void ice_tx_queue_release(void *txq);
219 void ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
220 void ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
221 void ice_free_queues(struct rte_eth_dev *dev);
222 int ice_fdir_setup_tx_resources(struct ice_pf *pf);
223 int ice_fdir_setup_rx_resources(struct ice_pf *pf);
224 uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
225 uint16_t nb_pkts);
226 uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
227 uint16_t nb_pkts);
228 void ice_set_rx_function(struct rte_eth_dev *dev);
229 uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
230 uint16_t nb_pkts);
231 void ice_set_tx_function_flag(struct rte_eth_dev *dev,
232 struct ice_tx_queue *txq);
233 void ice_set_tx_function(struct rte_eth_dev *dev);
234 uint32_t ice_rx_queue_count(void *rx_queue);
235 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
236 struct rte_eth_rxq_info *qinfo);
237 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
238 struct rte_eth_txq_info *qinfo);
239 int ice_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
240 struct rte_eth_burst_mode *mode);
241 int ice_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
242 struct rte_eth_burst_mode *mode);
243 int ice_rx_descriptor_status(void *rx_queue, uint16_t offset);
244 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset);
245 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
246 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
247 void ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq,
248 uint32_t rxdid);
249
250 int ice_rx_vec_dev_check(struct rte_eth_dev *dev);
251 int ice_tx_vec_dev_check(struct rte_eth_dev *dev);
252 int ice_rxq_vec_setup(struct ice_rx_queue *rxq);
253 int ice_txq_vec_setup(struct ice_tx_queue *txq);
254 uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
255 uint16_t nb_pkts);
256 uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
257 uint16_t nb_pkts);
258 uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
259 uint16_t nb_pkts);
260 uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
261 uint16_t nb_pkts);
262 uint16_t ice_recv_pkts_vec_avx2_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
263 uint16_t nb_pkts);
264 uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue,
265 struct rte_mbuf **rx_pkts,
266 uint16_t nb_pkts);
267 uint16_t ice_recv_scattered_pkts_vec_avx2_offload(void *rx_queue,
268 struct rte_mbuf **rx_pkts,
269 uint16_t nb_pkts);
270 uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
271 uint16_t nb_pkts);
272 uint16_t ice_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
273 uint16_t nb_pkts);
274 uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
275 uint16_t nb_pkts);
276 uint16_t ice_recv_pkts_vec_avx512_offload(void *rx_queue,
277 struct rte_mbuf **rx_pkts,
278 uint16_t nb_pkts);
279 uint16_t ice_recv_scattered_pkts_vec_avx512(void *rx_queue,
280 struct rte_mbuf **rx_pkts,
281 uint16_t nb_pkts);
282 uint16_t ice_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
283 struct rte_mbuf **rx_pkts,
284 uint16_t nb_pkts);
285 uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
286 uint16_t nb_pkts);
287 uint16_t ice_xmit_pkts_vec_avx512_offload(void *tx_queue,
288 struct rte_mbuf **tx_pkts,
289 uint16_t nb_pkts);
290 int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc);
291 int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
292 int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
293
294 #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \
295 int i; \
296 for (i = 0; i < (ad)->pf.dev_data->nb_rx_queues; i++) { \
297 struct ice_rx_queue *rxq = (ad)->pf.dev_data->rx_queues[i]; \
298 if (!rxq) \
299 continue; \
300 rxq->fdir_enabled = on; \
301 } \
302 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
303 } while (0)
304
305 /* Enable/disable flow director parsing from Rx descriptor in data path. */
306 static inline
ice_fdir_rx_parsing_enable(struct ice_adapter * ad,bool on)307 void ice_fdir_rx_parsing_enable(struct ice_adapter *ad, bool on)
308 {
309 if (on) {
310 /* Enable flow director parsing from Rx descriptor */
311 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
312 ad->fdir_ref_cnt++;
313 } else {
314 if (ad->fdir_ref_cnt >= 1) {
315 ad->fdir_ref_cnt--;
316
317 if (ad->fdir_ref_cnt == 0)
318 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
319 }
320 }
321 }
322
323 #define ICE_TIMESYNC_REG_WRAP_GUARD_BAND 10000
324
325 /* Helper function to convert a 32b nanoseconds timestamp to 64b. */
326 static inline
ice_tstamp_convert_32b_64b(struct ice_hw * hw,struct ice_adapter * ad,uint32_t flag,uint32_t in_timestamp)327 uint64_t ice_tstamp_convert_32b_64b(struct ice_hw *hw, struct ice_adapter *ad,
328 uint32_t flag, uint32_t in_timestamp)
329 {
330 const uint64_t mask = 0xFFFFFFFF;
331 uint32_t hi, lo, lo2, delta;
332 uint64_t ns;
333
334 if (flag) {
335 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
336 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));
337
338 /*
339 * On typical system, the delta between lo and lo2 is ~1000ns,
340 * so 10000 seems a large-enough but not overly-big guard band.
341 */
342 if (lo > (UINT32_MAX - ICE_TIMESYNC_REG_WRAP_GUARD_BAND))
343 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
344 else
345 lo2 = lo;
346
347 if (lo2 < lo) {
348 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
349 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));
350 }
351
352 ad->time_hw = ((uint64_t)hi << 32) | lo;
353 }
354
355 delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
356 if (delta > (mask / 2)) {
357 delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
358 ns = ad->time_hw - delta;
359 } else {
360 ns = ad->time_hw + delta;
361 }
362
363 return ns;
364 }
365
366 #endif /* _ICE_RXTX_H_ */
367