| /dpdk/drivers/net/hns3/ |
| H A D | hns3_cmd.c | 487 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_PTP_B, 1); in hns3_parse_capability() 493 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1); in hns3_parse_capability() 495 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1); in hns3_parse_capability() 499 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1); in hns3_parse_capability() 504 hns3_set_bit(hw->capability, in hns3_parse_capability() 509 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1); in hns3_parse_capability() 517 hns3_set_bit(api_caps, HNS3_API_CAP_FLEX_RSS_TBL_B, 1); in hns3_build_api_caps() 658 hns3_set_bit(hw->capability, in hns3_firmware_compat_config() 671 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1); in hns3_firmware_compat_config() 672 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0); in hns3_firmware_compat_config() [all …]
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| H A D | hns3_flow.c | 553 hns3_set_bit(rule->input_set, INNER_VLAN_TAG1, in hns3_parse_vlan() 558 hns3_set_bit(rule->input_set, INNER_VLAN_TAG2, in hns3_parse_vlan() 594 hns3_set_bit(rule->input_set, INNER_ETH_TYPE, 1); in hns3_parse_ipv4() 612 hns3_set_bit(rule->input_set, INNER_SRC_IP, 1); in hns3_parse_ipv4() 618 hns3_set_bit(rule->input_set, INNER_DST_IP, 1); in hns3_parse_ipv4() 624 hns3_set_bit(rule->input_set, INNER_IP_TOS, 1); in hns3_parse_ipv4() 653 hns3_set_bit(rule->input_set, INNER_ETH_TYPE, 1); in hns3_parse_ipv6() 678 hns3_set_bit(rule->input_set, INNER_SRC_IP, 1); in hns3_parse_ipv6() 680 hns3_set_bit(rule->input_set, INNER_DST_IP, 1); in hns3_parse_ipv6() 716 hns3_set_bit(rule->input_set, INNER_IP_PROTO, 1); in hns3_parse_tcp() [all …]
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| H A D | hns3_fdir.c | 403 hns3_set_bit(req1->port_info, HNS3_FD_EPORT_SW_EN_B, 0); in hns3_fd_tcam_config() 441 hns3_set_bit(ad_data, HNS3_FD_AD_WR_RULE_ID_B, in hns3_fd_ad_config() 446 hns3_set_bit(ad_data, HNS3_FD_AD_QUEUE_REGION_EN_B, 1); in hns3_fd_ad_config() 453 hns3_set_bit(ad_data, HNS3_FD_AD_COUNTER_HIGH_BIT_B, 1); in hns3_fd_ad_config() 456 hns3_set_bit(ad_data, HNS3_FD_AD_QUEUE_ID_HIGH_BIT_B, 1); in hns3_fd_ad_config() 458 hns3_set_bit(ad_data, HNS3_FD_AD_DROP_B, action->drop_packet); in hns3_fd_ad_config() 460 hns3_set_bit(ad_data, HNS3_FD_AD_DIRECT_QID_B, 1); in hns3_fd_ad_config() 463 hns3_set_bit(ad_data, HNS3_FD_AD_USE_COUNTER_B, action->use_counter); in hns3_fd_ad_config() 466 hns3_set_bit(ad_data, HNS3_FD_AD_NXT_STEP_B, action->use_next_stage); in hns3_fd_ad_config() 645 hns3_set_bit(port_number, HNS3_PORT_TYPE_B, HOST_PORT); in hns3_get_port_number() [all …]
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| H A D | hns3_ethdev.c | 2856 hns3_set_bit(hw->hw_tc_map, 0, 1); in hns3_get_board_configuration() 4272 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); in hns3_cfg_mac_mode() 4273 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); in hns3_cfg_mac_mode() 4274 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); in hns3_cfg_mac_mode() 4275 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); in hns3_cfg_mac_mode() 4276 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); in hns3_cfg_mac_mode() 4277 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); in hns3_cfg_mac_mode() 4278 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); in hns3_cfg_mac_mode() 4279 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); in hns3_cfg_mac_mode() 4912 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); in hns3_set_autoneg() [all …]
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| H A D | hns3_ptp.c | 92 hns3_set_bit(req->enable, HNS3_PTP_ENABLE_B, val); in hns3_timesync_configure() 93 hns3_set_bit(req->enable, HNS3_PTP_TX_ENABLE_B, val); in hns3_timesync_configure() 94 hns3_set_bit(req->enable, HNS3_PTP_RX_ENABLE_B, val); in hns3_timesync_configure()
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| H A D | hns3_rss.c | 594 hns3_set_bit(mode, HNS3_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); in hns3_set_rss_tc_mode() 598 hns3_set_bit(mode, HNS3_RSS_TC_SIZE_MSB_S, 1); in hns3_set_rss_tc_mode()
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| H A D | hns3_dcb.c | 370 hns3_set_bit(shap_cfg_cmd->flag, HNS3_TM_RATE_VLD_B, 1); in hns3_dcb_port_shaper_cfg() 413 hns3_set_bit(shap_cfg_cmd->flag, HNS3_TM_RATE_VLD_B, 1); in hns3_dcb_pg_shapping_cfg() 549 hns3_set_bit(shap_cfg_cmd->flag, HNS3_TM_RATE_VLD_B, 1); in hns3_dcb_pri_shapping_cfg()
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| H A D | hns3_ethdev.h | 928 #define hns3_set_bit(origin, shift, val) \ macro
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| H A D | hns3_ethdev_dump.c | 336 hns3_set_bit(queue_state[i / STATE_SIZE], in get_queue_enable_state()
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| H A D | hns3_rxtx.c | 583 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0); in hns3_tqp_enable() 603 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0); in hns3_send_reset_tqp_cmd() 709 hns3_set_bit(req->fun_reset_rcb, HNS3_CFG_RESET_RCB_B, 1); in hns3_reset_rcb_cmd() 840 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0); in hns3_send_reset_queue_cmd()
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| H A D | hns3_ethdev_vf.c | 934 hns3_set_bit(hw->capability, in hns3vf_update_caps()
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