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Searched refs:encp (Results 1 – 25 of 46) sorted by relevance

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/dpdk/drivers/common/sfc_efx/base/
H A Dhunt_nic.c73 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in hunt_board_cfg() local
108 encp->enc_bug35388_workaround = B_TRUE; in hunt_board_cfg()
121 encp->enc_bug41750_workaround = B_TRUE; in hunt_board_cfg()
133 if (EFX_PCI_FUNCTION_IS_VF(encp)) { in hunt_board_cfg()
135 encp->enc_bug41750_workaround = B_TRUE; in hunt_board_cfg()
147 if (encp->enc_bug35388_workaround) { in hunt_board_cfg()
148 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in hunt_board_cfg()
151 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in hunt_board_cfg()
158 encp->enc_bug61297_workaround = B_TRUE; in hunt_board_cfg()
165 encp->enc_rx_buf_align_start = 1; in hunt_board_cfg()
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H A Dmedford2_nic.c41 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in medford2_board_cfg() local
70 if (EFX_PCI_FUNCTION_IS_VF(encp)) { in medford2_board_cfg()
75 encp->enc_bug41750_workaround = B_TRUE; in medford2_board_cfg()
86 encp->enc_bug61265_workaround = B_TRUE; in medford2_board_cfg()
88 encp->enc_bug61265_workaround = B_FALSE; in medford2_board_cfg()
93 encp->enc_bug61297_workaround = B_FALSE; in medford2_board_cfg()
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in medford2_board_cfg()
112 encp->enc_rx_buf_align_start = 1; in medford2_board_cfg()
122 encp->enc_rx_buf_align_end = end_padding; in medford2_board_cfg()
124 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; in medford2_board_cfg()
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H A Dmedford_nic.c39 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in medford_board_cfg() local
68 if (EFX_PCI_FUNCTION_IS_VF(encp)) { in medford_board_cfg()
73 encp->enc_bug41750_workaround = B_TRUE; in medford_board_cfg()
84 encp->enc_bug61265_workaround = B_TRUE; in medford_board_cfg()
86 encp->enc_bug61265_workaround = B_FALSE; in medford_board_cfg()
91 encp->enc_bug61297_workaround = B_TRUE; in medford_board_cfg()
102 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in medford_board_cfg()
110 encp->enc_rx_buf_align_start = 1; in medford_board_cfg()
120 encp->enc_rx_buf_align_end = end_padding; in medford_board_cfg()
122 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; in medford_board_cfg()
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H A Drhead_nic.c49 encp->enc_tx_dma_desc_boundary = 0; in rhead_board_cfg()
57 encp->enc_tx_tso_max_header_ndescs = in rhead_board_cfg()
65 encp->enc_tx_tso_max_nframes = in rhead_board_cfg()
79 encp->enc_evq_limit = 1024; in rhead_board_cfg()
129 encp->enc_evq_timer_max_us = 0; in rhead_board_cfg()
134 encp->enc_ev_ew_desc_size = 0; in rhead_board_cfg()
142 encp->enc_rx_push_align = 1; in rhead_board_cfg()
148 encp->enc_rx_buf_align_start = 1; in rhead_board_cfg()
161 encp->enc_rx_scatter_max = 7; in rhead_board_cfg()
167 encp->enc_vpd_is_global = B_TRUE; in rhead_board_cfg()
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H A Dsiena_nic.c89 encp->enc_hw_pf_count = 1; in siena_board_cfg()
92 encp->enc_clk_mult = 1; in siena_board_cfg()
98 encp->enc_clk_mult = 2; in siena_board_cfg()
102 encp->enc_evq_timer_quantum_ns = in siena_board_cfg()
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in siena_board_cfg()
112 encp->enc_rx_prefix_size = 16; in siena_board_cfg()
116 encp->enc_rx_buf_align_end = 1; in siena_board_cfg()
119 encp->enc_rx_push_align = 1; in siena_board_cfg()
163 encp->enc_evq_limit = nevq; in siena_board_cfg()
185 encp->enc_rx_scatter_max = -1; in siena_board_cfg()
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H A Def10_nic.c1093 encp->enc_rx_prefix_size = 0; in ef10_get_datapath_caps()
1159 encp->enc_rx_batch_max = 16; in ef10_get_datapath_caps()
1168 encp->enc_rx_scatter_max = -1; in ef10_get_datapath_caps()
1471 encp->enc_mae_admin = B_FALSE; in ef10_get_datapath_caps()
1558 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf, in ef10_get_privilege_mask()
1987 encp->enc_pf = pf; in efx_mcdi_nic_board_cfg()
1988 encp->enc_vf = vf; in efx_mcdi_nic_board_cfg()
1989 encp->enc_intf = intf; in efx_mcdi_nic_board_cfg()
2085 encp->enc_intr_limit = nvec; in efx_mcdi_nic_board_cfg()
2270 encp->enc_evq_limit = 1024; in ef10_nic_board_cfg()
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H A Dmcdi_mon.c434 encp->enc_mcdi_sensor_maskp, in mcdi_mon_stats_update()
435 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_stats_update()
580 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
581 encp->enc_mcdi_sensor_maskp); in mcdi_mon_cfg_build()
590 encp->enc_mcdi_sensor_maskp, in mcdi_mon_cfg_build()
596 encp->enc_mcdi_sensor_maskp, in mcdi_mon_cfg_build()
597 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
605 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
606 encp->enc_mcdi_sensor_maskp); in mcdi_mon_cfg_build()
628 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_free()
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H A Def10_rx.c22 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_mcdi_rss_context_alloc() local
37 table_nentries_min = encp->enc_rx_scale_tbl_min_nentries; in efx_mcdi_rss_context_alloc()
38 table_nentries_max = encp->enc_rx_scale_tbl_max_nentries; in efx_mcdi_rss_context_alloc()
43 table_nentries_min = encp->enc_rx_scale_tbl_min_nentries; in efx_mcdi_rss_context_alloc()
44 table_nentries_max = encp->enc_rx_scale_tbl_max_nentries; in efx_mcdi_rss_context_alloc()
187 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_mcdi_rss_context_set_flags() local
396 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_mcdi_rss_context_write_table() local
411 encp->enc_rx_scale_tbl_max_nentries) { in efx_mcdi_rss_context_write_table()
555 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in ef10_rx_scale_mode_set() local
634 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in ef10_rx_scale_tbl_set() local
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H A Defx_nic.c406 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_nic_probe() local
440 encp->enc_features = enp->en_features; in efx_nic_probe()
562 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_nic_get_vi_pool() local
580 *evq_countp = encp->enc_evq_limit; in efx_nic_get_vi_pool()
581 *rxq_countp = encp->enc_rxq_limit; in efx_nic_get_vi_pool()
582 *txq_countp = encp->enc_txq_limit; in efx_nic_get_vi_pool()
1018 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mcdi_get_loopback_modes() local
1261 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_nic_check_pcie_link_speed() local
1479 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_nic_dma_config_add() local
1482 switch (encp->enc_dma_mapping) { in efx_nic_dma_config_add()
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H A Defx_ev.c211 desc_size = encp->enc_ev_desc_size; in efx_evq_size()
215 desc_size = encp->enc_ev_ew_desc_size; in efx_evq_size()
279 if (index >= encp->enc_evq_limit) { in efx_ev_qcreate_irq()
284 if (us > encp->enc_evq_timer_max_us) { in efx_ev_qcreate_irq()
304 (encp->enc_ev_ew_desc_size == 0)) { in efx_ev_qcreate_irq()
314 ndescs < encp->enc_evq_min_nevs || in efx_ev_qcreate_irq()
315 ndescs > encp->enc_evq_max_nevs) { in efx_ev_qcreate_irq()
495 const efx_nic_cfg_t *encp; in efx_ev_qcreate_check_init_done() local
502 encp = efx_nic_cfg_get(eep->ee_enp); in efx_ev_qcreate_check_init_done()
1254 if (us > encp->enc_evq_timer_max_us) { in siena_ev_qmoderate()
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H A Def10_mac.c224 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mac_pdu_set() local
227 if (encp->enc_enhanced_set_mac_supported) { in ef10_mac_pdu_set()
470 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mac_stats_get_mask() local
487 if (encp->enc_mac_stats_40g_tx_size_bins) { in ef10_mac_stats_get_mask()
499 if (encp->enc_pm_and_rxdp_counters) { in ef10_mac_stats_get_mask()
509 if (encp->enc_datapath_cap_evb) { in ef10_mac_stats_get_mask()
520 if (encp->enc_fec_counters) { in ef10_mac_stats_get_mask()
541 if (encp->enc_hlb_counters) { in ef10_mac_stats_get_mask()
585 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; in ef10_mac_stats_update() local
608 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) { in ef10_mac_stats_update()
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H A Defx_rx.c340 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_rx_scale_hash_flags_get() local
610 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_rx_scale_mode_set() local
851 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_rxq_size() local
853 return (ndescs * encp->enc_rx_desc_size); in efx_rxq_size()
900 EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs)); in efx_rx_qcreate_internal()
901 EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs)); in efx_rx_qcreate_internal()
903 if (index >= encp->enc_rxq_limit) { in efx_rx_qcreate_internal()
909 ndescs < encp->enc_rxq_min_ndescs || in efx_rx_qcreate_internal()
910 ndescs > encp->enc_rxq_max_ndescs) { in efx_rx_qcreate_internal()
1751 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_rx_qcreate() local
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H A Defx_tx.c338 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_txq_size() local
340 return (ndescs * encp->enc_tx_desc_size); in efx_txq_size()
375 EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs)); in efx_tx_qcreate()
376 EFSYS_ASSERT(ISP2(encp->enc_txq_min_ndescs)); in efx_tx_qcreate()
379 ndescs < encp->enc_txq_min_ndescs || in efx_tx_qcreate()
380 ndescs > encp->enc_txq_max_ndescs) { in efx_tx_qcreate()
883 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_tx_qpace() local
896 timer_period = 104 / encp->enc_clk_mult; in siena_tx_qpace()
977 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_tx_qcreate() local
989 if (index >= encp->enc_txq_limit) { in siena_tx_qcreate()
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H A Defx_mae.c272 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_init()
347 if (encp->enc_mae_supported == B_FALSE) in efx_mae_fini()
367 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_get_limits()
874 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_mport_id_by_selector()
2203 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_outer_rule_insert()
2306 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_outer_rule_remove()
2406 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_mac_addr_alloc()
2472 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_mac_addr_free()
2627 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_encap_header_alloc()
2719 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_encap_header_free()
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H A Defx_mon.c27 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mon_name() local
31 EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); in efx_mon_name()
32 EFSYS_ASSERT3U(encp->enc_mon_type, <, EFX_MON_NTYPES); in efx_mon_name()
33 return (__efx_mon_name[encp->enc_mon_type]); in efx_mon_name()
52 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mon_init() local
67 emp->em_type = encp->enc_mon_type; in efx_mon_init()
69 EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); in efx_mon_init()
H A Dsiena_sram.c16 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_sram_init() local
23 rx_base = encp->enc_buftbl_limit; in siena_sram_init()
24 tx_base = rx_base + (encp->enc_rxq_limit * in siena_sram_init()
H A Def10_mcdi.c110 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mcdi_get_timeout() local
117 if (encp->enc_nvram_update_verify_result_supported != B_FALSE) { in ef10_mcdi_get_timeout()
291 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mcdi_feature_supported() local
292 uint32_t privilege_mask = encp->enc_privilege_mask; in ef10_mcdi_feature_supported()
H A Defx_mcdi.c1718 (void) memset(encp->enc_phy_name, 0, in efx_mcdi_get_phy_cfg()
1719 sizeof (encp->enc_phy_name)); in efx_mcdi_get_phy_cfg()
1722 (void) memset(encp->enc_phy_revision, 0, in efx_mcdi_get_phy_cfg()
1723 sizeof (encp->enc_phy_revision)); in efx_mcdi_get_phy_cfg()
1724 memcpy(encp->enc_phy_revision, in efx_mcdi_get_phy_cfg()
1756 encp->enc_mcdi_mdio_channel = in efx_mcdi_get_phy_cfg()
1760 encp->enc_mcdi_phy_stat_mask = in efx_mcdi_get_phy_cfg()
1765 encp->enc_bist_mask = 0; in efx_mcdi_get_phy_cfg()
2737 if (encp->enc_init_evq_v2_supported) { in efx_mcdi_init_evq()
2855 if (encp->enc_init_evq_v2_supported) { in efx_mcdi_init_evq()
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H A Defx_phy.c76 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_phy_probe() local
82 epp->ep_port = encp->enc_port; in efx_phy_probe()
83 epp->ep_phy_type = encp->enc_phy_type; in efx_phy_probe()
155 efx_nic_cfg_t *encp = (&enp->en_nic_cfg); in efx_phy_led_set() local
168 mask |= encp->enc_led_mask; in efx_phy_led_set()
H A Def10_intr.c96 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_intr_trigger() local
99 if (encp->enc_bug41750_workaround) { in ef10_intr_trigger()
/dpdk/drivers/net/sfc/
H A Dsfc.c240 MIN(encp->enc_txq_limit, in sfc_estimate_resource_limits()
246 encp->enc_fw_assisted_tso_v2_n_contexts / in sfc_estimate_resource_limits()
247 encp->enc_hw_pf_count); in sfc_estimate_resource_limits()
444 const efx_nic_cfg_t *encp; in sfc_try_start() local
474 encp = efx_nic_cfg_get(sa->nic); in sfc_try_start()
482 encp->enc_tunnel_encapsulations_supported; in sfc_try_start()
881 const efx_nic_cfg_t *encp; in sfc_attach() local
910 encp = efx_nic_cfg_get(sa->nic); in sfc_attach()
917 encp->enc_tunnel_encapsulations_supported; in sfc_attach()
921 encp->enc_tso_v3_enabled; in sfc_attach()
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H A Dsfc_tx.c56 if (!encp->enc_hw_tx_insert_vlan_enabled) in sfc_tx_get_offload_mask()
59 if (!encp->enc_tunnel_encapsulations_supported) in sfc_tx_get_offload_mask()
66 (encp->enc_tunnel_encapsulations_supported & in sfc_tx_get_offload_mask()
71 (encp->enc_tunnel_encapsulations_supported & in sfc_tx_get_offload_mask()
216 encp->enc_tx_tso_tcp_header_offset_limit; in sfc_tx_qinit()
218 RTE_MIN(encp->enc_tx_tso_max_header_ndescs, in sfc_tx_qinit()
221 RTE_MIN(encp->enc_tx_tso_max_header_length, in sfc_tx_qinit()
224 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs, in sfc_tx_qinit()
402 if (encp->enc_tx_dma_desc_boundary != 0) { in sfc_tx_configure()
702 !encp->enc_tso_v3_enabled) { in sfc_tx_start()
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H A Dsfc_nic_dma.c227 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_nic_dma_attach() local
230 sfc_log_init(sa, "dma_mapping_type=%u", encp->enc_dma_mapping); in sfc_nic_dma_attach()
232 switch (encp->enc_dma_mapping) { in sfc_nic_dma_attach()
252 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_nic_dma_detach() local
254 sfc_log_init(sa, "dma_mapping_type=%u", encp->enc_dma_mapping); in sfc_nic_dma_detach()
256 switch (encp->enc_dma_mapping) { in sfc_nic_dma_detach()
H A Dsfc_flow_rss.c24 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_flow_rss_attach() local
30 flow_rss->qid_span_max = encp->enc_rx_scale_indirection_max_nqueues; in sfc_flow_rss_attach()
31 flow_rss->nb_tbl_entries_min = encp->enc_rx_scale_tbl_min_nentries; in sfc_flow_rss_attach()
32 flow_rss->nb_tbl_entries_max = encp->enc_rx_scale_tbl_max_nentries; in sfc_flow_rss_attach()
344 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_flow_rss_ctx_program() local
377 conf->qid_span <= encp->enc_rx_scale_even_spread_max_nqueues) { in sfc_flow_rss_ctx_program()
H A Dsfc_rx.c935 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_get_offload_mask() local
938 if (encp->enc_tunnel_encapsulations_supported == 0) in sfc_rx_get_offload_mask()
1008 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_mb_pool_buf_size() local
1095 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_qinit() local
1147 encp->enc_rx_prefix_size, in sfc_rx_qinit()
1149 encp->enc_rx_scatter_max, in sfc_rx_qinit()
1237 info.batch_max = encp->enc_rx_batch_max; in sfc_rx_qinit()
1238 info.prefix_size = encp->enc_rx_prefix_size; in sfc_rx_qinit()
1253 info.vi_window_shift = encp->enc_vi_window_shift; in sfc_rx_qinit()
1377 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_hash_init() local
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