1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2006-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_H 8 #define _SYS_EFX_H 9 10 #include "efx_annote.h" 11 #include "efsys.h" 12 #include "efx_types.h" 13 #include "efx_check.h" 14 #include "efx_phy_ids.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define EFX_STATIC_ASSERT(_cond) \ 21 ((void)sizeof (char[(_cond) ? 1 : -1])) 22 23 #define EFX_ARRAY_SIZE(_array) \ 24 (sizeof (_array) / sizeof ((_array)[0])) 25 26 #define EFX_FIELD_OFFSET(_type, _field) \ 27 ((size_t)&(((_type *)0)->_field)) 28 29 /* The macro expands divider twice */ 30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 31 32 /* Round value up to the nearest power of two. */ 33 #define EFX_P2ROUNDUP(_type, _value, _align) \ 34 (-(-(_type)(_value) & -(_type)(_align))) 35 36 /* Align value down to the nearest power of two. */ 37 #define EFX_P2ALIGN(_type, _value, _align) \ 38 ((_type)(_value) & -(_type)(_align)) 39 40 /* Test if value is power of 2 aligned. */ 41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 43 44 /* Return codes */ 45 46 typedef __success(return == 0) int efx_rc_t; 47 48 49 /* Chip families */ 50 51 typedef enum efx_family_e { 52 EFX_FAMILY_INVALID, 53 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 54 EFX_FAMILY_SIENA, 55 EFX_FAMILY_HUNTINGTON, 56 EFX_FAMILY_MEDFORD, 57 EFX_FAMILY_MEDFORD2, 58 EFX_FAMILY_RIVERHEAD, 59 EFX_FAMILY_NTYPES 60 } efx_family_t; 61 62 typedef enum efx_bar_type_e { 63 EFX_BAR_TYPE_MEM, 64 EFX_BAR_TYPE_IO 65 } efx_bar_type_t; 66 67 typedef struct efx_bar_region_s { 68 efx_bar_type_t ebr_type; 69 int ebr_index; 70 efsys_dma_addr_t ebr_offset; 71 efsys_dma_addr_t ebr_length; 72 } efx_bar_region_t; 73 74 /* The function is deprecated. It is used only if Riverhead is not supported. */ 75 LIBEFX_API 76 extern __checkReturn efx_rc_t 77 efx_family( 78 __in uint16_t venid, 79 __in uint16_t devid, 80 __out efx_family_t *efp, 81 __out unsigned int *membarp); 82 83 #if EFSYS_OPT_PCI 84 85 /* PCIe interface numbers for multi-host configurations. */ 86 typedef enum efx_pcie_interface_e { 87 EFX_PCIE_INTERFACE_CALLER = 1000, 88 EFX_PCIE_INTERFACE_HOST_PRIMARY, 89 EFX_PCIE_INTERFACE_NIC_EMBEDDED, 90 } efx_pcie_interface_t; 91 92 typedef struct efx_pci_ops_s { 93 /* 94 * Function for reading PCIe configuration space. 95 * 96 * espcp System-specific PCIe device handle; 97 * offset Offset inside PCIe configuration space to start reading 98 * from; 99 * edp EFX DWORD structure that should be populated by function 100 * in little-endian order; 101 * 102 * Returns status code, 0 on success, any other value on error. 103 */ 104 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp, 105 uint32_t offset, efx_dword_t *edp); 106 /* 107 * Function for finding PCIe memory bar handle by its index from a PCIe 108 * device handle. The found memory bar is available in read-only mode. 109 * 110 * configp System-specific PCIe device handle; 111 * index Memory bar index; 112 * memp Pointer to the found memory bar handle; 113 * 114 * Returns status code, 0 on success, any other value on error. 115 */ 116 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp, 117 int index, efsys_bar_t *memp); 118 } efx_pci_ops_t; 119 120 /* Determine EFX family and perform lookup of the function control window 121 * 122 * The function requires PCI config handle from which all memory bars can 123 * be accessed. 124 * A user of the API must be aware of memory bars indexes (not available 125 * on Windows). 126 */ 127 LIBEFX_API 128 extern __checkReturn efx_rc_t 129 efx_family_probe_bar( 130 __in uint16_t venid, 131 __in uint16_t devid, 132 __in efsys_pci_config_t *espcp, 133 __in const efx_pci_ops_t *epop, 134 __out efx_family_t *efp, 135 __out efx_bar_region_t *ebrp); 136 137 #endif /* EFSYS_OPT_PCI */ 138 139 140 #define EFX_PCI_VENID_SFC 0x1924 141 #define EFX_PCI_VENID_XILINX 0x10EE 142 143 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 144 145 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 146 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 147 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 148 149 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 150 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 151 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 152 153 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 154 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 155 156 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 157 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 158 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 159 160 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 161 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 162 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 163 164 #define EFX_PCI_DEVID_RIVERHEAD 0x0100 165 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100 166 167 #define EFX_MEM_BAR_SIENA 2 168 169 #define EFX_MEM_BAR_HUNTINGTON_PF 2 170 #define EFX_MEM_BAR_HUNTINGTON_VF 0 171 172 #define EFX_MEM_BAR_MEDFORD_PF 2 173 #define EFX_MEM_BAR_MEDFORD_VF 0 174 175 #define EFX_MEM_BAR_MEDFORD2 0 176 177 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */ 178 #define EFX_MEM_BAR_RIVERHEAD 2 179 180 181 /* Error codes */ 182 183 enum { 184 EFX_ERR_INVALID, 185 EFX_ERR_SRAM_OOB, 186 EFX_ERR_BUFID_DC_OOB, 187 EFX_ERR_MEM_PERR, 188 EFX_ERR_RBUF_OWN, 189 EFX_ERR_TBUF_OWN, 190 EFX_ERR_RDESQ_OWN, 191 EFX_ERR_TDESQ_OWN, 192 EFX_ERR_EVQ_OWN, 193 EFX_ERR_EVFF_OFLO, 194 EFX_ERR_ILL_ADDR, 195 EFX_ERR_SRAM_PERR, 196 EFX_ERR_NCODES 197 }; 198 199 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 200 LIBEFX_API 201 extern __checkReturn uint32_t 202 efx_crc32_calculate( 203 __in uint32_t crc_init, 204 __in_ecount(length) uint8_t const *input, 205 __in int length); 206 207 208 /* Type prototypes */ 209 210 typedef struct efx_rxq_s efx_rxq_t; 211 212 /* NIC */ 213 214 typedef struct efx_nic_s efx_nic_t; 215 216 LIBEFX_API 217 extern __checkReturn efx_rc_t 218 efx_nic_create( 219 __in efx_family_t family, 220 __in efsys_identifier_t *esip, 221 __in efsys_bar_t *esbp, 222 __in uint32_t fcw_offset, 223 __in efsys_lock_t *eslp, 224 __deref_out efx_nic_t **enpp); 225 226 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 227 typedef enum efx_fw_variant_e { 228 EFX_FW_VARIANT_FULL_FEATURED, 229 EFX_FW_VARIANT_LOW_LATENCY, 230 EFX_FW_VARIANT_PACKED_STREAM, 231 EFX_FW_VARIANT_HIGH_TX_RATE, 232 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 233 EFX_FW_VARIANT_RULES_ENGINE, 234 EFX_FW_VARIANT_DPDK, 235 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 236 } efx_fw_variant_t; 237 238 LIBEFX_API 239 extern __checkReturn efx_rc_t 240 efx_nic_probe( 241 __in efx_nic_t *enp, 242 __in efx_fw_variant_t efv); 243 244 LIBEFX_API 245 extern __checkReturn efx_rc_t 246 efx_nic_init( 247 __in efx_nic_t *enp); 248 249 LIBEFX_API 250 extern __checkReturn efx_rc_t 251 efx_nic_reset( 252 __in efx_nic_t *enp); 253 254 LIBEFX_API 255 extern __checkReturn boolean_t 256 efx_nic_hw_unavailable( 257 __in efx_nic_t *enp); 258 259 LIBEFX_API 260 extern void 261 efx_nic_set_hw_unavailable( 262 __in efx_nic_t *enp); 263 264 #if EFSYS_OPT_DIAG 265 266 LIBEFX_API 267 extern __checkReturn efx_rc_t 268 efx_nic_register_test( 269 __in efx_nic_t *enp); 270 271 #endif /* EFSYS_OPT_DIAG */ 272 273 LIBEFX_API 274 extern void 275 efx_nic_fini( 276 __in efx_nic_t *enp); 277 278 LIBEFX_API 279 extern void 280 efx_nic_unprobe( 281 __in efx_nic_t *enp); 282 283 LIBEFX_API 284 extern void 285 efx_nic_destroy( 286 __in efx_nic_t *enp); 287 288 #define EFX_PCIE_LINK_SPEED_GEN1 1 289 #define EFX_PCIE_LINK_SPEED_GEN2 2 290 #define EFX_PCIE_LINK_SPEED_GEN3 3 291 292 typedef enum efx_pcie_link_performance_e { 293 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 294 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 295 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 296 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 297 } efx_pcie_link_performance_t; 298 299 LIBEFX_API 300 extern __checkReturn efx_rc_t 301 efx_nic_calculate_pcie_link_bandwidth( 302 __in uint32_t pcie_link_width, 303 __in uint32_t pcie_link_gen, 304 __out uint32_t *bandwidth_mbpsp); 305 306 LIBEFX_API 307 extern __checkReturn efx_rc_t 308 efx_nic_check_pcie_link_speed( 309 __in efx_nic_t *enp, 310 __in uint32_t pcie_link_width, 311 __in uint32_t pcie_link_gen, 312 __out efx_pcie_link_performance_t *resultp); 313 314 #if EFSYS_OPT_MCDI 315 316 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 317 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */ 318 #define WITH_MCDI_V2 1 319 #endif 320 321 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 322 323 typedef enum efx_mcdi_exception_e { 324 EFX_MCDI_EXCEPTION_MC_REBOOT, 325 EFX_MCDI_EXCEPTION_MC_BADASSERT, 326 } efx_mcdi_exception_t; 327 328 #if EFSYS_OPT_MCDI_LOGGING 329 typedef enum efx_log_msg_e { 330 EFX_LOG_INVALID, 331 EFX_LOG_MCDI_REQUEST, 332 EFX_LOG_MCDI_RESPONSE, 333 } efx_log_msg_t; 334 #endif /* EFSYS_OPT_MCDI_LOGGING */ 335 336 typedef struct efx_mcdi_transport_s { 337 void *emt_context; 338 efsys_mem_t *emt_dma_mem; 339 void (*emt_execute)(void *, efx_mcdi_req_t *); 340 void (*emt_ev_cpl)(void *); 341 void (*emt_exception)(void *, efx_mcdi_exception_t); 342 #if EFSYS_OPT_MCDI_LOGGING 343 void (*emt_logger)(void *, efx_log_msg_t, 344 void *, size_t, void *, size_t); 345 #endif /* EFSYS_OPT_MCDI_LOGGING */ 346 #if EFSYS_OPT_MCDI_PROXY_AUTH 347 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 348 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 349 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 350 void (*emt_ev_proxy_request)(void *, uint32_t); 351 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 352 } efx_mcdi_transport_t; 353 354 LIBEFX_API 355 extern __checkReturn efx_rc_t 356 efx_mcdi_init( 357 __in efx_nic_t *enp, 358 __in const efx_mcdi_transport_t *mtp); 359 360 LIBEFX_API 361 extern __checkReturn efx_rc_t 362 efx_mcdi_reboot( 363 __in efx_nic_t *enp); 364 365 LIBEFX_API 366 extern void 367 efx_mcdi_new_epoch( 368 __in efx_nic_t *enp); 369 370 LIBEFX_API 371 extern void 372 efx_mcdi_get_timeout( 373 __in efx_nic_t *enp, 374 __in efx_mcdi_req_t *emrp, 375 __out uint32_t *usec_timeoutp); 376 377 LIBEFX_API 378 extern void 379 efx_mcdi_request_start( 380 __in efx_nic_t *enp, 381 __in efx_mcdi_req_t *emrp, 382 __in boolean_t ev_cpl); 383 384 LIBEFX_API 385 extern __checkReturn boolean_t 386 efx_mcdi_request_poll( 387 __in efx_nic_t *enp); 388 389 LIBEFX_API 390 extern __checkReturn boolean_t 391 efx_mcdi_request_abort( 392 __in efx_nic_t *enp); 393 394 LIBEFX_API 395 extern __checkReturn efx_rc_t 396 efx_mcdi_get_client_handle( 397 __in efx_nic_t *enp, 398 __in efx_pcie_interface_t intf, 399 __in uint16_t pf, 400 __in uint16_t vf, 401 __out uint32_t *handle); 402 403 LIBEFX_API 404 extern __checkReturn efx_rc_t 405 efx_mcdi_get_own_client_handle( 406 __in efx_nic_t *enp, 407 __out uint32_t *handle); 408 409 LIBEFX_API 410 extern void 411 efx_mcdi_fini( 412 __in efx_nic_t *enp); 413 414 #endif /* EFSYS_OPT_MCDI */ 415 416 /* INTR */ 417 418 #define EFX_NINTR_SIENA 1024 419 420 typedef enum efx_intr_type_e { 421 EFX_INTR_INVALID = 0, 422 EFX_INTR_LINE, 423 EFX_INTR_MESSAGE, 424 EFX_INTR_NTYPES 425 } efx_intr_type_t; 426 427 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 428 429 LIBEFX_API 430 extern __checkReturn efx_rc_t 431 efx_intr_init( 432 __in efx_nic_t *enp, 433 __in efx_intr_type_t type, 434 __in_opt efsys_mem_t *esmp); 435 436 LIBEFX_API 437 extern void 438 efx_intr_enable( 439 __in efx_nic_t *enp); 440 441 LIBEFX_API 442 extern void 443 efx_intr_disable( 444 __in efx_nic_t *enp); 445 446 LIBEFX_API 447 extern void 448 efx_intr_disable_unlocked( 449 __in efx_nic_t *enp); 450 451 #define EFX_INTR_NEVQS 32 452 453 LIBEFX_API 454 extern __checkReturn efx_rc_t 455 efx_intr_trigger( 456 __in efx_nic_t *enp, 457 __in unsigned int level); 458 459 LIBEFX_API 460 extern void 461 efx_intr_status_line( 462 __in efx_nic_t *enp, 463 __out boolean_t *fatalp, 464 __out uint32_t *maskp); 465 466 LIBEFX_API 467 extern void 468 efx_intr_status_message( 469 __in efx_nic_t *enp, 470 __in unsigned int message, 471 __out boolean_t *fatalp); 472 473 LIBEFX_API 474 extern void 475 efx_intr_fatal( 476 __in efx_nic_t *enp); 477 478 LIBEFX_API 479 extern void 480 efx_intr_fini( 481 __in efx_nic_t *enp); 482 483 /* MAC */ 484 485 #if EFSYS_OPT_MAC_STATS 486 487 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 488 typedef enum efx_mac_stat_e { 489 EFX_MAC_RX_OCTETS, 490 EFX_MAC_RX_PKTS, 491 EFX_MAC_RX_UNICST_PKTS, 492 EFX_MAC_RX_MULTICST_PKTS, 493 EFX_MAC_RX_BRDCST_PKTS, 494 EFX_MAC_RX_PAUSE_PKTS, 495 EFX_MAC_RX_LE_64_PKTS, 496 EFX_MAC_RX_65_TO_127_PKTS, 497 EFX_MAC_RX_128_TO_255_PKTS, 498 EFX_MAC_RX_256_TO_511_PKTS, 499 EFX_MAC_RX_512_TO_1023_PKTS, 500 EFX_MAC_RX_1024_TO_15XX_PKTS, 501 EFX_MAC_RX_GE_15XX_PKTS, 502 EFX_MAC_RX_ERRORS, 503 EFX_MAC_RX_FCS_ERRORS, 504 EFX_MAC_RX_DROP_EVENTS, 505 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 506 EFX_MAC_RX_SYMBOL_ERRORS, 507 EFX_MAC_RX_ALIGN_ERRORS, 508 EFX_MAC_RX_INTERNAL_ERRORS, 509 EFX_MAC_RX_JABBER_PKTS, 510 EFX_MAC_RX_LANE0_CHAR_ERR, 511 EFX_MAC_RX_LANE1_CHAR_ERR, 512 EFX_MAC_RX_LANE2_CHAR_ERR, 513 EFX_MAC_RX_LANE3_CHAR_ERR, 514 EFX_MAC_RX_LANE0_DISP_ERR, 515 EFX_MAC_RX_LANE1_DISP_ERR, 516 EFX_MAC_RX_LANE2_DISP_ERR, 517 EFX_MAC_RX_LANE3_DISP_ERR, 518 EFX_MAC_RX_MATCH_FAULT, 519 EFX_MAC_RX_NODESC_DROP_CNT, 520 EFX_MAC_TX_OCTETS, 521 EFX_MAC_TX_PKTS, 522 EFX_MAC_TX_UNICST_PKTS, 523 EFX_MAC_TX_MULTICST_PKTS, 524 EFX_MAC_TX_BRDCST_PKTS, 525 EFX_MAC_TX_PAUSE_PKTS, 526 EFX_MAC_TX_LE_64_PKTS, 527 EFX_MAC_TX_65_TO_127_PKTS, 528 EFX_MAC_TX_128_TO_255_PKTS, 529 EFX_MAC_TX_256_TO_511_PKTS, 530 EFX_MAC_TX_512_TO_1023_PKTS, 531 EFX_MAC_TX_1024_TO_15XX_PKTS, 532 EFX_MAC_TX_GE_15XX_PKTS, 533 EFX_MAC_TX_ERRORS, 534 EFX_MAC_TX_SGL_COL_PKTS, 535 EFX_MAC_TX_MULT_COL_PKTS, 536 EFX_MAC_TX_EX_COL_PKTS, 537 EFX_MAC_TX_LATE_COL_PKTS, 538 EFX_MAC_TX_DEF_PKTS, 539 EFX_MAC_TX_EX_DEF_PKTS, 540 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 541 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 542 EFX_MAC_PM_TRUNC_VFIFO_FULL, 543 EFX_MAC_PM_DISCARD_VFIFO_FULL, 544 EFX_MAC_PM_TRUNC_QBB, 545 EFX_MAC_PM_DISCARD_QBB, 546 EFX_MAC_PM_DISCARD_MAPPING, 547 EFX_MAC_RXDP_Q_DISABLED_PKTS, 548 EFX_MAC_RXDP_DI_DROPPED_PKTS, 549 EFX_MAC_RXDP_STREAMING_PKTS, 550 EFX_MAC_RXDP_HLB_FETCH, 551 EFX_MAC_RXDP_HLB_WAIT, 552 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 553 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 554 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 555 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 556 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 557 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 558 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 559 EFX_MAC_VADAPTER_RX_BAD_BYTES, 560 EFX_MAC_VADAPTER_RX_OVERFLOW, 561 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 562 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 563 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 564 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 565 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 566 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 567 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 568 EFX_MAC_VADAPTER_TX_BAD_BYTES, 569 EFX_MAC_VADAPTER_TX_OVERFLOW, 570 EFX_MAC_FEC_UNCORRECTED_ERRORS, 571 EFX_MAC_FEC_CORRECTED_ERRORS, 572 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 573 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 574 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 575 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 576 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 577 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 578 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 579 EFX_MAC_CTPIO_OVERFLOW_FAIL, 580 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 581 EFX_MAC_CTPIO_TIMEOUT_FAIL, 582 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 583 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 584 EFX_MAC_CTPIO_INVALID_WR_FAIL, 585 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 586 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 587 EFX_MAC_CTPIO_RUNT_FALLBACK, 588 EFX_MAC_CTPIO_SUCCESS, 589 EFX_MAC_CTPIO_FALLBACK, 590 EFX_MAC_CTPIO_POISON, 591 EFX_MAC_CTPIO_ERASE, 592 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 593 EFX_MAC_RXDP_HLB_IDLE, 594 EFX_MAC_RXDP_HLB_TIMEOUT, 595 EFX_MAC_NSTATS 596 } efx_mac_stat_t; 597 598 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 599 600 #endif /* EFSYS_OPT_MAC_STATS */ 601 602 typedef enum efx_link_mode_e { 603 EFX_LINK_UNKNOWN = 0, 604 EFX_LINK_DOWN, 605 EFX_LINK_10HDX, 606 EFX_LINK_10FDX, 607 EFX_LINK_100HDX, 608 EFX_LINK_100FDX, 609 EFX_LINK_1000HDX, 610 EFX_LINK_1000FDX, 611 EFX_LINK_10000FDX, 612 EFX_LINK_40000FDX, 613 EFX_LINK_25000FDX, 614 EFX_LINK_50000FDX, 615 EFX_LINK_100000FDX, 616 EFX_LINK_NMODES 617 } efx_link_mode_t; 618 619 #define EFX_MAC_ADDR_LEN 6 620 621 #define EFX_VNI_OR_VSID_LEN 3 622 623 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 624 625 #define EFX_MAC_MULTICAST_LIST_MAX 256 626 627 #define EFX_MAC_SDU_MAX 9202 628 629 #define EFX_MAC_PDU_ADJUSTMENT \ 630 (/* EtherII */ 14 \ 631 + /* VLAN */ 4 \ 632 + /* CRC */ 4 \ 633 + /* bug16011 */ 16) \ 634 635 #define EFX_MAC_PDU(_sdu) \ 636 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 637 638 /* 639 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 640 * the SDU rounded up slightly. 641 */ 642 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 643 644 #define EFX_MAC_PDU_MIN 60 645 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 646 647 LIBEFX_API 648 extern __checkReturn efx_rc_t 649 efx_mac_pdu_get( 650 __in efx_nic_t *enp, 651 __out size_t *pdu); 652 653 LIBEFX_API 654 extern __checkReturn efx_rc_t 655 efx_mac_pdu_set( 656 __in efx_nic_t *enp, 657 __in size_t pdu); 658 659 LIBEFX_API 660 extern __checkReturn efx_rc_t 661 efx_mac_addr_set( 662 __in efx_nic_t *enp, 663 __in uint8_t *addr); 664 665 LIBEFX_API 666 extern __checkReturn efx_rc_t 667 efx_mac_filter_set( 668 __in efx_nic_t *enp, 669 __in boolean_t all_unicst, 670 __in boolean_t mulcst, 671 __in boolean_t all_mulcst, 672 __in boolean_t brdcst); 673 674 LIBEFX_API 675 extern void 676 efx_mac_filter_get_all_ucast_mcast( 677 __in efx_nic_t *enp, 678 __out boolean_t *all_unicst, 679 __out boolean_t *all_mulcst); 680 681 LIBEFX_API 682 extern __checkReturn efx_rc_t 683 efx_mac_multicast_list_set( 684 __in efx_nic_t *enp, 685 __in_ecount(6*count) uint8_t const *addrs, 686 __in int count); 687 688 LIBEFX_API 689 extern __checkReturn efx_rc_t 690 efx_mac_filter_default_rxq_set( 691 __in efx_nic_t *enp, 692 __in efx_rxq_t *erp, 693 __in boolean_t using_rss); 694 695 LIBEFX_API 696 extern void 697 efx_mac_filter_default_rxq_clear( 698 __in efx_nic_t *enp); 699 700 LIBEFX_API 701 extern __checkReturn efx_rc_t 702 efx_mac_drain( 703 __in efx_nic_t *enp, 704 __in boolean_t enabled); 705 706 LIBEFX_API 707 extern __checkReturn efx_rc_t 708 efx_mac_up( 709 __in efx_nic_t *enp, 710 __out boolean_t *mac_upp); 711 712 #define EFX_FCNTL_RESPOND 0x00000001 713 #define EFX_FCNTL_GENERATE 0x00000002 714 715 LIBEFX_API 716 extern __checkReturn efx_rc_t 717 efx_mac_fcntl_set( 718 __in efx_nic_t *enp, 719 __in unsigned int fcntl, 720 __in boolean_t autoneg); 721 722 LIBEFX_API 723 extern void 724 efx_mac_fcntl_get( 725 __in efx_nic_t *enp, 726 __out unsigned int *fcntl_wantedp, 727 __out unsigned int *fcntl_linkp); 728 729 730 #if EFSYS_OPT_MAC_STATS 731 732 #if EFSYS_OPT_NAMES 733 734 LIBEFX_API 735 extern __checkReturn const char * 736 efx_mac_stat_name( 737 __in efx_nic_t *enp, 738 __in unsigned int id); 739 740 #endif /* EFSYS_OPT_NAMES */ 741 742 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 743 744 #define EFX_MAC_STATS_MASK_NPAGES \ 745 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 746 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 747 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 748 749 /* 750 * Get mask of MAC statistics supported by the hardware. 751 * 752 * If mask_size is insufficient to return the mask, EINVAL error is 753 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 754 * (which is sizeof (uint32_t)) is sufficient. 755 */ 756 LIBEFX_API 757 extern __checkReturn efx_rc_t 758 efx_mac_stats_get_mask( 759 __in efx_nic_t *enp, 760 __out_bcount(mask_size) uint32_t *maskp, 761 __in size_t mask_size); 762 763 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 764 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 765 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 766 767 768 LIBEFX_API 769 extern __checkReturn efx_rc_t 770 efx_mac_stats_clear( 771 __in efx_nic_t *enp); 772 773 /* 774 * Upload mac statistics supported by the hardware into the given buffer. 775 * 776 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 777 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 778 * 779 * The hardware will only DMA statistics that it understands (of course). 780 * Drivers should not make any assumptions about which statistics are 781 * supported, especially when the statistics are generated by firmware. 782 * 783 * Thus, drivers should zero this buffer before use, so that not-understood 784 * statistics read back as zero. 785 */ 786 LIBEFX_API 787 extern __checkReturn efx_rc_t 788 efx_mac_stats_upload( 789 __in efx_nic_t *enp, 790 __in efsys_mem_t *esmp); 791 792 LIBEFX_API 793 extern __checkReturn efx_rc_t 794 efx_mac_stats_periodic( 795 __in efx_nic_t *enp, 796 __in efsys_mem_t *esmp, 797 __in uint16_t period_ms, 798 __in boolean_t events); 799 800 LIBEFX_API 801 extern __checkReturn efx_rc_t 802 efx_mac_stats_update( 803 __in efx_nic_t *enp, 804 __in efsys_mem_t *esmp, 805 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 806 __inout_opt uint32_t *generationp); 807 808 #endif /* EFSYS_OPT_MAC_STATS */ 809 810 /* MON */ 811 812 typedef enum efx_mon_type_e { 813 EFX_MON_INVALID = 0, 814 EFX_MON_SFC90X0, 815 EFX_MON_SFC91X0, 816 EFX_MON_SFC92X0, 817 EFX_MON_NTYPES 818 } efx_mon_type_t; 819 820 #if EFSYS_OPT_NAMES 821 822 LIBEFX_API 823 extern const char * 824 efx_mon_name( 825 __in efx_nic_t *enp); 826 827 #endif /* EFSYS_OPT_NAMES */ 828 829 LIBEFX_API 830 extern __checkReturn efx_rc_t 831 efx_mon_init( 832 __in efx_nic_t *enp); 833 834 #if EFSYS_OPT_MON_STATS 835 836 #define EFX_MON_STATS_PAGE_SIZE 0x100 837 #define EFX_MON_MASK_ELEMENT_SIZE 32 838 839 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 840 typedef enum efx_mon_stat_e { 841 EFX_MON_STAT_CONTROLLER_TEMP, 842 EFX_MON_STAT_PHY_COMMON_TEMP, 843 EFX_MON_STAT_CONTROLLER_COOLING, 844 EFX_MON_STAT_PHY0_TEMP, 845 EFX_MON_STAT_PHY0_COOLING, 846 EFX_MON_STAT_PHY1_TEMP, 847 EFX_MON_STAT_PHY1_COOLING, 848 EFX_MON_STAT_IN_1V0, 849 EFX_MON_STAT_IN_1V2, 850 EFX_MON_STAT_IN_1V8, 851 EFX_MON_STAT_IN_2V5, 852 EFX_MON_STAT_IN_3V3, 853 EFX_MON_STAT_IN_12V0, 854 EFX_MON_STAT_IN_1V2A, 855 EFX_MON_STAT_IN_VREF, 856 EFX_MON_STAT_OUT_VAOE, 857 EFX_MON_STAT_AOE_TEMP, 858 EFX_MON_STAT_PSU_AOE_TEMP, 859 EFX_MON_STAT_PSU_TEMP, 860 EFX_MON_STAT_FAN_0, 861 EFX_MON_STAT_FAN_1, 862 EFX_MON_STAT_FAN_2, 863 EFX_MON_STAT_FAN_3, 864 EFX_MON_STAT_FAN_4, 865 EFX_MON_STAT_IN_VAOE, 866 EFX_MON_STAT_OUT_IAOE, 867 EFX_MON_STAT_IN_IAOE, 868 EFX_MON_STAT_NIC_POWER, 869 EFX_MON_STAT_IN_0V9, 870 EFX_MON_STAT_IN_I0V9, 871 EFX_MON_STAT_IN_I1V2, 872 EFX_MON_STAT_IN_0V9_ADC, 873 EFX_MON_STAT_CONTROLLER_2_TEMP, 874 EFX_MON_STAT_VREG_INTERNAL_TEMP, 875 EFX_MON_STAT_VREG_0V9_TEMP, 876 EFX_MON_STAT_VREG_1V2_TEMP, 877 EFX_MON_STAT_CONTROLLER_VPTAT, 878 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 879 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 880 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 881 EFX_MON_STAT_AMBIENT_TEMP, 882 EFX_MON_STAT_AIRFLOW, 883 EFX_MON_STAT_VDD08D_VSS08D_CSR, 884 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 885 EFX_MON_STAT_HOTPOINT_TEMP, 886 EFX_MON_STAT_PHY_POWER_PORT0, 887 EFX_MON_STAT_PHY_POWER_PORT1, 888 EFX_MON_STAT_MUM_VCC, 889 EFX_MON_STAT_IN_0V9_A, 890 EFX_MON_STAT_IN_I0V9_A, 891 EFX_MON_STAT_VREG_0V9_A_TEMP, 892 EFX_MON_STAT_IN_0V9_B, 893 EFX_MON_STAT_IN_I0V9_B, 894 EFX_MON_STAT_VREG_0V9_B_TEMP, 895 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 896 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 897 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 898 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 899 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 900 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 901 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 902 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 903 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 904 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 905 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 906 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 907 EFX_MON_STAT_SODIMM_VOUT, 908 EFX_MON_STAT_SODIMM_0_TEMP, 909 EFX_MON_STAT_SODIMM_1_TEMP, 910 EFX_MON_STAT_PHY0_VCC, 911 EFX_MON_STAT_PHY1_VCC, 912 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 913 EFX_MON_STAT_BOARD_FRONT_TEMP, 914 EFX_MON_STAT_BOARD_BACK_TEMP, 915 EFX_MON_STAT_IN_I1V8, 916 EFX_MON_STAT_IN_I2V5, 917 EFX_MON_STAT_IN_I3V3, 918 EFX_MON_STAT_IN_I12V0, 919 EFX_MON_STAT_IN_1V3, 920 EFX_MON_STAT_IN_I1V3, 921 EFX_MON_NSTATS 922 } efx_mon_stat_t; 923 924 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 925 926 typedef enum efx_mon_stat_state_e { 927 EFX_MON_STAT_STATE_OK = 0, 928 EFX_MON_STAT_STATE_WARNING = 1, 929 EFX_MON_STAT_STATE_FATAL = 2, 930 EFX_MON_STAT_STATE_BROKEN = 3, 931 EFX_MON_STAT_STATE_NO_READING = 4, 932 } efx_mon_stat_state_t; 933 934 typedef enum efx_mon_stat_unit_e { 935 EFX_MON_STAT_UNIT_UNKNOWN = 0, 936 EFX_MON_STAT_UNIT_BOOL, 937 EFX_MON_STAT_UNIT_TEMP_C, 938 EFX_MON_STAT_UNIT_VOLTAGE_MV, 939 EFX_MON_STAT_UNIT_CURRENT_MA, 940 EFX_MON_STAT_UNIT_POWER_W, 941 EFX_MON_STAT_UNIT_RPM, 942 EFX_MON_NUNITS 943 } efx_mon_stat_unit_t; 944 945 typedef struct efx_mon_stat_value_s { 946 uint16_t emsv_value; 947 efx_mon_stat_state_t emsv_state; 948 efx_mon_stat_unit_t emsv_unit; 949 } efx_mon_stat_value_t; 950 951 typedef struct efx_mon_limit_value_s { 952 uint16_t emlv_warning_min; 953 uint16_t emlv_warning_max; 954 uint16_t emlv_fatal_min; 955 uint16_t emlv_fatal_max; 956 } efx_mon_stat_limits_t; 957 958 typedef enum efx_mon_stat_portmask_e { 959 EFX_MON_STAT_PORTMAP_NONE = 0, 960 EFX_MON_STAT_PORTMAP_PORT0 = 1, 961 EFX_MON_STAT_PORTMAP_PORT1 = 2, 962 EFX_MON_STAT_PORTMAP_PORT2 = 3, 963 EFX_MON_STAT_PORTMAP_PORT3 = 4, 964 EFX_MON_STAT_PORTMAP_ALL = (-1), 965 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 966 } efx_mon_stat_portmask_t; 967 968 #if EFSYS_OPT_NAMES 969 970 LIBEFX_API 971 extern const char * 972 efx_mon_stat_name( 973 __in efx_nic_t *enp, 974 __in efx_mon_stat_t id); 975 976 LIBEFX_API 977 extern const char * 978 efx_mon_stat_description( 979 __in efx_nic_t *enp, 980 __in efx_mon_stat_t id); 981 982 #endif /* EFSYS_OPT_NAMES */ 983 984 LIBEFX_API 985 extern __checkReturn boolean_t 986 efx_mon_mcdi_to_efx_stat( 987 __in int mcdi_index, 988 __out efx_mon_stat_t *statp); 989 990 LIBEFX_API 991 extern __checkReturn boolean_t 992 efx_mon_get_stat_unit( 993 __in efx_mon_stat_t stat, 994 __out efx_mon_stat_unit_t *unitp); 995 996 LIBEFX_API 997 extern __checkReturn boolean_t 998 efx_mon_get_stat_portmap( 999 __in efx_mon_stat_t stat, 1000 __out efx_mon_stat_portmask_t *maskp); 1001 1002 LIBEFX_API 1003 extern __checkReturn efx_rc_t 1004 efx_mon_stats_update( 1005 __in efx_nic_t *enp, 1006 __in efsys_mem_t *esmp, 1007 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 1008 1009 LIBEFX_API 1010 extern __checkReturn efx_rc_t 1011 efx_mon_limits_update( 1012 __in efx_nic_t *enp, 1013 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 1014 1015 #endif /* EFSYS_OPT_MON_STATS */ 1016 1017 LIBEFX_API 1018 extern void 1019 efx_mon_fini( 1020 __in efx_nic_t *enp); 1021 1022 /* PHY */ 1023 1024 LIBEFX_API 1025 extern __checkReturn efx_rc_t 1026 efx_phy_verify( 1027 __in efx_nic_t *enp); 1028 1029 typedef enum efx_phy_led_mode_e { 1030 EFX_PHY_LED_DEFAULT = 0, 1031 EFX_PHY_LED_OFF, 1032 EFX_PHY_LED_ON, 1033 EFX_PHY_LED_FLASH, 1034 EFX_PHY_LED_NMODES 1035 } efx_phy_led_mode_t; 1036 1037 #if EFSYS_OPT_PHY_LED_CONTROL 1038 1039 LIBEFX_API 1040 extern __checkReturn efx_rc_t 1041 efx_phy_led_set( 1042 __in efx_nic_t *enp, 1043 __in efx_phy_led_mode_t mode); 1044 1045 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1046 1047 LIBEFX_API 1048 extern __checkReturn efx_rc_t 1049 efx_port_init( 1050 __in efx_nic_t *enp); 1051 1052 #if EFSYS_OPT_LOOPBACK 1053 1054 typedef enum efx_loopback_type_e { 1055 EFX_LOOPBACK_OFF = 0, 1056 EFX_LOOPBACK_DATA = 1, 1057 EFX_LOOPBACK_GMAC = 2, 1058 EFX_LOOPBACK_XGMII = 3, 1059 EFX_LOOPBACK_XGXS = 4, 1060 EFX_LOOPBACK_XAUI = 5, 1061 EFX_LOOPBACK_GMII = 6, 1062 EFX_LOOPBACK_SGMII = 7, 1063 EFX_LOOPBACK_XGBR = 8, 1064 EFX_LOOPBACK_XFI = 9, 1065 EFX_LOOPBACK_XAUI_FAR = 10, 1066 EFX_LOOPBACK_GMII_FAR = 11, 1067 EFX_LOOPBACK_SGMII_FAR = 12, 1068 EFX_LOOPBACK_XFI_FAR = 13, 1069 EFX_LOOPBACK_GPHY = 14, 1070 EFX_LOOPBACK_PHY_XS = 15, 1071 EFX_LOOPBACK_PCS = 16, 1072 EFX_LOOPBACK_PMA_PMD = 17, 1073 EFX_LOOPBACK_XPORT = 18, 1074 EFX_LOOPBACK_XGMII_WS = 19, 1075 EFX_LOOPBACK_XAUI_WS = 20, 1076 EFX_LOOPBACK_XAUI_WS_FAR = 21, 1077 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 1078 EFX_LOOPBACK_GMII_WS = 23, 1079 EFX_LOOPBACK_XFI_WS = 24, 1080 EFX_LOOPBACK_XFI_WS_FAR = 25, 1081 EFX_LOOPBACK_PHYXS_WS = 26, 1082 EFX_LOOPBACK_PMA_INT = 27, 1083 EFX_LOOPBACK_SD_NEAR = 28, 1084 EFX_LOOPBACK_SD_FAR = 29, 1085 EFX_LOOPBACK_PMA_INT_WS = 30, 1086 EFX_LOOPBACK_SD_FEP2_WS = 31, 1087 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 1088 EFX_LOOPBACK_SD_FEP_WS = 33, 1089 EFX_LOOPBACK_SD_FES_WS = 34, 1090 EFX_LOOPBACK_AOE_INT_NEAR = 35, 1091 EFX_LOOPBACK_DATA_WS = 36, 1092 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 1093 EFX_LOOPBACK_NTYPES 1094 } efx_loopback_type_t; 1095 1096 typedef enum efx_loopback_kind_e { 1097 EFX_LOOPBACK_KIND_OFF = 0, 1098 EFX_LOOPBACK_KIND_ALL, 1099 EFX_LOOPBACK_KIND_MAC, 1100 EFX_LOOPBACK_KIND_PHY, 1101 EFX_LOOPBACK_NKINDS 1102 } efx_loopback_kind_t; 1103 1104 LIBEFX_API 1105 extern void 1106 efx_loopback_mask( 1107 __in efx_loopback_kind_t loopback_kind, 1108 __out efx_qword_t *maskp); 1109 1110 LIBEFX_API 1111 extern __checkReturn efx_rc_t 1112 efx_port_loopback_set( 1113 __in efx_nic_t *enp, 1114 __in efx_link_mode_t link_mode, 1115 __in efx_loopback_type_t type); 1116 1117 #if EFSYS_OPT_NAMES 1118 1119 LIBEFX_API 1120 extern __checkReturn const char * 1121 efx_loopback_type_name( 1122 __in efx_nic_t *enp, 1123 __in efx_loopback_type_t type); 1124 1125 #endif /* EFSYS_OPT_NAMES */ 1126 1127 #endif /* EFSYS_OPT_LOOPBACK */ 1128 1129 LIBEFX_API 1130 extern __checkReturn efx_rc_t 1131 efx_port_poll( 1132 __in efx_nic_t *enp, 1133 __out_opt efx_link_mode_t *link_modep); 1134 1135 LIBEFX_API 1136 extern void 1137 efx_port_fini( 1138 __in efx_nic_t *enp); 1139 1140 typedef enum efx_phy_cap_type_e { 1141 EFX_PHY_CAP_INVALID = 0, 1142 EFX_PHY_CAP_10HDX, 1143 EFX_PHY_CAP_10FDX, 1144 EFX_PHY_CAP_100HDX, 1145 EFX_PHY_CAP_100FDX, 1146 EFX_PHY_CAP_1000HDX, 1147 EFX_PHY_CAP_1000FDX, 1148 EFX_PHY_CAP_10000FDX, 1149 EFX_PHY_CAP_PAUSE, 1150 EFX_PHY_CAP_ASYM, 1151 EFX_PHY_CAP_AN, 1152 EFX_PHY_CAP_40000FDX, 1153 EFX_PHY_CAP_DDM, 1154 EFX_PHY_CAP_100000FDX, 1155 EFX_PHY_CAP_25000FDX, 1156 EFX_PHY_CAP_50000FDX, 1157 EFX_PHY_CAP_BASER_FEC, 1158 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1159 EFX_PHY_CAP_RS_FEC, 1160 EFX_PHY_CAP_RS_FEC_REQUESTED, 1161 EFX_PHY_CAP_25G_BASER_FEC, 1162 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1163 EFX_PHY_CAP_NTYPES 1164 } efx_phy_cap_type_t; 1165 1166 1167 #define EFX_PHY_CAP_CURRENT 0x00000000 1168 #define EFX_PHY_CAP_DEFAULT 0x00000001 1169 #define EFX_PHY_CAP_PERM 0x00000002 1170 1171 LIBEFX_API 1172 extern void 1173 efx_phy_adv_cap_get( 1174 __in efx_nic_t *enp, 1175 __in uint32_t flag, 1176 __out uint32_t *maskp); 1177 1178 LIBEFX_API 1179 extern __checkReturn efx_rc_t 1180 efx_phy_adv_cap_set( 1181 __in efx_nic_t *enp, 1182 __in uint32_t mask); 1183 1184 LIBEFX_API 1185 extern void 1186 efx_phy_lp_cap_get( 1187 __in efx_nic_t *enp, 1188 __out uint32_t *maskp); 1189 1190 LIBEFX_API 1191 extern __checkReturn efx_rc_t 1192 efx_phy_oui_get( 1193 __in efx_nic_t *enp, 1194 __out uint32_t *ouip); 1195 1196 typedef enum efx_phy_media_type_e { 1197 EFX_PHY_MEDIA_INVALID = 0, 1198 EFX_PHY_MEDIA_XAUI, 1199 EFX_PHY_MEDIA_CX4, 1200 EFX_PHY_MEDIA_KX4, 1201 EFX_PHY_MEDIA_XFP, 1202 EFX_PHY_MEDIA_SFP_PLUS, 1203 EFX_PHY_MEDIA_BASE_T, 1204 EFX_PHY_MEDIA_QSFP_PLUS, 1205 EFX_PHY_MEDIA_NTYPES 1206 } efx_phy_media_type_t; 1207 1208 /* 1209 * Get the type of medium currently used. If the board has ports for 1210 * modules, a module is present, and we recognise the media type of 1211 * the module, then this will be the media type of the module. 1212 * Otherwise it will be the media type of the port. 1213 */ 1214 LIBEFX_API 1215 extern void 1216 efx_phy_media_type_get( 1217 __in efx_nic_t *enp, 1218 __out efx_phy_media_type_t *typep); 1219 1220 /* 1221 * 2-wire device address of the base information in accordance with SFF-8472 1222 * Diagnostic Monitoring Interface for Optical Transceivers section 1223 * 4 Memory Organization. 1224 */ 1225 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1226 1227 /* 1228 * 2-wire device address of the digital diagnostics monitoring interface 1229 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1230 * Transceivers section 4 Memory Organization. 1231 */ 1232 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1233 1234 /* 1235 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1236 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1237 * Operation. 1238 */ 1239 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1240 1241 /* 1242 * Maximum accessible data offset for PHY module information. 1243 */ 1244 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1245 1246 1247 LIBEFX_API 1248 extern __checkReturn efx_rc_t 1249 efx_phy_module_get_info( 1250 __in efx_nic_t *enp, 1251 __in uint8_t dev_addr, 1252 __in size_t offset, 1253 __in size_t len, 1254 __out_bcount(len) uint8_t *data); 1255 1256 #if EFSYS_OPT_PHY_STATS 1257 1258 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1259 typedef enum efx_phy_stat_e { 1260 EFX_PHY_STAT_OUI, 1261 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1262 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1263 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1264 EFX_PHY_STAT_PMA_PMD_REV_A, 1265 EFX_PHY_STAT_PMA_PMD_REV_B, 1266 EFX_PHY_STAT_PMA_PMD_REV_C, 1267 EFX_PHY_STAT_PMA_PMD_REV_D, 1268 EFX_PHY_STAT_PCS_LINK_UP, 1269 EFX_PHY_STAT_PCS_RX_FAULT, 1270 EFX_PHY_STAT_PCS_TX_FAULT, 1271 EFX_PHY_STAT_PCS_BER, 1272 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1273 EFX_PHY_STAT_PHY_XS_LINK_UP, 1274 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1275 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1276 EFX_PHY_STAT_PHY_XS_ALIGN, 1277 EFX_PHY_STAT_PHY_XS_SYNC_A, 1278 EFX_PHY_STAT_PHY_XS_SYNC_B, 1279 EFX_PHY_STAT_PHY_XS_SYNC_C, 1280 EFX_PHY_STAT_PHY_XS_SYNC_D, 1281 EFX_PHY_STAT_AN_LINK_UP, 1282 EFX_PHY_STAT_AN_MASTER, 1283 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1284 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1285 EFX_PHY_STAT_CL22EXT_LINK_UP, 1286 EFX_PHY_STAT_SNR_A, 1287 EFX_PHY_STAT_SNR_B, 1288 EFX_PHY_STAT_SNR_C, 1289 EFX_PHY_STAT_SNR_D, 1290 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1291 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1292 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1293 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1294 EFX_PHY_STAT_AN_COMPLETE, 1295 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1296 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1297 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1298 EFX_PHY_STAT_PCS_FW_VERSION_0, 1299 EFX_PHY_STAT_PCS_FW_VERSION_1, 1300 EFX_PHY_STAT_PCS_FW_VERSION_2, 1301 EFX_PHY_STAT_PCS_FW_VERSION_3, 1302 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1303 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1304 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1305 EFX_PHY_STAT_PCS_OP_MODE, 1306 EFX_PHY_NSTATS 1307 } efx_phy_stat_t; 1308 1309 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1310 1311 #if EFSYS_OPT_NAMES 1312 1313 LIBEFX_API 1314 extern const char * 1315 efx_phy_stat_name( 1316 __in efx_nic_t *enp, 1317 __in efx_phy_stat_t stat); 1318 1319 #endif /* EFSYS_OPT_NAMES */ 1320 1321 #define EFX_PHY_STATS_SIZE 0x100 1322 1323 LIBEFX_API 1324 extern __checkReturn efx_rc_t 1325 efx_phy_stats_update( 1326 __in efx_nic_t *enp, 1327 __in efsys_mem_t *esmp, 1328 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1329 1330 #endif /* EFSYS_OPT_PHY_STATS */ 1331 1332 1333 #if EFSYS_OPT_BIST 1334 1335 typedef enum efx_bist_type_e { 1336 EFX_BIST_TYPE_UNKNOWN, 1337 EFX_BIST_TYPE_PHY_NORMAL, 1338 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1339 EFX_BIST_TYPE_PHY_CABLE_LONG, 1340 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1341 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1342 EFX_BIST_TYPE_REG, /* Test the register memories */ 1343 EFX_BIST_TYPE_NTYPES, 1344 } efx_bist_type_t; 1345 1346 typedef enum efx_bist_result_e { 1347 EFX_BIST_RESULT_UNKNOWN, 1348 EFX_BIST_RESULT_RUNNING, 1349 EFX_BIST_RESULT_PASSED, 1350 EFX_BIST_RESULT_FAILED, 1351 } efx_bist_result_t; 1352 1353 typedef enum efx_phy_cable_status_e { 1354 EFX_PHY_CABLE_STATUS_OK, 1355 EFX_PHY_CABLE_STATUS_INVALID, 1356 EFX_PHY_CABLE_STATUS_OPEN, 1357 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1358 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1359 EFX_PHY_CABLE_STATUS_BUSY, 1360 } efx_phy_cable_status_t; 1361 1362 typedef enum efx_bist_value_e { 1363 EFX_BIST_PHY_CABLE_LENGTH_A, 1364 EFX_BIST_PHY_CABLE_LENGTH_B, 1365 EFX_BIST_PHY_CABLE_LENGTH_C, 1366 EFX_BIST_PHY_CABLE_LENGTH_D, 1367 EFX_BIST_PHY_CABLE_STATUS_A, 1368 EFX_BIST_PHY_CABLE_STATUS_B, 1369 EFX_BIST_PHY_CABLE_STATUS_C, 1370 EFX_BIST_PHY_CABLE_STATUS_D, 1371 EFX_BIST_FAULT_CODE, 1372 /* 1373 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1374 * response. 1375 */ 1376 EFX_BIST_MEM_TEST, 1377 EFX_BIST_MEM_ADDR, 1378 EFX_BIST_MEM_BUS, 1379 EFX_BIST_MEM_EXPECT, 1380 EFX_BIST_MEM_ACTUAL, 1381 EFX_BIST_MEM_ECC, 1382 EFX_BIST_MEM_ECC_PARITY, 1383 EFX_BIST_MEM_ECC_FATAL, 1384 EFX_BIST_NVALUES, 1385 } efx_bist_value_t; 1386 1387 LIBEFX_API 1388 extern __checkReturn efx_rc_t 1389 efx_bist_enable_offline( 1390 __in efx_nic_t *enp); 1391 1392 LIBEFX_API 1393 extern __checkReturn efx_rc_t 1394 efx_bist_start( 1395 __in efx_nic_t *enp, 1396 __in efx_bist_type_t type); 1397 1398 LIBEFX_API 1399 extern __checkReturn efx_rc_t 1400 efx_bist_poll( 1401 __in efx_nic_t *enp, 1402 __in efx_bist_type_t type, 1403 __out efx_bist_result_t *resultp, 1404 __out_opt uint32_t *value_maskp, 1405 __out_ecount_opt(count) unsigned long *valuesp, 1406 __in size_t count); 1407 1408 LIBEFX_API 1409 extern void 1410 efx_bist_stop( 1411 __in efx_nic_t *enp, 1412 __in efx_bist_type_t type); 1413 1414 #endif /* EFSYS_OPT_BIST */ 1415 1416 #define EFX_FEATURE_IPV6 0x00000001 1417 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1418 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1419 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1420 #define EFX_FEATURE_MCDI 0x00000020 1421 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1422 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1423 #define EFX_FEATURE_TURBO 0x00000100 1424 #define EFX_FEATURE_MCDI_DMA 0x00000200 1425 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1426 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1427 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1428 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1429 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1430 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1431 1432 typedef enum efx_tunnel_protocol_e { 1433 EFX_TUNNEL_PROTOCOL_NONE = 0, 1434 EFX_TUNNEL_PROTOCOL_VXLAN, 1435 EFX_TUNNEL_PROTOCOL_GENEVE, 1436 EFX_TUNNEL_PROTOCOL_NVGRE, 1437 EFX_TUNNEL_NPROTOS 1438 } efx_tunnel_protocol_t; 1439 1440 typedef enum efx_vi_window_shift_e { 1441 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1442 EFX_VI_WINDOW_SHIFT_8K = 13, 1443 EFX_VI_WINDOW_SHIFT_16K = 14, 1444 EFX_VI_WINDOW_SHIFT_64K = 16, 1445 } efx_vi_window_shift_t; 1446 1447 typedef enum efx_nic_dma_mapping_e { 1448 EFX_NIC_DMA_MAPPING_UNKNOWN = 0, 1449 EFX_NIC_DMA_MAPPING_FLAT, 1450 EFX_NIC_DMA_MAPPING_REGIONED, 1451 1452 EFX_NIC_DMA_MAPPING_NTYPES 1453 } efx_nic_dma_mapping_t; 1454 1455 typedef struct efx_nic_cfg_s { 1456 uint32_t enc_board_type; 1457 uint32_t enc_phy_type; 1458 #if EFSYS_OPT_NAMES 1459 char enc_phy_name[21]; 1460 #endif 1461 char enc_phy_revision[21]; 1462 efx_mon_type_t enc_mon_type; 1463 #if EFSYS_OPT_MON_STATS 1464 uint32_t enc_mon_stat_dma_buf_size; 1465 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1466 #endif 1467 unsigned int enc_features; 1468 efx_vi_window_shift_t enc_vi_window_shift; 1469 uint8_t enc_mac_addr[6]; 1470 uint8_t enc_port; /* PHY port number */ 1471 uint32_t enc_intr_vec_base; 1472 uint32_t enc_intr_limit; 1473 uint32_t enc_evq_limit; 1474 uint32_t enc_txq_limit; 1475 uint32_t enc_rxq_limit; 1476 uint32_t enc_evq_max_nevs; 1477 uint32_t enc_evq_min_nevs; 1478 uint32_t enc_rxq_max_ndescs; 1479 uint32_t enc_rxq_min_ndescs; 1480 uint32_t enc_txq_max_ndescs; 1481 uint32_t enc_txq_min_ndescs; 1482 uint32_t enc_buftbl_limit; 1483 uint32_t enc_piobuf_limit; 1484 uint32_t enc_piobuf_size; 1485 uint32_t enc_piobuf_min_alloc_size; 1486 uint32_t enc_evq_timer_quantum_ns; 1487 uint32_t enc_evq_timer_max_us; 1488 uint32_t enc_clk_mult; 1489 uint32_t enc_ev_ew_desc_size; 1490 uint32_t enc_ev_desc_size; 1491 uint32_t enc_rx_desc_size; 1492 uint32_t enc_tx_desc_size; 1493 /* Maximum Rx prefix size if many Rx prefixes are supported */ 1494 uint32_t enc_rx_prefix_size; 1495 uint32_t enc_rx_buf_align_start; 1496 uint32_t enc_rx_buf_align_end; 1497 #if EFSYS_OPT_RX_SCALE 1498 /* 1499 * The limit on how many queues an RSS context in the even spread 1500 * mode can span. When this mode is not supported, the value is 0. 1501 */ 1502 uint32_t enc_rx_scale_even_spread_max_nqueues; 1503 /* 1504 * The limit on how many queues an RSS indirection table can address. 1505 * 1506 * Indirection table entries are offsets relative to a base queue ID. 1507 * This means that the maximum offset has to be less than this value. 1508 */ 1509 uint32_t enc_rx_scale_indirection_max_nqueues; 1510 /* Minimum number of entries an RSS indirection table can contain. */ 1511 uint32_t enc_rx_scale_tbl_min_nentries; 1512 /* Maximum number of entries an RSS indirection table can contain. */ 1513 uint32_t enc_rx_scale_tbl_max_nentries; 1514 uint32_t enc_rx_scale_max_exclusive_contexts; 1515 /* 1516 * Mask of supported hash algorithms. 1517 * Hash algorithm types are used as the bit indices. 1518 */ 1519 uint32_t enc_rx_scale_hash_alg_mask; 1520 /* 1521 * Indicates whether port numbers can be included to the 1522 * input data for hash computation. 1523 */ 1524 boolean_t enc_rx_scale_l4_hash_supported; 1525 boolean_t enc_rx_scale_additional_modes_supported; 1526 /* 1527 * Indicates whether the user can decide how many entries to 1528 * have in the indirection table of an exclusive RSS context. 1529 */ 1530 boolean_t enc_rx_scale_tbl_entry_count_is_selectable; 1531 #endif /* EFSYS_OPT_RX_SCALE */ 1532 #if EFSYS_OPT_LOOPBACK 1533 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1534 #endif /* EFSYS_OPT_LOOPBACK */ 1535 #if EFSYS_OPT_PHY_FLAGS 1536 uint32_t enc_phy_flags_mask; 1537 #endif /* EFSYS_OPT_PHY_FLAGS */ 1538 #if EFSYS_OPT_PHY_LED_CONTROL 1539 uint32_t enc_led_mask; 1540 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1541 #if EFSYS_OPT_PHY_STATS 1542 uint64_t enc_phy_stat_mask; 1543 #endif /* EFSYS_OPT_PHY_STATS */ 1544 #if EFSYS_OPT_MCDI 1545 uint8_t enc_mcdi_mdio_channel; 1546 #if EFSYS_OPT_PHY_STATS 1547 uint32_t enc_mcdi_phy_stat_mask; 1548 #endif /* EFSYS_OPT_PHY_STATS */ 1549 #if EFSYS_OPT_MON_STATS 1550 uint32_t *enc_mcdi_sensor_maskp; 1551 uint32_t enc_mcdi_sensor_mask_size; 1552 #endif /* EFSYS_OPT_MON_STATS */ 1553 #endif /* EFSYS_OPT_MCDI */ 1554 #if EFSYS_OPT_BIST 1555 uint32_t enc_bist_mask; 1556 #endif /* EFSYS_OPT_BIST */ 1557 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1558 efx_pcie_interface_t enc_intf; 1559 uint32_t enc_pf; 1560 uint32_t enc_vf; 1561 uint32_t enc_privilege_mask; 1562 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1563 boolean_t enc_evq_init_done_ev_supported; 1564 boolean_t enc_bug26807_workaround; 1565 boolean_t enc_bug35388_workaround; 1566 boolean_t enc_bug41750_workaround; 1567 boolean_t enc_bug61265_workaround; 1568 boolean_t enc_bug61297_workaround; 1569 boolean_t enc_rx_batching_enabled; 1570 /* Maximum number of descriptors completed in an rx event. */ 1571 uint32_t enc_rx_batch_max; 1572 /* Number of rx descriptors the hardware requires for a push. */ 1573 uint32_t enc_rx_push_align; 1574 /* Maximum amount of data in DMA descriptor */ 1575 uint32_t enc_tx_dma_desc_size_max; 1576 /* 1577 * Boundary which DMA descriptor data must not cross or 0 if no 1578 * limitation. 1579 */ 1580 uint32_t enc_tx_dma_desc_boundary; 1581 /* 1582 * Maximum number of bytes into the packet the TCP header can start for 1583 * the hardware to apply TSO packet edits. 1584 */ 1585 uint32_t enc_tx_tso_tcp_header_offset_limit; 1586 /* Maximum number of header DMA descriptors per TSO transaction. */ 1587 uint32_t enc_tx_tso_max_header_ndescs; 1588 /* Maximum header length acceptable by TSO transaction. */ 1589 uint32_t enc_tx_tso_max_header_length; 1590 /* Maximum number of payload DMA descriptors per TSO transaction. */ 1591 uint32_t enc_tx_tso_max_payload_ndescs; 1592 /* Maximum payload length per TSO transaction. */ 1593 uint32_t enc_tx_tso_max_payload_length; 1594 /* Maximum number of frames to be generated per TSO transaction. */ 1595 uint32_t enc_tx_tso_max_nframes; 1596 boolean_t enc_fw_assisted_tso_enabled; 1597 boolean_t enc_fw_assisted_tso_v2_enabled; 1598 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1599 boolean_t enc_tso_v3_enabled; 1600 /* Number of TSO contexts on the NIC (FATSOv2) */ 1601 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1602 boolean_t enc_hw_tx_insert_vlan_enabled; 1603 /* Number of PFs on the NIC */ 1604 uint32_t enc_hw_pf_count; 1605 /* Datapath firmware vadapter/vport/vswitch support */ 1606 boolean_t enc_datapath_cap_evb; 1607 /* Datapath firmware vport reconfigure support */ 1608 boolean_t enc_vport_reconfigure_supported; 1609 boolean_t enc_rx_disable_scatter_supported; 1610 /* Maximum number of Rx scatter segments supported by HW */ 1611 uint32_t enc_rx_scatter_max; 1612 boolean_t enc_allow_set_mac_with_installed_filters; 1613 boolean_t enc_enhanced_set_mac_supported; 1614 boolean_t enc_init_evq_v2_supported; 1615 boolean_t enc_init_evq_extended_width_supported; 1616 boolean_t enc_no_cont_ev_mode_supported; 1617 boolean_t enc_init_rxq_with_buffer_size; 1618 boolean_t enc_rx_packed_stream_supported; 1619 boolean_t enc_rx_var_packed_stream_supported; 1620 boolean_t enc_rx_es_super_buffer_supported; 1621 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1622 boolean_t enc_pm_and_rxdp_counters; 1623 boolean_t enc_mac_stats_40g_tx_size_bins; 1624 uint32_t enc_tunnel_encapsulations_supported; 1625 /* 1626 * NIC global maximum for unique UDP tunnel ports shared by all 1627 * functions. 1628 */ 1629 uint32_t enc_tunnel_config_udp_entries_max; 1630 /* External port identifier */ 1631 uint8_t enc_external_port; 1632 uint32_t enc_mcdi_max_payload_length; 1633 /* VPD may be per-PF or global */ 1634 boolean_t enc_vpd_is_global; 1635 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1636 uint32_t enc_required_pcie_bandwidth_mbps; 1637 uint32_t enc_max_pcie_link_gen; 1638 /* Firmware verifies integrity of NVRAM updates */ 1639 boolean_t enc_nvram_update_verify_result_supported; 1640 /* Firmware supports polled NVRAM updates on select partitions */ 1641 boolean_t enc_nvram_update_poll_verify_result_supported; 1642 /* Firmware accepts updates via the BUNDLE partition */ 1643 boolean_t enc_nvram_bundle_update_supported; 1644 /* Firmware support for extended MAC_STATS buffer */ 1645 uint32_t enc_mac_stats_nstats; 1646 boolean_t enc_fec_counters; 1647 boolean_t enc_hlb_counters; 1648 /* NIC support for Match-Action Engine (MAE). */ 1649 boolean_t enc_mae_supported; 1650 /* 1651 * NIC is privileged, i.e. it is the MAE admin. 1652 * Only privileged MAE clients can manage MAE flow rules, 1653 * for example, modify, count and route traffic to selected 1654 * destination (a MAE client or network port). 1655 */ 1656 boolean_t enc_mae_admin; 1657 /* NIC support for MAE action set v2 features. */ 1658 boolean_t enc_mae_aset_v2_supported; 1659 /* Firmware support for "FLAG" and "MARK" filter actions */ 1660 boolean_t enc_filter_action_flag_supported; 1661 boolean_t enc_filter_action_mark_supported; 1662 uint32_t enc_filter_action_mark_max; 1663 /* Port assigned to this PCI function */ 1664 uint32_t enc_assigned_port; 1665 /* NIC DMA mapping type */ 1666 efx_nic_dma_mapping_t enc_dma_mapping; 1667 } efx_nic_cfg_t; 1668 1669 #define EFX_PCI_VF_INVALID 0xffff 1670 1671 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ 1672 ((configp)->evc_function == EFX_PCI_VF_INVALID) 1673 1674 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID) 1675 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID) 1676 1677 #define EFX_PCI_FUNCTION(_encp) \ 1678 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1679 1680 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1681 1682 LIBEFX_API 1683 extern const efx_nic_cfg_t * 1684 efx_nic_cfg_get( 1685 __in const efx_nic_t *enp); 1686 1687 /* RxDPCPU firmware id values by which FW variant can be identified */ 1688 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1689 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1690 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1691 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1692 #define EFX_RXDP_DPDK_FW_ID 0x6 1693 1694 typedef struct efx_nic_fw_info_s { 1695 /* Basic FW version information */ 1696 uint16_t enfi_mc_fw_version[4]; 1697 /* 1698 * If datapath capabilities can be detected, 1699 * additional FW information is to be shown 1700 */ 1701 boolean_t enfi_dpcpu_fw_ids_valid; 1702 /* Rx and Tx datapath CPU FW IDs */ 1703 uint16_t enfi_rx_dpcpu_fw_id; 1704 uint16_t enfi_tx_dpcpu_fw_id; 1705 } efx_nic_fw_info_t; 1706 1707 LIBEFX_API 1708 extern __checkReturn efx_rc_t 1709 efx_nic_get_fw_version( 1710 __in efx_nic_t *enp, 1711 __out efx_nic_fw_info_t *enfip); 1712 1713 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64) 1714 #define EFX_NIC_BOARD_INFO_NAME_LEN (16) 1715 1716 typedef struct efx_nic_board_info_s { 1717 /* The following two fields are NUL-terminated ASCII strings. */ 1718 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN]; 1719 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN]; 1720 uint32_t enbi_revision; 1721 } efx_nic_board_info_t; 1722 1723 LIBEFX_API 1724 extern __checkReturn efx_rc_t 1725 efx_nic_get_board_info( 1726 __in efx_nic_t *enp, 1727 __out efx_nic_board_info_t *board_infop); 1728 1729 /* Driver resource limits (minimum required/maximum usable). */ 1730 typedef struct efx_drv_limits_s { 1731 uint32_t edl_min_evq_count; 1732 uint32_t edl_max_evq_count; 1733 1734 uint32_t edl_min_rxq_count; 1735 uint32_t edl_max_rxq_count; 1736 1737 uint32_t edl_min_txq_count; 1738 uint32_t edl_max_txq_count; 1739 1740 /* PIO blocks (sub-allocated from piobuf) */ 1741 uint32_t edl_min_pio_alloc_size; 1742 uint32_t edl_max_pio_alloc_count; 1743 } efx_drv_limits_t; 1744 1745 LIBEFX_API 1746 extern __checkReturn efx_rc_t 1747 efx_nic_set_drv_limits( 1748 __inout efx_nic_t *enp, 1749 __in efx_drv_limits_t *edlp); 1750 1751 /* 1752 * Register the OS driver version string for management agents 1753 * (e.g. via NC-SI). The content length is provided (i.e. no 1754 * NUL terminator). Use length 0 to indicate no version string 1755 * should be advertised. It is valid to set the version string 1756 * only before efx_nic_probe() is called. 1757 */ 1758 LIBEFX_API 1759 extern __checkReturn efx_rc_t 1760 efx_nic_set_drv_version( 1761 __inout efx_nic_t *enp, 1762 __in_ecount(length) char const *verp, 1763 __in size_t length); 1764 1765 typedef enum efx_nic_region_e { 1766 EFX_REGION_VI, /* Memory BAR UC mapping */ 1767 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1768 } efx_nic_region_t; 1769 1770 LIBEFX_API 1771 extern __checkReturn efx_rc_t 1772 efx_nic_get_bar_region( 1773 __in efx_nic_t *enp, 1774 __in efx_nic_region_t region, 1775 __out uint32_t *offsetp, 1776 __out size_t *sizep); 1777 1778 LIBEFX_API 1779 extern __checkReturn efx_rc_t 1780 efx_nic_get_vi_pool( 1781 __in efx_nic_t *enp, 1782 __out uint32_t *evq_countp, 1783 __out uint32_t *rxq_countp, 1784 __out uint32_t *txq_countp); 1785 1786 1787 #if EFSYS_OPT_VPD 1788 1789 typedef enum efx_vpd_tag_e { 1790 EFX_VPD_ID = 0x02, 1791 EFX_VPD_END = 0x0f, 1792 EFX_VPD_RO = 0x10, 1793 EFX_VPD_RW = 0x11, 1794 } efx_vpd_tag_t; 1795 1796 typedef uint16_t efx_vpd_keyword_t; 1797 1798 typedef struct efx_vpd_value_s { 1799 efx_vpd_tag_t evv_tag; 1800 efx_vpd_keyword_t evv_keyword; 1801 uint8_t evv_length; 1802 uint8_t evv_value[0x100]; 1803 } efx_vpd_value_t; 1804 1805 1806 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1807 1808 LIBEFX_API 1809 extern __checkReturn efx_rc_t 1810 efx_vpd_init( 1811 __in efx_nic_t *enp); 1812 1813 LIBEFX_API 1814 extern __checkReturn efx_rc_t 1815 efx_vpd_size( 1816 __in efx_nic_t *enp, 1817 __out size_t *sizep); 1818 1819 LIBEFX_API 1820 extern __checkReturn efx_rc_t 1821 efx_vpd_read( 1822 __in efx_nic_t *enp, 1823 __out_bcount(size) caddr_t data, 1824 __in size_t size); 1825 1826 LIBEFX_API 1827 extern __checkReturn efx_rc_t 1828 efx_vpd_verify( 1829 __in efx_nic_t *enp, 1830 __in_bcount(size) caddr_t data, 1831 __in size_t size); 1832 1833 LIBEFX_API 1834 extern __checkReturn efx_rc_t 1835 efx_vpd_reinit( 1836 __in efx_nic_t *enp, 1837 __in_bcount(size) caddr_t data, 1838 __in size_t size); 1839 1840 LIBEFX_API 1841 extern __checkReturn efx_rc_t 1842 efx_vpd_get( 1843 __in efx_nic_t *enp, 1844 __in_bcount(size) caddr_t data, 1845 __in size_t size, 1846 __inout efx_vpd_value_t *evvp); 1847 1848 LIBEFX_API 1849 extern __checkReturn efx_rc_t 1850 efx_vpd_set( 1851 __in efx_nic_t *enp, 1852 __inout_bcount(size) caddr_t data, 1853 __in size_t size, 1854 __in efx_vpd_value_t *evvp); 1855 1856 LIBEFX_API 1857 extern __checkReturn efx_rc_t 1858 efx_vpd_next( 1859 __in efx_nic_t *enp, 1860 __inout_bcount(size) caddr_t data, 1861 __in size_t size, 1862 __out efx_vpd_value_t *evvp, 1863 __inout unsigned int *contp); 1864 1865 LIBEFX_API 1866 extern __checkReturn efx_rc_t 1867 efx_vpd_write( 1868 __in efx_nic_t *enp, 1869 __in_bcount(size) caddr_t data, 1870 __in size_t size); 1871 1872 LIBEFX_API 1873 extern void 1874 efx_vpd_fini( 1875 __in efx_nic_t *enp); 1876 1877 #endif /* EFSYS_OPT_VPD */ 1878 1879 /* NVRAM */ 1880 1881 #if EFSYS_OPT_NVRAM 1882 1883 typedef enum efx_nvram_type_e { 1884 EFX_NVRAM_INVALID = 0, 1885 EFX_NVRAM_BOOTROM, 1886 EFX_NVRAM_BOOTROM_CFG, 1887 EFX_NVRAM_MC_FIRMWARE, 1888 EFX_NVRAM_MC_GOLDEN, 1889 EFX_NVRAM_PHY, 1890 EFX_NVRAM_NULLPHY, 1891 EFX_NVRAM_FPGA, 1892 EFX_NVRAM_FCFW, 1893 EFX_NVRAM_CPLD, 1894 EFX_NVRAM_FPGA_BACKUP, 1895 EFX_NVRAM_DYNAMIC_CFG, 1896 EFX_NVRAM_LICENSE, 1897 EFX_NVRAM_UEFIROM, 1898 EFX_NVRAM_MUM_FIRMWARE, 1899 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1900 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1901 EFX_NVRAM_BUNDLE, 1902 EFX_NVRAM_BUNDLE_METADATA, 1903 EFX_NVRAM_NTYPES, 1904 } efx_nvram_type_t; 1905 1906 typedef struct efx_nvram_info_s { 1907 uint32_t eni_flags; 1908 uint32_t eni_partn_size; 1909 uint32_t eni_address; 1910 uint32_t eni_erase_size; 1911 uint32_t eni_write_size; 1912 } efx_nvram_info_t; 1913 1914 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) 1915 1916 LIBEFX_API 1917 extern __checkReturn efx_rc_t 1918 efx_nvram_init( 1919 __in efx_nic_t *enp); 1920 1921 #if EFSYS_OPT_DIAG 1922 1923 LIBEFX_API 1924 extern __checkReturn efx_rc_t 1925 efx_nvram_test( 1926 __in efx_nic_t *enp); 1927 1928 #endif /* EFSYS_OPT_DIAG */ 1929 1930 LIBEFX_API 1931 extern __checkReturn efx_rc_t 1932 efx_nvram_size( 1933 __in efx_nic_t *enp, 1934 __in efx_nvram_type_t type, 1935 __out size_t *sizep); 1936 1937 LIBEFX_API 1938 extern __checkReturn efx_rc_t 1939 efx_nvram_info( 1940 __in efx_nic_t *enp, 1941 __in efx_nvram_type_t type, 1942 __out efx_nvram_info_t *enip); 1943 1944 LIBEFX_API 1945 extern __checkReturn efx_rc_t 1946 efx_nvram_rw_start( 1947 __in efx_nic_t *enp, 1948 __in efx_nvram_type_t type, 1949 __out_opt size_t *pref_chunkp); 1950 1951 LIBEFX_API 1952 extern __checkReturn efx_rc_t 1953 efx_nvram_rw_finish( 1954 __in efx_nic_t *enp, 1955 __in efx_nvram_type_t type, 1956 __out_opt uint32_t *verify_resultp); 1957 1958 LIBEFX_API 1959 extern __checkReturn efx_rc_t 1960 efx_nvram_get_version( 1961 __in efx_nic_t *enp, 1962 __in efx_nvram_type_t type, 1963 __out uint32_t *subtypep, 1964 __out_ecount(4) uint16_t version[4]); 1965 1966 LIBEFX_API 1967 extern __checkReturn efx_rc_t 1968 efx_nvram_read_chunk( 1969 __in efx_nic_t *enp, 1970 __in efx_nvram_type_t type, 1971 __in unsigned int offset, 1972 __out_bcount(size) caddr_t data, 1973 __in size_t size); 1974 1975 LIBEFX_API 1976 extern __checkReturn efx_rc_t 1977 efx_nvram_read_backup( 1978 __in efx_nic_t *enp, 1979 __in efx_nvram_type_t type, 1980 __in unsigned int offset, 1981 __out_bcount(size) caddr_t data, 1982 __in size_t size); 1983 1984 LIBEFX_API 1985 extern __checkReturn efx_rc_t 1986 efx_nvram_set_version( 1987 __in efx_nic_t *enp, 1988 __in efx_nvram_type_t type, 1989 __in_ecount(4) uint16_t version[4]); 1990 1991 LIBEFX_API 1992 extern __checkReturn efx_rc_t 1993 efx_nvram_validate( 1994 __in efx_nic_t *enp, 1995 __in efx_nvram_type_t type, 1996 __in_bcount(partn_size) caddr_t partn_data, 1997 __in size_t partn_size); 1998 1999 LIBEFX_API 2000 extern __checkReturn efx_rc_t 2001 efx_nvram_erase( 2002 __in efx_nic_t *enp, 2003 __in efx_nvram_type_t type); 2004 2005 LIBEFX_API 2006 extern __checkReturn efx_rc_t 2007 efx_nvram_write_chunk( 2008 __in efx_nic_t *enp, 2009 __in efx_nvram_type_t type, 2010 __in unsigned int offset, 2011 __in_bcount(size) caddr_t data, 2012 __in size_t size); 2013 2014 LIBEFX_API 2015 extern void 2016 efx_nvram_fini( 2017 __in efx_nic_t *enp); 2018 2019 #endif /* EFSYS_OPT_NVRAM */ 2020 2021 #if EFSYS_OPT_BOOTCFG 2022 2023 /* Report size and offset of bootcfg sector in NVRAM partition. */ 2024 LIBEFX_API 2025 extern __checkReturn efx_rc_t 2026 efx_bootcfg_sector_info( 2027 __in efx_nic_t *enp, 2028 __in uint32_t pf, 2029 __out_opt uint32_t *sector_countp, 2030 __out size_t *offsetp, 2031 __out size_t *max_sizep); 2032 2033 /* 2034 * Copy bootcfg sector data to a target buffer which may differ in size. 2035 * Optionally corrects format errors in source buffer. 2036 */ 2037 LIBEFX_API 2038 extern efx_rc_t 2039 efx_bootcfg_copy_sector( 2040 __in efx_nic_t *enp, 2041 __inout_bcount(sector_length) 2042 uint8_t *sector, 2043 __in size_t sector_length, 2044 __out_bcount(data_size) uint8_t *data, 2045 __in size_t data_size, 2046 __in boolean_t handle_format_errors); 2047 2048 LIBEFX_API 2049 extern efx_rc_t 2050 efx_bootcfg_read( 2051 __in efx_nic_t *enp, 2052 __out_bcount(size) uint8_t *data, 2053 __in size_t size); 2054 2055 LIBEFX_API 2056 extern efx_rc_t 2057 efx_bootcfg_write( 2058 __in efx_nic_t *enp, 2059 __in_bcount(size) uint8_t *data, 2060 __in size_t size); 2061 2062 2063 /* 2064 * Processing routines for buffers arranged in the DHCP/BOOTP option format 2065 * (see https://tools.ietf.org/html/rfc1533) 2066 * 2067 * Summarising the format: the buffer is a sequence of options. All options 2068 * begin with a tag octet, which uniquely identifies the option. Fixed- 2069 * length options without data consist of only a tag octet. Only options PAD 2070 * (0) and END (255) are fixed length. All other options are variable-length 2071 * with a length octet following the tag octet. The value of the length 2072 * octet does not include the two octets specifying the tag and length. The 2073 * length octet is followed by "length" octets of data. 2074 * 2075 * Option data may be a sequence of sub-options in the same format. The data 2076 * content of the encapsulating option is one or more encapsulated sub-options, 2077 * with no terminating END tag is required. 2078 * 2079 * To be valid, the top-level sequence of options should be terminated by an 2080 * END tag. The buffer should be padded with the PAD byte. 2081 * 2082 * When stored to NVRAM, the DHCP option format buffer is preceded by a 2083 * checksum octet. The full buffer (including after the END tag) contributes 2084 * to the checksum, hence the need to fill the buffer to the end with PAD. 2085 */ 2086 2087 #define EFX_DHCP_END ((uint8_t)0xff) 2088 #define EFX_DHCP_PAD ((uint8_t)0) 2089 2090 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 2091 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 2092 2093 LIBEFX_API 2094 extern __checkReturn uint8_t 2095 efx_dhcp_csum( 2096 __in_bcount(size) uint8_t const *data, 2097 __in size_t size); 2098 2099 LIBEFX_API 2100 extern __checkReturn efx_rc_t 2101 efx_dhcp_verify( 2102 __in_bcount(size) uint8_t const *data, 2103 __in size_t size, 2104 __out_opt size_t *usedp); 2105 2106 LIBEFX_API 2107 extern __checkReturn efx_rc_t 2108 efx_dhcp_find_tag( 2109 __in_bcount(buffer_length) uint8_t *bufferp, 2110 __in size_t buffer_length, 2111 __in uint16_t opt, 2112 __deref_out uint8_t **valuepp, 2113 __out size_t *value_lengthp); 2114 2115 LIBEFX_API 2116 extern __checkReturn efx_rc_t 2117 efx_dhcp_find_end( 2118 __in_bcount(buffer_length) uint8_t *bufferp, 2119 __in size_t buffer_length, 2120 __deref_out uint8_t **endpp); 2121 2122 2123 LIBEFX_API 2124 extern __checkReturn efx_rc_t 2125 efx_dhcp_delete_tag( 2126 __inout_bcount(buffer_length) uint8_t *bufferp, 2127 __in size_t buffer_length, 2128 __in uint16_t opt); 2129 2130 LIBEFX_API 2131 extern __checkReturn efx_rc_t 2132 efx_dhcp_add_tag( 2133 __inout_bcount(buffer_length) uint8_t *bufferp, 2134 __in size_t buffer_length, 2135 __in uint16_t opt, 2136 __in_bcount_opt(value_length) uint8_t *valuep, 2137 __in size_t value_length); 2138 2139 LIBEFX_API 2140 extern __checkReturn efx_rc_t 2141 efx_dhcp_update_tag( 2142 __inout_bcount(buffer_length) uint8_t *bufferp, 2143 __in size_t buffer_length, 2144 __in uint16_t opt, 2145 __in uint8_t *value_locationp, 2146 __in_bcount_opt(value_length) uint8_t *valuep, 2147 __in size_t value_length); 2148 2149 2150 #endif /* EFSYS_OPT_BOOTCFG */ 2151 2152 #if EFSYS_OPT_IMAGE_LAYOUT 2153 2154 #include "ef10_signed_image_layout.h" 2155 2156 /* 2157 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 2158 * 2159 * NOTE: 2160 * The image header format is extensible. However, older drivers require an 2161 * exact match of image header version and header length when validating and 2162 * writing firmware images. 2163 * 2164 * To avoid breaking backward compatibility, we use the upper bits of the 2165 * controller version fields to contain an extra version number used for 2166 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 2167 * version). See bug39254 and SF-102785-PS for details. 2168 */ 2169 typedef struct efx_image_header_s { 2170 uint32_t eih_magic; 2171 uint32_t eih_version; 2172 uint32_t eih_type; 2173 uint32_t eih_subtype; 2174 uint32_t eih_code_size; 2175 uint32_t eih_size; 2176 union { 2177 uint32_t eih_controller_version_min; 2178 struct { 2179 uint16_t eih_controller_version_min_short; 2180 uint8_t eih_extra_version_a; 2181 uint8_t eih_extra_version_b; 2182 }; 2183 }; 2184 union { 2185 uint32_t eih_controller_version_max; 2186 struct { 2187 uint16_t eih_controller_version_max_short; 2188 uint8_t eih_extra_version_c; 2189 uint8_t eih_extra_version_d; 2190 }; 2191 }; 2192 uint16_t eih_code_version_a; 2193 uint16_t eih_code_version_b; 2194 uint16_t eih_code_version_c; 2195 uint16_t eih_code_version_d; 2196 } efx_image_header_t; 2197 2198 #define EFX_IMAGE_HEADER_SIZE (40) 2199 #define EFX_IMAGE_HEADER_VERSION (4) 2200 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 2201 2202 2203 typedef struct efx_image_trailer_s { 2204 uint32_t eit_crc; 2205 } efx_image_trailer_t; 2206 2207 #define EFX_IMAGE_TRAILER_SIZE (4) 2208 2209 typedef enum efx_image_format_e { 2210 EFX_IMAGE_FORMAT_NO_IMAGE, 2211 EFX_IMAGE_FORMAT_INVALID, 2212 EFX_IMAGE_FORMAT_UNSIGNED, 2213 EFX_IMAGE_FORMAT_SIGNED, 2214 EFX_IMAGE_FORMAT_SIGNED_PACKAGE 2215 } efx_image_format_t; 2216 2217 typedef struct efx_image_info_s { 2218 efx_image_format_t eii_format; 2219 uint8_t * eii_imagep; 2220 size_t eii_image_size; 2221 efx_image_header_t * eii_headerp; 2222 } efx_image_info_t; 2223 2224 LIBEFX_API 2225 extern __checkReturn efx_rc_t 2226 efx_check_reflash_image( 2227 __in void *bufferp, 2228 __in uint32_t buffer_size, 2229 __out efx_image_info_t *infop); 2230 2231 LIBEFX_API 2232 extern __checkReturn efx_rc_t 2233 efx_build_signed_image_write_buffer( 2234 __out_bcount(buffer_size) 2235 uint8_t *bufferp, 2236 __in uint32_t buffer_size, 2237 __in efx_image_info_t *infop, 2238 __out efx_image_header_t **headerpp); 2239 2240 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 2241 2242 #if EFSYS_OPT_DIAG 2243 2244 typedef enum efx_pattern_type_t { 2245 EFX_PATTERN_BYTE_INCREMENT = 0, 2246 EFX_PATTERN_ALL_THE_SAME, 2247 EFX_PATTERN_BIT_ALTERNATE, 2248 EFX_PATTERN_BYTE_ALTERNATE, 2249 EFX_PATTERN_BYTE_CHANGING, 2250 EFX_PATTERN_BIT_SWEEP, 2251 EFX_PATTERN_NTYPES 2252 } efx_pattern_type_t; 2253 2254 typedef void 2255 (*efx_sram_pattern_fn_t)( 2256 __in size_t row, 2257 __in boolean_t negate, 2258 __out efx_qword_t *eqp); 2259 2260 LIBEFX_API 2261 extern __checkReturn efx_rc_t 2262 efx_sram_test( 2263 __in efx_nic_t *enp, 2264 __in efx_pattern_type_t type); 2265 2266 #endif /* EFSYS_OPT_DIAG */ 2267 2268 LIBEFX_API 2269 extern __checkReturn efx_rc_t 2270 efx_sram_buf_tbl_set( 2271 __in efx_nic_t *enp, 2272 __in uint32_t id, 2273 __in efsys_mem_t *esmp, 2274 __in size_t n); 2275 2276 LIBEFX_API 2277 extern void 2278 efx_sram_buf_tbl_clear( 2279 __in efx_nic_t *enp, 2280 __in uint32_t id, 2281 __in size_t n); 2282 2283 #define EFX_BUF_TBL_SIZE 0x20000 2284 2285 #define EFX_BUF_SIZE 4096 2286 2287 /* EV */ 2288 2289 typedef struct efx_evq_s efx_evq_t; 2290 2291 #if EFSYS_OPT_QSTATS 2292 2293 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ 2294 typedef enum efx_ev_qstat_e { 2295 EV_ALL, 2296 EV_RX, 2297 EV_RX_OK, 2298 EV_RX_FRM_TRUNC, 2299 EV_RX_TOBE_DISC, 2300 EV_RX_PAUSE_FRM_ERR, 2301 EV_RX_BUF_OWNER_ID_ERR, 2302 EV_RX_IPV4_HDR_CHKSUM_ERR, 2303 EV_RX_TCP_UDP_CHKSUM_ERR, 2304 EV_RX_ETH_CRC_ERR, 2305 EV_RX_IP_FRAG_ERR, 2306 EV_RX_MCAST_PKT, 2307 EV_RX_MCAST_HASH_MATCH, 2308 EV_RX_TCP_IPV4, 2309 EV_RX_TCP_IPV6, 2310 EV_RX_UDP_IPV4, 2311 EV_RX_UDP_IPV6, 2312 EV_RX_OTHER_IPV4, 2313 EV_RX_OTHER_IPV6, 2314 EV_RX_NON_IP, 2315 EV_RX_BATCH, 2316 EV_TX, 2317 EV_TX_WQ_FF_FULL, 2318 EV_TX_PKT_ERR, 2319 EV_TX_PKT_TOO_BIG, 2320 EV_TX_UNEXPECTED, 2321 EV_GLOBAL, 2322 EV_GLOBAL_MNT, 2323 EV_DRIVER, 2324 EV_DRIVER_SRM_UPD_DONE, 2325 EV_DRIVER_TX_DESCQ_FLS_DONE, 2326 EV_DRIVER_RX_DESCQ_FLS_DONE, 2327 EV_DRIVER_RX_DESCQ_FLS_FAILED, 2328 EV_DRIVER_RX_DSC_ERROR, 2329 EV_DRIVER_TX_DSC_ERROR, 2330 EV_DRV_GEN, 2331 EV_MCDI_RESPONSE, 2332 EV_RX_PARSE_INCOMPLETE, 2333 EV_NQSTATS 2334 } efx_ev_qstat_t; 2335 2336 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2337 2338 #endif /* EFSYS_OPT_QSTATS */ 2339 2340 LIBEFX_API 2341 extern __checkReturn efx_rc_t 2342 efx_ev_init( 2343 __in efx_nic_t *enp); 2344 2345 LIBEFX_API 2346 extern void 2347 efx_ev_fini( 2348 __in efx_nic_t *enp); 2349 2350 LIBEFX_API 2351 extern __checkReturn size_t 2352 efx_evq_size( 2353 __in const efx_nic_t *enp, 2354 __in unsigned int ndescs, 2355 __in uint32_t flags); 2356 2357 LIBEFX_API 2358 extern __checkReturn unsigned int 2359 efx_evq_nbufs( 2360 __in const efx_nic_t *enp, 2361 __in unsigned int ndescs, 2362 __in uint32_t flags); 2363 2364 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2365 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2366 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2367 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2368 2369 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2370 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2371 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2372 2373 /* 2374 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more 2375 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in 2376 * NO_CONT_EV mode". 2377 * 2378 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, 2379 * which is the case when an event queue is set to THROUGHPUT mode. 2380 */ 2381 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) 2382 2383 /* Configure EVQ for extended width events (EF100 only) */ 2384 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20) 2385 2386 2387 LIBEFX_API 2388 extern __checkReturn efx_rc_t 2389 efx_ev_qcreate( 2390 __in efx_nic_t *enp, 2391 __in unsigned int index, 2392 __in efsys_mem_t *esmp, 2393 __in size_t ndescs, 2394 __in uint32_t id, 2395 __in uint32_t us, 2396 __in uint32_t flags, 2397 __deref_out efx_evq_t **eepp); 2398 2399 LIBEFX_API 2400 extern __checkReturn efx_rc_t 2401 efx_ev_qcreate_irq( 2402 __in efx_nic_t *enp, 2403 __in unsigned int index, 2404 __in efsys_mem_t *esmp, 2405 __in size_t ndescs, 2406 __in uint32_t id, 2407 __in uint32_t us, 2408 __in uint32_t flags, 2409 __in uint32_t irq, 2410 __deref_out efx_evq_t **eepp); 2411 2412 LIBEFX_API 2413 extern void 2414 efx_ev_qpost( 2415 __in efx_evq_t *eep, 2416 __in uint16_t data); 2417 2418 typedef __checkReturn boolean_t 2419 (*efx_initialized_ev_t)( 2420 __in_opt void *arg); 2421 2422 #define EFX_PKT_UNICAST 0x0004 2423 #define EFX_PKT_START 0x0008 2424 2425 #define EFX_PKT_VLAN_TAGGED 0x0010 2426 #define EFX_CKSUM_TCPUDP 0x0020 2427 #define EFX_CKSUM_IPV4 0x0040 2428 #define EFX_PKT_CONT 0x0080 2429 2430 #define EFX_CHECK_VLAN 0x0100 2431 #define EFX_PKT_TCP 0x0200 2432 #define EFX_PKT_UDP 0x0400 2433 #define EFX_PKT_IPV4 0x0800 2434 2435 #define EFX_PKT_IPV6 0x1000 2436 #define EFX_PKT_PREFIX_LEN 0x2000 2437 #define EFX_ADDR_MISMATCH 0x4000 2438 #define EFX_DISCARD 0x8000 2439 2440 /* 2441 * The following flags are used only for packed stream 2442 * mode. The values for the flags are reused to fit into 16 bit, 2443 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2444 * packed stream mode 2445 */ 2446 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2447 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2448 2449 2450 #define EFX_EV_RX_NLABELS 32 2451 #define EFX_EV_TX_NLABELS 32 2452 2453 typedef __checkReturn boolean_t 2454 (*efx_rx_ev_t)( 2455 __in_opt void *arg, 2456 __in uint32_t label, 2457 __in uint32_t id, 2458 __in uint32_t size, 2459 __in uint16_t flags); 2460 2461 typedef __checkReturn boolean_t 2462 (*efx_rx_packets_ev_t)( 2463 __in_opt void *arg, 2464 __in uint32_t label, 2465 __in unsigned int num_packets, 2466 __in uint32_t flags); 2467 2468 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2469 2470 /* 2471 * Packed stream mode is documented in SF-112241-TC. 2472 * The general idea is that, instead of putting each incoming 2473 * packet into a separate buffer which is specified in a RX 2474 * descriptor, a large buffer is provided to the hardware and 2475 * packets are put there in a continuous stream. 2476 * The main advantage of such an approach is that RX queue refilling 2477 * happens much less frequently. 2478 * 2479 * Equal stride packed stream mode is documented in SF-119419-TC. 2480 * The general idea is to utilize advantages of the packed stream, 2481 * but avoid indirection in packets representation. 2482 * The main advantage of such an approach is that RX queue refilling 2483 * happens much less frequently and packets buffers are independent 2484 * from upper layers point of view. 2485 */ 2486 2487 typedef __checkReturn boolean_t 2488 (*efx_rx_ps_ev_t)( 2489 __in_opt void *arg, 2490 __in uint32_t label, 2491 __in uint32_t id, 2492 __in uint32_t pkt_count, 2493 __in uint16_t flags); 2494 2495 #endif 2496 2497 typedef __checkReturn boolean_t 2498 (*efx_tx_ev_t)( 2499 __in_opt void *arg, 2500 __in uint32_t label, 2501 __in uint32_t id); 2502 2503 typedef __checkReturn boolean_t 2504 (*efx_tx_ndescs_ev_t)( 2505 __in_opt void *arg, 2506 __in uint32_t label, 2507 __in unsigned int ndescs); 2508 2509 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2510 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2511 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2512 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2513 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2514 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2515 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2516 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2517 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2518 2519 typedef __checkReturn boolean_t 2520 (*efx_exception_ev_t)( 2521 __in_opt void *arg, 2522 __in uint32_t label, 2523 __in uint32_t data); 2524 2525 typedef __checkReturn boolean_t 2526 (*efx_rxq_flush_done_ev_t)( 2527 __in_opt void *arg, 2528 __in uint32_t rxq_index); 2529 2530 typedef __checkReturn boolean_t 2531 (*efx_rxq_flush_failed_ev_t)( 2532 __in_opt void *arg, 2533 __in uint32_t rxq_index); 2534 2535 typedef __checkReturn boolean_t 2536 (*efx_txq_flush_done_ev_t)( 2537 __in_opt void *arg, 2538 __in uint32_t txq_index); 2539 2540 typedef __checkReturn boolean_t 2541 (*efx_software_ev_t)( 2542 __in_opt void *arg, 2543 __in uint16_t magic); 2544 2545 typedef __checkReturn boolean_t 2546 (*efx_sram_ev_t)( 2547 __in_opt void *arg, 2548 __in uint32_t code); 2549 2550 #define EFX_SRAM_CLEAR 0 2551 #define EFX_SRAM_UPDATE 1 2552 #define EFX_SRAM_ILLEGAL_CLEAR 2 2553 2554 typedef __checkReturn boolean_t 2555 (*efx_wake_up_ev_t)( 2556 __in_opt void *arg, 2557 __in uint32_t label); 2558 2559 typedef __checkReturn boolean_t 2560 (*efx_timer_ev_t)( 2561 __in_opt void *arg, 2562 __in uint32_t label); 2563 2564 typedef __checkReturn boolean_t 2565 (*efx_link_change_ev_t)( 2566 __in_opt void *arg, 2567 __in efx_link_mode_t link_mode); 2568 2569 #if EFSYS_OPT_MON_STATS 2570 2571 typedef __checkReturn boolean_t 2572 (*efx_monitor_ev_t)( 2573 __in_opt void *arg, 2574 __in efx_mon_stat_t id, 2575 __in efx_mon_stat_value_t value); 2576 2577 #endif /* EFSYS_OPT_MON_STATS */ 2578 2579 #if EFSYS_OPT_MAC_STATS 2580 2581 typedef __checkReturn boolean_t 2582 (*efx_mac_stats_ev_t)( 2583 __in_opt void *arg, 2584 __in uint32_t generation); 2585 2586 #endif /* EFSYS_OPT_MAC_STATS */ 2587 2588 #if EFSYS_OPT_DESC_PROXY 2589 2590 /* 2591 * NOTE: This callback returns the raw descriptor data, which has not been 2592 * converted to host endian. The callback must use the EFX_OWORD macros 2593 * to extract the descriptor fields as host endian values. 2594 */ 2595 typedef __checkReturn boolean_t 2596 (*efx_desc_proxy_txq_desc_ev_t)( 2597 __in_opt void *arg, 2598 __in uint16_t vi_id, 2599 __in efx_oword_t txq_desc); 2600 2601 /* 2602 * NOTE: This callback returns the raw descriptor data, which has not been 2603 * converted to host endian. The callback must use the EFX_OWORD macros 2604 * to extract the descriptor fields as host endian values. 2605 */ 2606 typedef __checkReturn boolean_t 2607 (*efx_desc_proxy_virtq_desc_ev_t)( 2608 __in_opt void *arg, 2609 __in uint16_t vi_id, 2610 __in uint16_t avail, 2611 __in efx_oword_t virtq_desc); 2612 2613 #endif /* EFSYS_OPT_DESC_PROXY */ 2614 2615 typedef struct efx_ev_callbacks_s { 2616 efx_initialized_ev_t eec_initialized; 2617 efx_rx_ev_t eec_rx; 2618 efx_rx_packets_ev_t eec_rx_packets; 2619 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2620 efx_rx_ps_ev_t eec_rx_ps; 2621 #endif 2622 efx_tx_ev_t eec_tx; 2623 efx_tx_ndescs_ev_t eec_tx_ndescs; 2624 efx_exception_ev_t eec_exception; 2625 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2626 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2627 efx_txq_flush_done_ev_t eec_txq_flush_done; 2628 efx_software_ev_t eec_software; 2629 efx_sram_ev_t eec_sram; 2630 efx_wake_up_ev_t eec_wake_up; 2631 efx_timer_ev_t eec_timer; 2632 efx_link_change_ev_t eec_link_change; 2633 #if EFSYS_OPT_MON_STATS 2634 efx_monitor_ev_t eec_monitor; 2635 #endif /* EFSYS_OPT_MON_STATS */ 2636 #if EFSYS_OPT_MAC_STATS 2637 efx_mac_stats_ev_t eec_mac_stats; 2638 #endif /* EFSYS_OPT_MAC_STATS */ 2639 #if EFSYS_OPT_DESC_PROXY 2640 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc; 2641 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc; 2642 #endif /* EFSYS_OPT_DESC_PROXY */ 2643 2644 } efx_ev_callbacks_t; 2645 2646 LIBEFX_API 2647 extern __checkReturn boolean_t 2648 efx_ev_qpending( 2649 __in efx_evq_t *eep, 2650 __in unsigned int count); 2651 2652 #if EFSYS_OPT_EV_PREFETCH 2653 2654 LIBEFX_API 2655 extern void 2656 efx_ev_qprefetch( 2657 __in efx_evq_t *eep, 2658 __in unsigned int count); 2659 2660 #endif /* EFSYS_OPT_EV_PREFETCH */ 2661 2662 LIBEFX_API 2663 extern void 2664 efx_ev_qcreate_check_init_done( 2665 __in efx_evq_t *eep, 2666 __in const efx_ev_callbacks_t *eecp, 2667 __in_opt void *arg); 2668 2669 LIBEFX_API 2670 extern void 2671 efx_ev_qpoll( 2672 __in efx_evq_t *eep, 2673 __inout unsigned int *countp, 2674 __in const efx_ev_callbacks_t *eecp, 2675 __in_opt void *arg); 2676 2677 LIBEFX_API 2678 extern __checkReturn efx_rc_t 2679 efx_ev_usecs_to_ticks( 2680 __in efx_nic_t *enp, 2681 __in unsigned int usecs, 2682 __out unsigned int *ticksp); 2683 2684 LIBEFX_API 2685 extern __checkReturn efx_rc_t 2686 efx_ev_qmoderate( 2687 __in efx_evq_t *eep, 2688 __in unsigned int us); 2689 2690 LIBEFX_API 2691 extern __checkReturn efx_rc_t 2692 efx_ev_qprime( 2693 __in efx_evq_t *eep, 2694 __in unsigned int count); 2695 2696 #if EFSYS_OPT_QSTATS 2697 2698 #if EFSYS_OPT_NAMES 2699 2700 LIBEFX_API 2701 extern const char * 2702 efx_ev_qstat_name( 2703 __in efx_nic_t *enp, 2704 __in unsigned int id); 2705 2706 #endif /* EFSYS_OPT_NAMES */ 2707 2708 LIBEFX_API 2709 extern void 2710 efx_ev_qstats_update( 2711 __in efx_evq_t *eep, 2712 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2713 2714 #endif /* EFSYS_OPT_QSTATS */ 2715 2716 LIBEFX_API 2717 extern void 2718 efx_ev_qdestroy( 2719 __in efx_evq_t *eep); 2720 2721 /* RX */ 2722 2723 LIBEFX_API 2724 extern __checkReturn efx_rc_t 2725 efx_rx_init( 2726 __inout efx_nic_t *enp); 2727 2728 LIBEFX_API 2729 extern void 2730 efx_rx_fini( 2731 __in efx_nic_t *enp); 2732 2733 #if EFSYS_OPT_RX_SCATTER 2734 LIBEFX_API 2735 extern __checkReturn efx_rc_t 2736 efx_rx_scatter_enable( 2737 __in efx_nic_t *enp, 2738 __in unsigned int buf_size); 2739 #endif /* EFSYS_OPT_RX_SCATTER */ 2740 2741 /* Handle to represent use of the default RSS context. */ 2742 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2743 2744 #if EFSYS_OPT_RX_SCALE 2745 2746 typedef enum efx_rx_hash_alg_e { 2747 EFX_RX_HASHALG_LFSR = 0, 2748 EFX_RX_HASHALG_TOEPLITZ, 2749 EFX_RX_HASHALG_PACKED_STREAM, 2750 EFX_RX_NHASHALGS 2751 } efx_rx_hash_alg_t; 2752 2753 /* 2754 * Legacy hash type flags. 2755 * 2756 * They represent standard tuples for distinct traffic classes. 2757 */ 2758 #define EFX_RX_HASH_IPV4 (1U << 0) 2759 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2760 #define EFX_RX_HASH_IPV6 (1U << 2) 2761 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2762 2763 #define EFX_RX_HASH_LEGACY_MASK \ 2764 (EFX_RX_HASH_IPV4 | \ 2765 EFX_RX_HASH_TCPIPV4 | \ 2766 EFX_RX_HASH_IPV6 | \ 2767 EFX_RX_HASH_TCPIPV6) 2768 2769 /* 2770 * The type of the argument used by efx_rx_scale_mode_set() to 2771 * provide a means for the client drivers to configure hashing. 2772 * 2773 * A properly constructed value can either be: 2774 * - a combination of legacy flags 2775 * - a combination of EFX_RX_HASH() flags 2776 */ 2777 typedef uint32_t efx_rx_hash_type_t; 2778 2779 typedef enum efx_rx_hash_support_e { 2780 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2781 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2782 } efx_rx_hash_support_t; 2783 2784 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2785 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2786 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2787 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2788 2789 typedef enum efx_rx_scale_context_type_e { 2790 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2791 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2792 EFX_RX_SCALE_SHARED, /* Read-only key/indirection table */ 2793 EFX_RX_SCALE_EVEN_SPREAD, /* No indirection table, writable key */ 2794 } efx_rx_scale_context_type_t; 2795 2796 /* 2797 * Traffic classes eligible for hash computation. 2798 * 2799 * Select packet headers used in computing the receive hash. 2800 * This uses the same encoding as the RSS_MODES field of 2801 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2802 */ 2803 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2804 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2805 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2806 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2807 #define EFX_RX_CLASS_IPV4_LBN 16 2808 #define EFX_RX_CLASS_IPV4_WIDTH 4 2809 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2810 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2811 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2812 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2813 #define EFX_RX_CLASS_IPV6_LBN 28 2814 #define EFX_RX_CLASS_IPV6_WIDTH 4 2815 2816 #define EFX_RX_NCLASSES 6 2817 2818 /* 2819 * Ancillary flags used to construct generic hash tuples. 2820 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2821 */ 2822 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2823 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2824 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2825 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2826 2827 /* 2828 * Generic hash tuples. 2829 * 2830 * They express combinations of packet fields 2831 * which can contribute to the hash value for 2832 * a particular traffic class. 2833 */ 2834 #define EFX_RX_CLASS_HASH_DISABLE 0 2835 2836 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2837 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2838 2839 #define EFX_RX_CLASS_HASH_2TUPLE \ 2840 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2841 EFX_RX_CLASS_HASH_DST_ADDR) 2842 2843 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2844 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2845 EFX_RX_CLASS_HASH_SRC_PORT) 2846 2847 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2848 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2849 EFX_RX_CLASS_HASH_DST_PORT) 2850 2851 #define EFX_RX_CLASS_HASH_4TUPLE \ 2852 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2853 EFX_RX_CLASS_HASH_DST_ADDR | \ 2854 EFX_RX_CLASS_HASH_SRC_PORT | \ 2855 EFX_RX_CLASS_HASH_DST_PORT) 2856 2857 #define EFX_RX_CLASS_HASH_NTUPLES 7 2858 2859 /* 2860 * Hash flag constructor. 2861 * 2862 * Resulting flags encode hash tuples for specific traffic classes. 2863 * The client drivers are encouraged to use these flags to form 2864 * a hash type value. 2865 */ 2866 #define EFX_RX_HASH(_class, _tuple) \ 2867 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2868 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2869 2870 /* 2871 * The maximum number of EFX_RX_HASH() flags. 2872 */ 2873 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2874 2875 LIBEFX_API 2876 extern __checkReturn efx_rc_t 2877 efx_rx_scale_hash_flags_get( 2878 __in efx_nic_t *enp, 2879 __in efx_rx_hash_alg_t hash_alg, 2880 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2881 __in unsigned int max_nflags, 2882 __out unsigned int *nflagsp); 2883 2884 LIBEFX_API 2885 extern __checkReturn efx_rc_t 2886 efx_rx_hash_default_support_get( 2887 __in efx_nic_t *enp, 2888 __out efx_rx_hash_support_t *supportp); 2889 2890 2891 LIBEFX_API 2892 extern __checkReturn efx_rc_t 2893 efx_rx_scale_default_support_get( 2894 __in efx_nic_t *enp, 2895 __out efx_rx_scale_context_type_t *typep); 2896 2897 LIBEFX_API 2898 extern __checkReturn efx_rc_t 2899 efx_rx_scale_context_alloc( 2900 __in efx_nic_t *enp, 2901 __in efx_rx_scale_context_type_t type, 2902 __in uint32_t num_queues, 2903 __out uint32_t *rss_contextp); 2904 2905 LIBEFX_API 2906 extern __checkReturn efx_rc_t 2907 efx_rx_scale_context_alloc_v2( 2908 __in efx_nic_t *enp, 2909 __in efx_rx_scale_context_type_t type, 2910 __in uint32_t num_queues, 2911 __in uint32_t table_nentries, 2912 __out uint32_t *rss_contextp); 2913 2914 LIBEFX_API 2915 extern __checkReturn efx_rc_t 2916 efx_rx_scale_context_free( 2917 __in efx_nic_t *enp, 2918 __in uint32_t rss_context); 2919 2920 LIBEFX_API 2921 extern __checkReturn efx_rc_t 2922 efx_rx_scale_mode_set( 2923 __in efx_nic_t *enp, 2924 __in uint32_t rss_context, 2925 __in efx_rx_hash_alg_t alg, 2926 __in efx_rx_hash_type_t type, 2927 __in boolean_t insert); 2928 2929 LIBEFX_API 2930 extern __checkReturn efx_rc_t 2931 efx_rx_scale_tbl_set( 2932 __in efx_nic_t *enp, 2933 __in uint32_t rss_context, 2934 __in_ecount(nentries) unsigned int *table, 2935 __in size_t nentries); 2936 2937 LIBEFX_API 2938 extern __checkReturn efx_rc_t 2939 efx_rx_scale_key_set( 2940 __in efx_nic_t *enp, 2941 __in uint32_t rss_context, 2942 __in_ecount(n) uint8_t *key, 2943 __in size_t n); 2944 2945 LIBEFX_API 2946 extern __checkReturn uint32_t 2947 efx_pseudo_hdr_hash_get( 2948 __in efx_rxq_t *erp, 2949 __in efx_rx_hash_alg_t func, 2950 __in uint8_t *buffer); 2951 2952 #endif /* EFSYS_OPT_RX_SCALE */ 2953 2954 LIBEFX_API 2955 extern __checkReturn efx_rc_t 2956 efx_pseudo_hdr_pkt_length_get( 2957 __in efx_rxq_t *erp, 2958 __in uint8_t *buffer, 2959 __out uint16_t *pkt_lengthp); 2960 2961 LIBEFX_API 2962 extern __checkReturn size_t 2963 efx_rxq_size( 2964 __in const efx_nic_t *enp, 2965 __in unsigned int ndescs); 2966 2967 LIBEFX_API 2968 extern __checkReturn unsigned int 2969 efx_rxq_nbufs( 2970 __in const efx_nic_t *enp, 2971 __in unsigned int ndescs); 2972 2973 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2974 2975 /* 2976 * libefx representation of the Rx prefix layout information. 2977 * 2978 * The information may be used inside libefx to implement Rx prefix fields 2979 * accessors and by drivers which process Rx prefix itself. 2980 */ 2981 2982 /* 2983 * All known Rx prefix fields. 2984 * 2985 * An Rx prefix may have a subset of these fields. 2986 */ 2987 typedef enum efx_rx_prefix_field_e { 2988 EFX_RX_PREFIX_FIELD_LENGTH = 0, 2989 EFX_RX_PREFIX_FIELD_ORIG_LENGTH, 2990 EFX_RX_PREFIX_FIELD_CLASS, 2991 EFX_RX_PREFIX_FIELD_RSS_HASH, 2992 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID, 2993 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP, 2994 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI, 2995 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI, 2996 EFX_RX_PREFIX_FIELD_USER_FLAG, 2997 EFX_RX_PREFIX_FIELD_USER_MARK, 2998 EFX_RX_PREFIX_FIELD_USER_MARK_VALID, 2999 EFX_RX_PREFIX_FIELD_CSUM_FRAME, 3000 EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 3001 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 3002 EFX_RX_PREFIX_NFIELDS 3003 } efx_rx_prefix_field_t; 3004 3005 /* 3006 * Location and endianness of a field in Rx prefix. 3007 * 3008 * If width is zero, the field is not present. 3009 */ 3010 typedef struct efx_rx_prefix_field_info_s { 3011 uint16_t erpfi_offset_bits; 3012 uint8_t erpfi_width_bits; 3013 boolean_t erpfi_big_endian; 3014 } efx_rx_prefix_field_info_t; 3015 3016 /* Helper macro to define Rx prefix fields */ 3017 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \ 3018 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \ 3019 .erpfi_offset_bits = EFX_LOW_BIT(_field), \ 3020 .erpfi_width_bits = EFX_WIDTH(_field), \ 3021 .erpfi_big_endian = (_big_endian), \ 3022 } 3023 3024 typedef struct efx_rx_prefix_layout_s { 3025 uint32_t erpl_id; 3026 uint8_t erpl_length; 3027 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS]; 3028 } efx_rx_prefix_layout_t; 3029 3030 /* 3031 * Helper function to find out a bit mask of wanted but not available 3032 * Rx prefix fields. 3033 * 3034 * A field is considered as not available if any parameter mismatch. 3035 */ 3036 LIBEFX_API 3037 extern __checkReturn uint32_t 3038 efx_rx_prefix_layout_check( 3039 __in const efx_rx_prefix_layout_t *available, 3040 __in const efx_rx_prefix_layout_t *wanted); 3041 3042 LIBEFX_API 3043 extern __checkReturn efx_rc_t 3044 efx_rx_prefix_get_layout( 3045 __in const efx_rxq_t *erp, 3046 __out efx_rx_prefix_layout_t *erplp); 3047 3048 typedef enum efx_rxq_type_e { 3049 EFX_RXQ_TYPE_DEFAULT, 3050 EFX_RXQ_TYPE_PACKED_STREAM, 3051 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 3052 EFX_RXQ_NTYPES 3053 } efx_rxq_type_t; 3054 3055 /* 3056 * Dummy flag to be used instead of 0 to make it clear that the argument 3057 * is receive queue flags. 3058 */ 3059 #define EFX_RXQ_FLAG_NONE 0x0 3060 #define EFX_RXQ_FLAG_SCATTER 0x1 3061 /* 3062 * If tunnels are supported and Rx event can provide information about 3063 * either outer or inner packet classes (e.g. SFN8xxx adapters with 3064 * full-feature firmware variant running), outer classes are requested by 3065 * default. However, if the driver supports tunnels, the flag allows to 3066 * request inner classes which are required to be able to interpret inner 3067 * Rx checksum offload results. 3068 */ 3069 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 3070 /* 3071 * Request delivery of the RSS hash calculated by HW to be used by 3072 * the driver. 3073 */ 3074 #define EFX_RXQ_FLAG_RSS_HASH 0x4 3075 /* 3076 * Request ingress mport field in the Rx prefix of a queue. 3077 */ 3078 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8 3079 /* 3080 * Request user mark field in the Rx prefix of a queue. 3081 */ 3082 #define EFX_RXQ_FLAG_USER_MARK 0x10 3083 /* 3084 * Request user flag field in the Rx prefix of a queue. 3085 */ 3086 #define EFX_RXQ_FLAG_USER_FLAG 0x20 3087 3088 LIBEFX_API 3089 extern __checkReturn efx_rc_t 3090 efx_rx_qcreate( 3091 __in efx_nic_t *enp, 3092 __in unsigned int index, 3093 __in unsigned int label, 3094 __in efx_rxq_type_t type, 3095 __in size_t buf_size, 3096 __in efsys_mem_t *esmp, 3097 __in size_t ndescs, 3098 __in uint32_t id, 3099 __in unsigned int flags, 3100 __in efx_evq_t *eep, 3101 __deref_out efx_rxq_t **erpp); 3102 3103 #if EFSYS_OPT_RX_PACKED_STREAM 3104 3105 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 3106 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 3107 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 3108 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 3109 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 3110 3111 LIBEFX_API 3112 extern __checkReturn efx_rc_t 3113 efx_rx_qcreate_packed_stream( 3114 __in efx_nic_t *enp, 3115 __in unsigned int index, 3116 __in unsigned int label, 3117 __in uint32_t ps_buf_size, 3118 __in efsys_mem_t *esmp, 3119 __in size_t ndescs, 3120 __in efx_evq_t *eep, 3121 __deref_out efx_rxq_t **erpp); 3122 3123 #endif 3124 3125 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 3126 3127 /* Maximum head-of-line block timeout in nanoseconds */ 3128 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 3129 3130 LIBEFX_API 3131 extern __checkReturn efx_rc_t 3132 efx_rx_qcreate_es_super_buffer( 3133 __in efx_nic_t *enp, 3134 __in unsigned int index, 3135 __in unsigned int label, 3136 __in uint32_t n_bufs_per_desc, 3137 __in uint32_t max_dma_len, 3138 __in uint32_t buf_stride, 3139 __in uint32_t hol_block_timeout, 3140 __in efsys_mem_t *esmp, 3141 __in size_t ndescs, 3142 __in unsigned int flags, 3143 __in efx_evq_t *eep, 3144 __deref_out efx_rxq_t **erpp); 3145 3146 #endif 3147 3148 typedef struct efx_buffer_s { 3149 efsys_dma_addr_t eb_addr; 3150 size_t eb_size; 3151 boolean_t eb_eop; 3152 } efx_buffer_t; 3153 3154 typedef struct efx_desc_s { 3155 efx_qword_t ed_eq; 3156 } efx_desc_t; 3157 3158 LIBEFX_API 3159 extern void 3160 efx_rx_qpost( 3161 __in efx_rxq_t *erp, 3162 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 3163 __in size_t size, 3164 __in unsigned int ndescs, 3165 __in unsigned int completed, 3166 __in unsigned int added); 3167 3168 LIBEFX_API 3169 extern void 3170 efx_rx_qpush( 3171 __in efx_rxq_t *erp, 3172 __in unsigned int added, 3173 __inout unsigned int *pushedp); 3174 3175 #if EFSYS_OPT_RX_PACKED_STREAM 3176 3177 LIBEFX_API 3178 extern void 3179 efx_rx_qpush_ps_credits( 3180 __in efx_rxq_t *erp); 3181 3182 LIBEFX_API 3183 extern __checkReturn uint8_t * 3184 efx_rx_qps_packet_info( 3185 __in efx_rxq_t *erp, 3186 __in uint8_t *buffer, 3187 __in uint32_t buffer_length, 3188 __in uint32_t current_offset, 3189 __out uint16_t *lengthp, 3190 __out uint32_t *next_offsetp, 3191 __out uint32_t *timestamp); 3192 #endif 3193 3194 LIBEFX_API 3195 extern __checkReturn efx_rc_t 3196 efx_rx_qflush( 3197 __in efx_rxq_t *erp); 3198 3199 LIBEFX_API 3200 extern void 3201 efx_rx_qenable( 3202 __in efx_rxq_t *erp); 3203 3204 LIBEFX_API 3205 extern void 3206 efx_rx_qdestroy( 3207 __in efx_rxq_t *erp); 3208 3209 /* TX */ 3210 3211 typedef struct efx_txq_s efx_txq_t; 3212 3213 #if EFSYS_OPT_QSTATS 3214 3215 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 3216 typedef enum efx_tx_qstat_e { 3217 TX_POST, 3218 TX_POST_PIO, 3219 TX_NQSTATS 3220 } efx_tx_qstat_t; 3221 3222 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 3223 3224 #endif /* EFSYS_OPT_QSTATS */ 3225 3226 LIBEFX_API 3227 extern __checkReturn efx_rc_t 3228 efx_tx_init( 3229 __in efx_nic_t *enp); 3230 3231 LIBEFX_API 3232 extern void 3233 efx_tx_fini( 3234 __in efx_nic_t *enp); 3235 3236 LIBEFX_API 3237 extern __checkReturn size_t 3238 efx_txq_size( 3239 __in const efx_nic_t *enp, 3240 __in unsigned int ndescs); 3241 3242 LIBEFX_API 3243 extern __checkReturn unsigned int 3244 efx_txq_nbufs( 3245 __in const efx_nic_t *enp, 3246 __in unsigned int ndescs); 3247 3248 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 3249 3250 #define EFX_TXQ_CKSUM_IPV4 0x0001 3251 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 3252 #define EFX_TXQ_FATSOV2 0x0004 3253 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 3254 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 3255 3256 LIBEFX_API 3257 extern __checkReturn efx_rc_t 3258 efx_tx_qcreate( 3259 __in efx_nic_t *enp, 3260 __in unsigned int index, 3261 __in unsigned int label, 3262 __in efsys_mem_t *esmp, 3263 __in size_t n, 3264 __in uint32_t id, 3265 __in uint16_t flags, 3266 __in efx_evq_t *eep, 3267 __deref_out efx_txq_t **etpp, 3268 __out unsigned int *addedp); 3269 3270 LIBEFX_API 3271 extern __checkReturn efx_rc_t 3272 efx_tx_qpost( 3273 __in efx_txq_t *etp, 3274 __in_ecount(ndescs) efx_buffer_t *eb, 3275 __in unsigned int ndescs, 3276 __in unsigned int completed, 3277 __inout unsigned int *addedp); 3278 3279 LIBEFX_API 3280 extern __checkReturn efx_rc_t 3281 efx_tx_qpace( 3282 __in efx_txq_t *etp, 3283 __in unsigned int ns); 3284 3285 LIBEFX_API 3286 extern void 3287 efx_tx_qpush( 3288 __in efx_txq_t *etp, 3289 __in unsigned int added, 3290 __in unsigned int pushed); 3291 3292 LIBEFX_API 3293 extern __checkReturn efx_rc_t 3294 efx_tx_qflush( 3295 __in efx_txq_t *etp); 3296 3297 LIBEFX_API 3298 extern void 3299 efx_tx_qenable( 3300 __in efx_txq_t *etp); 3301 3302 LIBEFX_API 3303 extern __checkReturn efx_rc_t 3304 efx_tx_qpio_enable( 3305 __in efx_txq_t *etp); 3306 3307 LIBEFX_API 3308 extern void 3309 efx_tx_qpio_disable( 3310 __in efx_txq_t *etp); 3311 3312 LIBEFX_API 3313 extern __checkReturn efx_rc_t 3314 efx_tx_qpio_write( 3315 __in efx_txq_t *etp, 3316 __in_ecount(buf_length) uint8_t *buffer, 3317 __in size_t buf_length, 3318 __in size_t pio_buf_offset); 3319 3320 LIBEFX_API 3321 extern __checkReturn efx_rc_t 3322 efx_tx_qpio_post( 3323 __in efx_txq_t *etp, 3324 __in size_t pkt_length, 3325 __in unsigned int completed, 3326 __inout unsigned int *addedp); 3327 3328 LIBEFX_API 3329 extern __checkReturn efx_rc_t 3330 efx_tx_qdesc_post( 3331 __in efx_txq_t *etp, 3332 __in_ecount(n) efx_desc_t *ed, 3333 __in unsigned int n, 3334 __in unsigned int completed, 3335 __inout unsigned int *addedp); 3336 3337 LIBEFX_API 3338 extern void 3339 efx_tx_qdesc_dma_create( 3340 __in efx_txq_t *etp, 3341 __in efsys_dma_addr_t addr, 3342 __in size_t size, 3343 __in boolean_t eop, 3344 __out efx_desc_t *edp); 3345 3346 LIBEFX_API 3347 extern void 3348 efx_tx_qdesc_tso_create( 3349 __in efx_txq_t *etp, 3350 __in uint16_t ipv4_id, 3351 __in uint32_t tcp_seq, 3352 __in uint8_t tcp_flags, 3353 __out efx_desc_t *edp); 3354 3355 /* Number of FATSOv2 option descriptors */ 3356 #define EFX_TX_FATSOV2_OPT_NDESCS 2 3357 3358 /* Maximum number of DMA segments per TSO packet (not superframe) */ 3359 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 3360 3361 LIBEFX_API 3362 extern void 3363 efx_tx_qdesc_tso2_create( 3364 __in efx_txq_t *etp, 3365 __in uint16_t ipv4_id, 3366 __in uint16_t outer_ipv4_id, 3367 __in uint32_t tcp_seq, 3368 __in uint16_t tcp_mss, 3369 __out_ecount(count) efx_desc_t *edp, 3370 __in int count); 3371 3372 LIBEFX_API 3373 extern void 3374 efx_tx_qdesc_vlantci_create( 3375 __in efx_txq_t *etp, 3376 __in uint16_t tci, 3377 __out efx_desc_t *edp); 3378 3379 LIBEFX_API 3380 extern void 3381 efx_tx_qdesc_checksum_create( 3382 __in efx_txq_t *etp, 3383 __in uint16_t flags, 3384 __out efx_desc_t *edp); 3385 3386 #if EFSYS_OPT_QSTATS 3387 3388 #if EFSYS_OPT_NAMES 3389 3390 LIBEFX_API 3391 extern const char * 3392 efx_tx_qstat_name( 3393 __in efx_nic_t *etp, 3394 __in unsigned int id); 3395 3396 #endif /* EFSYS_OPT_NAMES */ 3397 3398 LIBEFX_API 3399 extern void 3400 efx_tx_qstats_update( 3401 __in efx_txq_t *etp, 3402 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 3403 3404 #endif /* EFSYS_OPT_QSTATS */ 3405 3406 LIBEFX_API 3407 extern void 3408 efx_tx_qdestroy( 3409 __in efx_txq_t *etp); 3410 3411 3412 /* FILTER */ 3413 3414 #if EFSYS_OPT_FILTER 3415 3416 #define EFX_ETHER_TYPE_IPV4 0x0800 3417 #define EFX_ETHER_TYPE_IPV6 0x86DD 3418 3419 #define EFX_IPPROTO_TCP 6 3420 #define EFX_IPPROTO_UDP 17 3421 #define EFX_IPPROTO_GRE 47 3422 3423 /* Use RSS to spread across multiple queues */ 3424 #define EFX_FILTER_FLAG_RX_RSS 0x01 3425 /* Enable RX scatter */ 3426 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 3427 /* 3428 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 3429 * May only be set by the filter implementation for each type. 3430 * A removal request will restore the automatic filter in its place. 3431 */ 3432 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 3433 /* Filter is for RX */ 3434 #define EFX_FILTER_FLAG_RX 0x08 3435 /* Filter is for TX */ 3436 #define EFX_FILTER_FLAG_TX 0x10 3437 /* Set match flag on the received packet */ 3438 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 3439 /* Set match mark on the received packet */ 3440 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 3441 3442 typedef uint8_t efx_filter_flags_t; 3443 3444 /* 3445 * Flags which specify the fields to match on. The values are the same as in the 3446 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 3447 */ 3448 3449 /* Match by remote IP host address */ 3450 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 3451 /* Match by local IP host address */ 3452 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 3453 /* Match by remote MAC address */ 3454 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 3455 /* Match by remote TCP/UDP port */ 3456 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 3457 /* Match by remote TCP/UDP port */ 3458 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 3459 /* Match by local TCP/UDP port */ 3460 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 3461 /* Match by Ether-type */ 3462 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 3463 /* Match by inner VLAN ID */ 3464 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 3465 /* Match by outer VLAN ID */ 3466 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 3467 /* Match by IP transport protocol */ 3468 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 3469 /* Match by ingress MPORT */ 3470 #define EFX_FILTER_MATCH_MPORT 0x00000400 3471 /* Match by VNI or VSID */ 3472 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 3473 /* For encapsulated packets, match by inner frame local MAC address */ 3474 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 3475 /* For encapsulated packets, match all multicast inner frames */ 3476 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 3477 /* For encapsulated packets, match all unicast inner frames */ 3478 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 3479 /* 3480 * Match by encap type, this flag does not correspond to 3481 * the MCDI match flags and any unoccupied value may be used 3482 */ 3483 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 3484 /* Match otherwise-unmatched multicast and broadcast packets */ 3485 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 3486 /* Match otherwise-unmatched unicast packets */ 3487 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 3488 3489 typedef uint32_t efx_filter_match_flags_t; 3490 3491 /* Filter priority from lowest to highest */ 3492 typedef enum efx_filter_priority_s { 3493 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device 3494 * address list or hardware 3495 * requirements. This may only be used 3496 * by the filter implementation for 3497 * each NIC type. */ 3498 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 3499 EFX_FILTER_NPRI, 3500 } efx_filter_priority_t; 3501 3502 /* 3503 * FIXME: All these fields are assumed to be in little-endian byte order. 3504 * It may be better for some to be big-endian. See bug42804. 3505 */ 3506 3507 typedef struct efx_filter_spec_s { 3508 efx_filter_match_flags_t efs_match_flags; 3509 uint8_t efs_priority; 3510 efx_filter_flags_t efs_flags; 3511 uint16_t efs_dmaq_id; 3512 uint32_t efs_rss_context; 3513 uint32_t efs_mark; 3514 /* 3515 * Saved lower-priority filter. If it is set, it is restored on 3516 * filter delete operation. 3517 */ 3518 struct efx_filter_spec_s *efs_overridden_spec; 3519 /* Fields below here are hashed for software filter lookup */ 3520 uint16_t efs_outer_vid; 3521 uint16_t efs_inner_vid; 3522 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 3523 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 3524 uint16_t efs_ether_type; 3525 uint8_t efs_ip_proto; 3526 efx_tunnel_protocol_t efs_encap_type; 3527 uint16_t efs_loc_port; 3528 uint16_t efs_rem_port; 3529 efx_oword_t efs_rem_host; 3530 efx_oword_t efs_loc_host; 3531 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 3532 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 3533 uint32_t efs_ingress_mport; 3534 } efx_filter_spec_t; 3535 3536 3537 /* Default values for use in filter specifications */ 3538 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 3539 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 3540 3541 LIBEFX_API 3542 extern __checkReturn efx_rc_t 3543 efx_filter_init( 3544 __in efx_nic_t *enp); 3545 3546 LIBEFX_API 3547 extern void 3548 efx_filter_fini( 3549 __in efx_nic_t *enp); 3550 3551 LIBEFX_API 3552 extern __checkReturn efx_rc_t 3553 efx_filter_insert( 3554 __in efx_nic_t *enp, 3555 __inout efx_filter_spec_t *spec); 3556 3557 LIBEFX_API 3558 extern __checkReturn efx_rc_t 3559 efx_filter_remove( 3560 __in efx_nic_t *enp, 3561 __inout efx_filter_spec_t *spec); 3562 3563 LIBEFX_API 3564 extern __checkReturn efx_rc_t 3565 efx_filter_restore( 3566 __in efx_nic_t *enp); 3567 3568 LIBEFX_API 3569 extern __checkReturn efx_rc_t 3570 efx_filter_supported_filters( 3571 __in efx_nic_t *enp, 3572 __out_ecount(buffer_length) uint32_t *buffer, 3573 __in size_t buffer_length, 3574 __out size_t *list_lengthp); 3575 3576 LIBEFX_API 3577 extern void 3578 efx_filter_spec_init_rx( 3579 __out efx_filter_spec_t *spec, 3580 __in efx_filter_priority_t priority, 3581 __in efx_filter_flags_t flags, 3582 __in efx_rxq_t *erp); 3583 3584 LIBEFX_API 3585 extern void 3586 efx_filter_spec_init_tx( 3587 __out efx_filter_spec_t *spec, 3588 __in efx_txq_t *etp); 3589 3590 LIBEFX_API 3591 extern __checkReturn efx_rc_t 3592 efx_filter_spec_set_ipv4_local( 3593 __inout efx_filter_spec_t *spec, 3594 __in uint8_t proto, 3595 __in uint32_t host, 3596 __in uint16_t port); 3597 3598 LIBEFX_API 3599 extern __checkReturn efx_rc_t 3600 efx_filter_spec_set_ipv4_full( 3601 __inout efx_filter_spec_t *spec, 3602 __in uint8_t proto, 3603 __in uint32_t lhost, 3604 __in uint16_t lport, 3605 __in uint32_t rhost, 3606 __in uint16_t rport); 3607 3608 LIBEFX_API 3609 extern __checkReturn efx_rc_t 3610 efx_filter_spec_set_eth_local( 3611 __inout efx_filter_spec_t *spec, 3612 __in uint16_t vid, 3613 __in const uint8_t *addr); 3614 3615 LIBEFX_API 3616 extern void 3617 efx_filter_spec_set_ether_type( 3618 __inout efx_filter_spec_t *spec, 3619 __in uint16_t ether_type); 3620 3621 LIBEFX_API 3622 extern __checkReturn efx_rc_t 3623 efx_filter_spec_set_uc_def( 3624 __inout efx_filter_spec_t *spec); 3625 3626 LIBEFX_API 3627 extern __checkReturn efx_rc_t 3628 efx_filter_spec_set_mc_def( 3629 __inout efx_filter_spec_t *spec); 3630 3631 typedef enum efx_filter_inner_frame_match_e { 3632 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3633 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3634 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3635 } efx_filter_inner_frame_match_t; 3636 3637 LIBEFX_API 3638 extern __checkReturn efx_rc_t 3639 efx_filter_spec_set_encap_type( 3640 __inout efx_filter_spec_t *spec, 3641 __in efx_tunnel_protocol_t encap_type, 3642 __in efx_filter_inner_frame_match_t inner_frame_match); 3643 3644 LIBEFX_API 3645 extern __checkReturn efx_rc_t 3646 efx_filter_spec_set_vxlan( 3647 __inout efx_filter_spec_t *spec, 3648 __in const uint8_t *vni, 3649 __in const uint8_t *inner_addr, 3650 __in const uint8_t *outer_addr); 3651 3652 LIBEFX_API 3653 extern __checkReturn efx_rc_t 3654 efx_filter_spec_set_geneve( 3655 __inout efx_filter_spec_t *spec, 3656 __in const uint8_t *vni, 3657 __in const uint8_t *inner_addr, 3658 __in const uint8_t *outer_addr); 3659 3660 LIBEFX_API 3661 extern __checkReturn efx_rc_t 3662 efx_filter_spec_set_nvgre( 3663 __inout efx_filter_spec_t *spec, 3664 __in const uint8_t *vsid, 3665 __in const uint8_t *inner_addr, 3666 __in const uint8_t *outer_addr); 3667 3668 #if EFSYS_OPT_RX_SCALE 3669 LIBEFX_API 3670 extern __checkReturn efx_rc_t 3671 efx_filter_spec_set_rss_context( 3672 __inout efx_filter_spec_t *spec, 3673 __in uint32_t rss_context); 3674 #endif 3675 #endif /* EFSYS_OPT_FILTER */ 3676 3677 /* HASH */ 3678 3679 LIBEFX_API 3680 extern __checkReturn uint32_t 3681 efx_hash_dwords( 3682 __in_ecount(count) uint32_t const *input, 3683 __in size_t count, 3684 __in uint32_t init); 3685 3686 LIBEFX_API 3687 extern __checkReturn uint32_t 3688 efx_hash_bytes( 3689 __in_ecount(length) uint8_t const *input, 3690 __in size_t length, 3691 __in uint32_t init); 3692 3693 #if EFSYS_OPT_LICENSING 3694 3695 /* LICENSING */ 3696 3697 typedef struct efx_key_stats_s { 3698 uint32_t eks_valid; 3699 uint32_t eks_invalid; 3700 uint32_t eks_blacklisted; 3701 uint32_t eks_unverifiable; 3702 uint32_t eks_wrong_node; 3703 uint32_t eks_licensed_apps_lo; 3704 uint32_t eks_licensed_apps_hi; 3705 uint32_t eks_licensed_features_lo; 3706 uint32_t eks_licensed_features_hi; 3707 } efx_key_stats_t; 3708 3709 LIBEFX_API 3710 extern __checkReturn efx_rc_t 3711 efx_lic_init( 3712 __in efx_nic_t *enp); 3713 3714 LIBEFX_API 3715 extern void 3716 efx_lic_fini( 3717 __in efx_nic_t *enp); 3718 3719 LIBEFX_API 3720 extern __checkReturn boolean_t 3721 efx_lic_check_support( 3722 __in efx_nic_t *enp); 3723 3724 LIBEFX_API 3725 extern __checkReturn efx_rc_t 3726 efx_lic_update_licenses( 3727 __in efx_nic_t *enp); 3728 3729 LIBEFX_API 3730 extern __checkReturn efx_rc_t 3731 efx_lic_get_key_stats( 3732 __in efx_nic_t *enp, 3733 __out efx_key_stats_t *ksp); 3734 3735 LIBEFX_API 3736 extern __checkReturn efx_rc_t 3737 efx_lic_app_state( 3738 __in efx_nic_t *enp, 3739 __in uint64_t app_id, 3740 __out boolean_t *licensedp); 3741 3742 LIBEFX_API 3743 extern __checkReturn efx_rc_t 3744 efx_lic_get_id( 3745 __in efx_nic_t *enp, 3746 __in size_t buffer_size, 3747 __out uint32_t *typep, 3748 __out size_t *lengthp, 3749 __out_opt uint8_t *bufferp); 3750 3751 3752 LIBEFX_API 3753 extern __checkReturn efx_rc_t 3754 efx_lic_find_start( 3755 __in efx_nic_t *enp, 3756 __in_bcount(buffer_size) 3757 caddr_t bufferp, 3758 __in size_t buffer_size, 3759 __out uint32_t *startp); 3760 3761 LIBEFX_API 3762 extern __checkReturn efx_rc_t 3763 efx_lic_find_end( 3764 __in efx_nic_t *enp, 3765 __in_bcount(buffer_size) 3766 caddr_t bufferp, 3767 __in size_t buffer_size, 3768 __in uint32_t offset, 3769 __out uint32_t *endp); 3770 3771 LIBEFX_API 3772 extern __checkReturn __success(return != B_FALSE) boolean_t 3773 efx_lic_find_key( 3774 __in efx_nic_t *enp, 3775 __in_bcount(buffer_size) 3776 caddr_t bufferp, 3777 __in size_t buffer_size, 3778 __in uint32_t offset, 3779 __out uint32_t *startp, 3780 __out uint32_t *lengthp); 3781 3782 LIBEFX_API 3783 extern __checkReturn __success(return != B_FALSE) boolean_t 3784 efx_lic_validate_key( 3785 __in efx_nic_t *enp, 3786 __in_bcount(length) caddr_t keyp, 3787 __in uint32_t length); 3788 3789 LIBEFX_API 3790 extern __checkReturn efx_rc_t 3791 efx_lic_read_key( 3792 __in efx_nic_t *enp, 3793 __in_bcount(buffer_size) 3794 caddr_t bufferp, 3795 __in size_t buffer_size, 3796 __in uint32_t offset, 3797 __in uint32_t length, 3798 __out_bcount_part(key_max_size, *lengthp) 3799 caddr_t keyp, 3800 __in size_t key_max_size, 3801 __out uint32_t *lengthp); 3802 3803 LIBEFX_API 3804 extern __checkReturn efx_rc_t 3805 efx_lic_write_key( 3806 __in efx_nic_t *enp, 3807 __in_bcount(buffer_size) 3808 caddr_t bufferp, 3809 __in size_t buffer_size, 3810 __in uint32_t offset, 3811 __in_bcount(length) caddr_t keyp, 3812 __in uint32_t length, 3813 __out uint32_t *lengthp); 3814 3815 LIBEFX_API 3816 extern __checkReturn efx_rc_t 3817 efx_lic_delete_key( 3818 __in efx_nic_t *enp, 3819 __in_bcount(buffer_size) 3820 caddr_t bufferp, 3821 __in size_t buffer_size, 3822 __in uint32_t offset, 3823 __in uint32_t length, 3824 __in uint32_t end, 3825 __out uint32_t *deltap); 3826 3827 LIBEFX_API 3828 extern __checkReturn efx_rc_t 3829 efx_lic_create_partition( 3830 __in efx_nic_t *enp, 3831 __in_bcount(buffer_size) 3832 caddr_t bufferp, 3833 __in size_t buffer_size); 3834 3835 extern __checkReturn efx_rc_t 3836 efx_lic_finish_partition( 3837 __in efx_nic_t *enp, 3838 __in_bcount(buffer_size) 3839 caddr_t bufferp, 3840 __in size_t buffer_size); 3841 3842 #endif /* EFSYS_OPT_LICENSING */ 3843 3844 /* TUNNEL */ 3845 3846 #if EFSYS_OPT_TUNNEL 3847 3848 LIBEFX_API 3849 extern __checkReturn efx_rc_t 3850 efx_tunnel_init( 3851 __in efx_nic_t *enp); 3852 3853 LIBEFX_API 3854 extern void 3855 efx_tunnel_fini( 3856 __in efx_nic_t *enp); 3857 3858 /* 3859 * For overlay network encapsulation using UDP, the firmware needs to know 3860 * the configured UDP port for the overlay so it can decode encapsulated 3861 * frames correctly. 3862 * The UDP port/protocol list is global. 3863 */ 3864 3865 LIBEFX_API 3866 extern __checkReturn efx_rc_t 3867 efx_tunnel_config_udp_add( 3868 __in efx_nic_t *enp, 3869 __in uint16_t port /* host/cpu-endian */, 3870 __in efx_tunnel_protocol_t protocol); 3871 3872 /* 3873 * Returns EBUSY if reconfiguration of the port is in progress in other thread. 3874 */ 3875 LIBEFX_API 3876 extern __checkReturn efx_rc_t 3877 efx_tunnel_config_udp_remove( 3878 __in efx_nic_t *enp, 3879 __in uint16_t port /* host/cpu-endian */, 3880 __in efx_tunnel_protocol_t protocol); 3881 3882 /* 3883 * Returns EBUSY if reconfiguration of any of the tunnel entries 3884 * is in progress in other thread. 3885 */ 3886 LIBEFX_API 3887 extern __checkReturn efx_rc_t 3888 efx_tunnel_config_clear( 3889 __in efx_nic_t *enp); 3890 3891 /** 3892 * Apply tunnel UDP ports configuration to hardware. 3893 * 3894 * EAGAIN is returned if hardware will be reset (datapath and managment CPU 3895 * reboot). 3896 */ 3897 LIBEFX_API 3898 extern __checkReturn efx_rc_t 3899 efx_tunnel_reconfigure( 3900 __in efx_nic_t *enp); 3901 3902 #endif /* EFSYS_OPT_TUNNEL */ 3903 3904 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3905 3906 /** 3907 * Firmware subvariant choice options. 3908 * 3909 * It may be switched to no Tx checksum if attached drivers are either 3910 * preboot or firmware subvariant aware and no VIS are allocated. 3911 * If may be always switched to default explicitly using set request or 3912 * implicitly if unaware driver is attaching. If switching is done when 3913 * a driver is attached, it gets MC_REBOOT event and should recreate its 3914 * datapath. 3915 * 3916 * See SF-119419-TC DPDK Firmware Driver Interface and 3917 * SF-109306-TC EF10 for Driver Writers for details. 3918 */ 3919 typedef enum efx_nic_fw_subvariant_e { 3920 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3921 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3922 EFX_NIC_FW_SUBVARIANT_NTYPES 3923 } efx_nic_fw_subvariant_t; 3924 3925 LIBEFX_API 3926 extern __checkReturn efx_rc_t 3927 efx_nic_get_fw_subvariant( 3928 __in efx_nic_t *enp, 3929 __out efx_nic_fw_subvariant_t *subvariantp); 3930 3931 LIBEFX_API 3932 extern __checkReturn efx_rc_t 3933 efx_nic_set_fw_subvariant( 3934 __in efx_nic_t *enp, 3935 __in efx_nic_fw_subvariant_t subvariant); 3936 3937 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3938 3939 typedef enum efx_phy_fec_type_e { 3940 EFX_PHY_FEC_NONE = 0, 3941 EFX_PHY_FEC_BASER, 3942 EFX_PHY_FEC_RS 3943 } efx_phy_fec_type_t; 3944 3945 LIBEFX_API 3946 extern __checkReturn efx_rc_t 3947 efx_phy_fec_type_get( 3948 __in efx_nic_t *enp, 3949 __out efx_phy_fec_type_t *typep); 3950 3951 typedef struct efx_phy_link_state_s { 3952 uint32_t epls_adv_cap_mask; 3953 uint32_t epls_lp_cap_mask; 3954 uint32_t epls_ld_cap_mask; 3955 unsigned int epls_fcntl; 3956 efx_phy_fec_type_t epls_fec; 3957 efx_link_mode_t epls_link_mode; 3958 } efx_phy_link_state_t; 3959 3960 LIBEFX_API 3961 extern __checkReturn efx_rc_t 3962 efx_phy_link_state_get( 3963 __in efx_nic_t *enp, 3964 __out efx_phy_link_state_t *eplsp); 3965 3966 3967 #if EFSYS_OPT_EVB 3968 3969 typedef uint32_t efx_vswitch_id_t; 3970 typedef uint32_t efx_vport_id_t; 3971 3972 typedef enum efx_vswitch_type_e { 3973 EFX_VSWITCH_TYPE_VLAN = 1, 3974 EFX_VSWITCH_TYPE_VEB, 3975 /* VSWITCH_TYPE_VEPA: obsolete */ 3976 EFX_VSWITCH_TYPE_MUX = 4, 3977 } efx_vswitch_type_t; 3978 3979 typedef enum efx_vport_type_e { 3980 EFX_VPORT_TYPE_NORMAL = 4, 3981 EFX_VPORT_TYPE_EXPANSION, 3982 EFX_VPORT_TYPE_TEST, 3983 } efx_vport_type_t; 3984 3985 /* Unspecified VLAN ID to support disabling of VLAN filtering */ 3986 #define EFX_FILTER_VID_UNSPEC 0xffff 3987 #define EFX_DEFAULT_VSWITCH_ID 1 3988 3989 /* Default VF VLAN ID on creation */ 3990 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC 3991 #define EFX_VPORT_ID_INVALID 0 3992 3993 typedef struct efx_vport_config_s { 3994 /* Either VF index or EFX_PCI_VF_INVALID for PF */ 3995 uint16_t evc_function; 3996 /* VLAN ID of the associated function */ 3997 uint16_t evc_vid; 3998 /* vport id shared with client driver */ 3999 efx_vport_id_t evc_vport_id; 4000 /* MAC address of the associated function */ 4001 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; 4002 /* 4003 * vports created with this flag set may only transfer traffic on the 4004 * VLANs permitted by the vport. Also, an attempt to install filter with 4005 * VLAN will be refused unless requesting function has VLAN privilege. 4006 */ 4007 boolean_t evc_vlan_restrict; 4008 /* Whether this function is assigned or not */ 4009 boolean_t evc_vport_assigned; 4010 } efx_vport_config_t; 4011 4012 typedef struct efx_vswitch_s efx_vswitch_t; 4013 4014 LIBEFX_API 4015 extern __checkReturn efx_rc_t 4016 efx_evb_init( 4017 __in efx_nic_t *enp); 4018 4019 LIBEFX_API 4020 extern void 4021 efx_evb_fini( 4022 __in efx_nic_t *enp); 4023 4024 LIBEFX_API 4025 extern __checkReturn efx_rc_t 4026 efx_evb_vswitch_create( 4027 __in efx_nic_t *enp, 4028 __in uint32_t num_vports, 4029 __inout_ecount(num_vports) efx_vport_config_t *vport_configp, 4030 __deref_out efx_vswitch_t **evpp); 4031 4032 LIBEFX_API 4033 extern __checkReturn efx_rc_t 4034 efx_evb_vswitch_destroy( 4035 __in efx_nic_t *enp, 4036 __in efx_vswitch_t *evp); 4037 4038 LIBEFX_API 4039 extern __checkReturn efx_rc_t 4040 efx_evb_vport_mac_set( 4041 __in efx_nic_t *enp, 4042 __in efx_vswitch_t *evp, 4043 __in efx_vport_id_t vport_id, 4044 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); 4045 4046 LIBEFX_API 4047 extern __checkReturn efx_rc_t 4048 efx_evb_vport_vlan_set( 4049 __in efx_nic_t *enp, 4050 __in efx_vswitch_t *evp, 4051 __in efx_vport_id_t vport_id, 4052 __in uint16_t vid); 4053 4054 LIBEFX_API 4055 extern __checkReturn efx_rc_t 4056 efx_evb_vport_reset( 4057 __in efx_nic_t *enp, 4058 __in efx_vswitch_t *evp, 4059 __in efx_vport_id_t vport_id, 4060 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, 4061 __in uint16_t vid, 4062 __out boolean_t *is_fn_resetp); 4063 4064 LIBEFX_API 4065 extern __checkReturn efx_rc_t 4066 efx_evb_vport_stats( 4067 __in efx_nic_t *enp, 4068 __in efx_vswitch_t *evp, 4069 __in efx_vport_id_t vport_id, 4070 __out efsys_mem_t *stats_bufferp); 4071 4072 #endif /* EFSYS_OPT_EVB */ 4073 4074 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 4075 4076 typedef struct efx_proxy_auth_config_s { 4077 efsys_mem_t *request_bufferp; 4078 efsys_mem_t *response_bufferp; 4079 efsys_mem_t *status_bufferp; 4080 uint32_t block_cnt; 4081 uint32_t *op_listp; 4082 size_t op_count; 4083 uint32_t handled_privileges; 4084 } efx_proxy_auth_config_t; 4085 4086 typedef struct efx_proxy_cmd_params_s { 4087 uint32_t pf_index; 4088 uint32_t vf_index; 4089 uint8_t *request_bufferp; 4090 size_t request_size; 4091 uint8_t *response_bufferp; 4092 size_t response_size; 4093 size_t *response_size_actualp; 4094 } efx_proxy_cmd_params_t; 4095 4096 LIBEFX_API 4097 extern __checkReturn efx_rc_t 4098 efx_proxy_auth_init( 4099 __in efx_nic_t *enp); 4100 4101 LIBEFX_API 4102 extern void 4103 efx_proxy_auth_fini( 4104 __in efx_nic_t *enp); 4105 4106 LIBEFX_API 4107 extern __checkReturn efx_rc_t 4108 efx_proxy_auth_configure( 4109 __in efx_nic_t *enp, 4110 __in efx_proxy_auth_config_t *configp); 4111 4112 LIBEFX_API 4113 extern __checkReturn efx_rc_t 4114 efx_proxy_auth_destroy( 4115 __in efx_nic_t *enp, 4116 __in uint32_t handled_privileges); 4117 4118 LIBEFX_API 4119 extern __checkReturn efx_rc_t 4120 efx_proxy_auth_complete_request( 4121 __in efx_nic_t *enp, 4122 __in uint32_t fn_index, 4123 __in uint32_t proxy_result, 4124 __in uint32_t handle); 4125 4126 LIBEFX_API 4127 extern __checkReturn efx_rc_t 4128 efx_proxy_auth_exec_cmd( 4129 __in efx_nic_t *enp, 4130 __inout efx_proxy_cmd_params_t *paramsp); 4131 4132 LIBEFX_API 4133 extern __checkReturn efx_rc_t 4134 efx_proxy_auth_set_privilege_mask( 4135 __in efx_nic_t *enp, 4136 __in uint32_t vf_index, 4137 __in uint32_t mask, 4138 __in uint32_t value); 4139 4140 LIBEFX_API 4141 extern __checkReturn efx_rc_t 4142 efx_proxy_auth_privilege_mask_get( 4143 __in efx_nic_t *enp, 4144 __in uint32_t pf_index, 4145 __in uint32_t vf_index, 4146 __out uint32_t *maskp); 4147 4148 LIBEFX_API 4149 extern __checkReturn efx_rc_t 4150 efx_proxy_auth_privilege_modify( 4151 __in efx_nic_t *enp, 4152 __in uint32_t pf_index, 4153 __in uint32_t vf_index, 4154 __in uint32_t add_privileges_mask, 4155 __in uint32_t remove_privileges_mask); 4156 4157 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 4158 4159 #if EFSYS_OPT_MAE 4160 4161 LIBEFX_API 4162 extern __checkReturn efx_rc_t 4163 efx_mae_init( 4164 __in efx_nic_t *enp); 4165 4166 LIBEFX_API 4167 extern void 4168 efx_mae_fini( 4169 __in efx_nic_t *enp); 4170 4171 typedef struct efx_mae_limits_s { 4172 uint32_t eml_max_n_action_prios; 4173 uint32_t eml_max_n_outer_prios; 4174 uint32_t eml_encap_types_supported; 4175 uint32_t eml_encap_header_size_limit; 4176 uint32_t eml_max_n_counters; 4177 } efx_mae_limits_t; 4178 4179 LIBEFX_API 4180 extern __checkReturn efx_rc_t 4181 efx_mae_get_limits( 4182 __in efx_nic_t *enp, 4183 __out efx_mae_limits_t *emlp); 4184 4185 typedef enum efx_mae_rule_type_e { 4186 EFX_MAE_RULE_ACTION = 0, 4187 EFX_MAE_RULE_OUTER, 4188 4189 EFX_MAE_RULE_NTYPES 4190 } efx_mae_rule_type_t; 4191 4192 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t; 4193 4194 LIBEFX_API 4195 extern __checkReturn efx_rc_t 4196 efx_mae_match_spec_init( 4197 __in efx_nic_t *enp, 4198 __in efx_mae_rule_type_t type, 4199 __in uint32_t prio, 4200 __out efx_mae_match_spec_t **specp); 4201 4202 LIBEFX_API 4203 extern void 4204 efx_mae_match_spec_fini( 4205 __in efx_nic_t *enp, 4206 __in efx_mae_match_spec_t *spec); 4207 4208 typedef enum efx_mae_field_id_e { 4209 /* 4210 * Fields which can be set by efx_mae_match_spec_field_set() 4211 * or by using dedicated field-specific helper APIs. 4212 */ 4213 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0, 4214 EFX_MAE_FIELD_ETHER_TYPE_BE, 4215 EFX_MAE_FIELD_ETH_SADDR_BE, 4216 EFX_MAE_FIELD_ETH_DADDR_BE, 4217 EFX_MAE_FIELD_VLAN0_TCI_BE, 4218 EFX_MAE_FIELD_VLAN0_PROTO_BE, 4219 EFX_MAE_FIELD_VLAN1_TCI_BE, 4220 EFX_MAE_FIELD_VLAN1_PROTO_BE, 4221 EFX_MAE_FIELD_SRC_IP4_BE, 4222 EFX_MAE_FIELD_DST_IP4_BE, 4223 EFX_MAE_FIELD_IP_PROTO, 4224 EFX_MAE_FIELD_IP_TOS, 4225 EFX_MAE_FIELD_IP_TTL, 4226 EFX_MAE_FIELD_SRC_IP6_BE, 4227 EFX_MAE_FIELD_DST_IP6_BE, 4228 EFX_MAE_FIELD_L4_SPORT_BE, 4229 EFX_MAE_FIELD_L4_DPORT_BE, 4230 EFX_MAE_FIELD_TCP_FLAGS_BE, 4231 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE, 4232 EFX_MAE_FIELD_ENC_ETH_SADDR_BE, 4233 EFX_MAE_FIELD_ENC_ETH_DADDR_BE, 4234 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE, 4235 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE, 4236 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE, 4237 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE, 4238 EFX_MAE_FIELD_ENC_SRC_IP4_BE, 4239 EFX_MAE_FIELD_ENC_DST_IP4_BE, 4240 EFX_MAE_FIELD_ENC_IP_PROTO, 4241 EFX_MAE_FIELD_ENC_IP_TOS, 4242 EFX_MAE_FIELD_ENC_IP_TTL, 4243 EFX_MAE_FIELD_ENC_SRC_IP6_BE, 4244 EFX_MAE_FIELD_ENC_DST_IP6_BE, 4245 EFX_MAE_FIELD_ENC_L4_SPORT_BE, 4246 EFX_MAE_FIELD_ENC_L4_DPORT_BE, 4247 EFX_MAE_FIELD_ENC_VNET_ID_BE, 4248 EFX_MAE_FIELD_OUTER_RULE_ID, 4249 4250 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */ 4251 EFX_MAE_FIELD_HAS_OVLAN, 4252 EFX_MAE_FIELD_HAS_IVLAN, 4253 EFX_MAE_FIELD_ENC_HAS_OVLAN, 4254 EFX_MAE_FIELD_ENC_HAS_IVLAN, 4255 4256 /* 4257 * Fields which can be set by efx_mae_match_spec_field_set() 4258 * or by using dedicated field-specific helper APIs. 4259 */ 4260 EFX_MAE_FIELD_RECIRC_ID, 4261 EFX_MAE_FIELD_NIDS 4262 } efx_mae_field_id_t; 4263 4264 /* MPORT selector. Used to refer to MPORTs in match/action rules. */ 4265 typedef struct efx_mport_sel_s { 4266 uint32_t sel; 4267 } efx_mport_sel_t; 4268 4269 /* 4270 * MPORT ID. Used to refer dynamically to a specific MPORT. 4271 * The difference between MPORT selector and MPORT ID is that 4272 * selector can specify an exact MPORT ID or it can specify a 4273 * pattern by which an exact MPORT ID can be selected. For example, 4274 * static MPORT selector can specify MPORT of a current PF, which 4275 * will be translated to the dynamic MPORT ID based on which PF is 4276 * using that MPORT selector. 4277 */ 4278 typedef struct efx_mport_id_s { 4279 uint32_t id; 4280 } efx_mport_id_t; 4281 4282 typedef enum efx_mport_type_e { 4283 EFX_MPORT_TYPE_NET_PORT = 0, 4284 EFX_MPORT_TYPE_ALIAS, 4285 EFX_MPORT_TYPE_VNIC, 4286 } efx_mport_type_t; 4287 4288 typedef enum efx_mport_vnic_client_type_e { 4289 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1, 4290 EFX_MPORT_VNIC_CLIENT_PLUGIN, 4291 } efx_mport_vnic_client_type_t; 4292 4293 typedef struct efx_mport_desc_s { 4294 efx_mport_id_t emd_id; 4295 boolean_t emd_can_receive_on; 4296 boolean_t emd_can_deliver_to; 4297 boolean_t emd_can_delete; 4298 boolean_t emd_zombie; 4299 efx_mport_type_t emd_type; 4300 union { 4301 struct { 4302 uint32_t ep_index; 4303 } emd_net_port; 4304 struct { 4305 efx_mport_id_t ea_target_mport_id; 4306 } emd_alias; 4307 struct { 4308 efx_mport_vnic_client_type_t ev_client_type; 4309 efx_pcie_interface_t ev_intf; 4310 uint16_t ev_pf; 4311 uint16_t ev_vf; 4312 /* MCDI client handle for this VNIC. */ 4313 uint32_t ev_handle; 4314 } emd_vnic; 4315 }; 4316 } efx_mport_desc_t; 4317 4318 #define EFX_MPORT_NULL (0U) 4319 4320 /* 4321 * Generate an invalid MPORT selector. 4322 * 4323 * The resulting MPORT selector is opaque to the caller. Requests 4324 * that attempt to use it will be rejected. 4325 */ 4326 LIBEFX_API 4327 extern __checkReturn efx_rc_t 4328 efx_mae_mport_invalid( 4329 __out efx_mport_sel_t *mportp); 4330 4331 /* 4332 * Get MPORT selector of a physical port. 4333 * 4334 * The resulting MPORT selector is opaque to the caller and can be 4335 * passed as an argument to efx_mae_match_spec_mport_set() 4336 * and efx_mae_action_set_populate_deliver(). 4337 */ 4338 LIBEFX_API 4339 extern __checkReturn efx_rc_t 4340 efx_mae_mport_by_phy_port( 4341 __in uint32_t phy_port, 4342 __out efx_mport_sel_t *mportp); 4343 4344 /* 4345 * Get MPORT selector of a PCIe function. 4346 * 4347 * The resulting MPORT selector is opaque to the caller and can be 4348 * passed as an argument to efx_mae_match_spec_mport_set() 4349 * and efx_mae_action_set_populate_deliver(). 4350 */ 4351 LIBEFX_API 4352 extern __checkReturn efx_rc_t 4353 efx_mae_mport_by_pcie_function( 4354 __in uint32_t pf, 4355 __in uint32_t vf, 4356 __out efx_mport_sel_t *mportp); 4357 4358 /* 4359 * Get MPORT selector of a multi-host PCIe function. 4360 * 4361 * The resulting MPORT selector is opaque to the caller and can be 4362 * passed as an argument to efx_mae_match_spec_mport_set() 4363 * and efx_mae_action_set_populate_deliver(). 4364 */ 4365 LIBEFX_API 4366 extern __checkReturn efx_rc_t 4367 efx_mae_mport_by_pcie_mh_function( 4368 __in efx_pcie_interface_t intf, 4369 __in uint32_t pf, 4370 __in uint32_t vf, 4371 __out efx_mport_sel_t *mportp); 4372 4373 /* 4374 * Get MPORT selector by an MPORT ID 4375 * 4376 * The resulting MPORT selector is opaque to the caller and can be 4377 * passed as an argument to efx_mae_match_spec_mport_set() 4378 * and efx_mae_action_set_populate_deliver(). 4379 */ 4380 LIBEFX_API 4381 extern __checkReturn efx_rc_t 4382 efx_mae_mport_by_id( 4383 __in const efx_mport_id_t *mport_idp, 4384 __out efx_mport_sel_t *mportp); 4385 4386 /* Get MPORT ID by an MPORT selector */ 4387 LIBEFX_API 4388 extern __checkReturn efx_rc_t 4389 efx_mae_mport_id_by_selector( 4390 __in efx_nic_t *enp, 4391 __in const efx_mport_sel_t *mport_selectorp, 4392 __out efx_mport_id_t *mport_idp); 4393 4394 /* 4395 * Fields which have BE postfix in their named constants are expected 4396 * to be passed by callers in big-endian byte order. They will appear 4397 * in the MCDI buffer, which is a part of the match specification, in 4398 * the very same byte order, that is, no conversion will be performed. 4399 * 4400 * Fields which don't have BE postfix in their named constants are in 4401 * host byte order. MCDI expects them to be little-endian, so the API 4402 * will take care to carry out conversion to little-endian byte order. 4403 * At the moment, the only field in host byte order is MPORT selector. 4404 */ 4405 LIBEFX_API 4406 extern __checkReturn efx_rc_t 4407 efx_mae_match_spec_field_set( 4408 __in efx_mae_match_spec_t *spec, 4409 __in efx_mae_field_id_t field_id, 4410 __in size_t value_size, 4411 __in_bcount(value_size) const uint8_t *value, 4412 __in size_t mask_size, 4413 __in_bcount(mask_size) const uint8_t *mask); 4414 4415 /* The corresponding mask will be set to B_TRUE. */ 4416 LIBEFX_API 4417 extern __checkReturn efx_rc_t 4418 efx_mae_match_spec_bit_set( 4419 __in efx_mae_match_spec_t *spec, 4420 __in efx_mae_field_id_t field_id, 4421 __in boolean_t value); 4422 4423 /* If the mask argument is NULL, the API will use full mask by default. */ 4424 LIBEFX_API 4425 extern __checkReturn efx_rc_t 4426 efx_mae_match_spec_mport_set( 4427 __in efx_mae_match_spec_t *spec, 4428 __in const efx_mport_sel_t *valuep, 4429 __in_opt const efx_mport_sel_t *maskp); 4430 4431 LIBEFX_API 4432 extern __checkReturn efx_rc_t 4433 efx_mae_match_spec_recirc_id_set( 4434 __in efx_mae_match_spec_t *spec, 4435 __in uint8_t recirc_id); 4436 4437 LIBEFX_API 4438 extern __checkReturn boolean_t 4439 efx_mae_match_specs_equal( 4440 __in const efx_mae_match_spec_t *left, 4441 __in const efx_mae_match_spec_t *right); 4442 4443 /* 4444 * Make sure that match fields known by EFX have proper masks set 4445 * in the match specification as per requirements of SF-122526-TC. 4446 * 4447 * In the case efx_mae_field_id_t lacks named identifiers for any 4448 * fields which the FW maintains with support status MATCH_ALWAYS, 4449 * the validation result may not be accurate. 4450 */ 4451 LIBEFX_API 4452 extern __checkReturn boolean_t 4453 efx_mae_match_spec_is_valid( 4454 __in efx_nic_t *enp, 4455 __in const efx_mae_match_spec_t *spec); 4456 4457 typedef struct efx_mae_actions_s efx_mae_actions_t; 4458 4459 LIBEFX_API 4460 extern __checkReturn efx_rc_t 4461 efx_mae_action_set_spec_init( 4462 __in efx_nic_t *enp, 4463 __out efx_mae_actions_t **specp); 4464 4465 LIBEFX_API 4466 extern void 4467 efx_mae_action_set_spec_fini( 4468 __in efx_nic_t *enp, 4469 __in efx_mae_actions_t *spec); 4470 4471 LIBEFX_API 4472 extern __checkReturn efx_rc_t 4473 efx_mae_action_set_populate_decap( 4474 __in efx_mae_actions_t *spec); 4475 4476 LIBEFX_API 4477 extern __checkReturn efx_rc_t 4478 efx_mae_action_set_populate_vlan_pop( 4479 __in efx_mae_actions_t *spec); 4480 4481 /* 4482 * This always amends the outermost header. This way, for a tunnel 4483 * packet, if action DECAP is not requested, this will affect the 4484 * outer header; otherwise, the inner header will be updated. 4485 * 4486 * Use efx_mae_action_set_fill_in_dst_mac_id() to set ID of 4487 * the allocated MAC address entry in the specification 4488 * prior to action set allocation. 4489 */ 4490 LIBEFX_API 4491 extern __checkReturn efx_rc_t 4492 efx_mae_action_set_populate_set_dst_mac( 4493 __in efx_mae_actions_t *spec); 4494 4495 /* 4496 * This always amends the outermost header. This way, for a tunnel 4497 * packet, if action DECAP is not requested, this will affect the 4498 * outer header; otherwise, the inner header will be updated. 4499 * 4500 * Use efx_mae_action_set_fill_in_src_mac_id() to set ID of 4501 * the allocated MAC address entry in the specification 4502 * prior to action set allocation. 4503 */ 4504 LIBEFX_API 4505 extern __checkReturn efx_rc_t 4506 efx_mae_action_set_populate_set_src_mac( 4507 __in efx_mae_actions_t *spec); 4508 4509 /* 4510 * This always amends the outermost header. This way, for a tunnel 4511 * packet, if action DECAP is not requested, this will affect the 4512 * outer header; otherwise, the inner header will be updated. 4513 * 4514 * This will also take care to update IPv4 checksum accordingly. 4515 */ 4516 LIBEFX_API 4517 extern __checkReturn efx_rc_t 4518 efx_mae_action_set_populate_decr_ip_ttl( 4519 __in efx_mae_actions_t *spec); 4520 4521 LIBEFX_API 4522 extern __checkReturn efx_rc_t 4523 efx_mae_action_set_populate_vlan_push( 4524 __in efx_mae_actions_t *spec, 4525 __in uint16_t tpid_be, 4526 __in uint16_t tci_be); 4527 4528 /* 4529 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated 4530 * encap. header in the specification prior to action set allocation. 4531 */ 4532 LIBEFX_API 4533 extern __checkReturn efx_rc_t 4534 efx_mae_action_set_populate_encap( 4535 __in efx_mae_actions_t *spec); 4536 4537 /* 4538 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter 4539 * in the specification prior to action set allocation. 4540 * 4541 * NOTICE: the HW will conduct action COUNT after actions DECAP, 4542 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet, 4543 * but, as a workaround, this order is not validated by the API. 4544 * 4545 * The workaround helps to unblock DPDK + Open vSwitch use case. 4546 * In Open vSwitch, this action is always the first to be added, 4547 * in particular, it's known to be inserted before action DECAP, 4548 * so enforcing the right order here would cause runtime errors. 4549 * The existing behaviour in Open vSwitch is unlikely to change 4550 * any time soon, and the workaround is a good solution because 4551 * in fact the real COUNT order is a don't care to Open vSwitch. 4552 */ 4553 LIBEFX_API 4554 extern __checkReturn efx_rc_t 4555 efx_mae_action_set_populate_count( 4556 __in efx_mae_actions_t *spec); 4557 4558 LIBEFX_API 4559 extern __checkReturn efx_rc_t 4560 efx_mae_action_set_populate_flag( 4561 __in efx_mae_actions_t *spec); 4562 4563 LIBEFX_API 4564 extern __checkReturn efx_rc_t 4565 efx_mae_action_set_populate_mark( 4566 __in efx_mae_actions_t *spec, 4567 __in uint32_t mark_value); 4568 4569 LIBEFX_API 4570 extern __checkReturn efx_rc_t 4571 efx_mae_action_set_populate_deliver( 4572 __in efx_mae_actions_t *spec, 4573 __in const efx_mport_sel_t *mportp); 4574 4575 LIBEFX_API 4576 extern __checkReturn efx_rc_t 4577 efx_mae_action_set_populate_drop( 4578 __in efx_mae_actions_t *spec); 4579 4580 LIBEFX_API 4581 extern __checkReturn boolean_t 4582 efx_mae_action_set_specs_equal( 4583 __in const efx_mae_actions_t *left, 4584 __in const efx_mae_actions_t *right); 4585 4586 /* 4587 * Conduct a comparison to check whether two match specifications 4588 * of equal rule type (action / outer) and priority would map to 4589 * the very same rule class from the firmware's standpoint. 4590 * 4591 * For match specification fields that are not supported by firmware, 4592 * the rule class only matches if the mask/value pairs for that field 4593 * are equal. Clients should use efx_mae_match_spec_is_valid() before 4594 * calling this API to detect usage of unsupported fields. 4595 */ 4596 LIBEFX_API 4597 extern __checkReturn efx_rc_t 4598 efx_mae_match_specs_class_cmp( 4599 __in efx_nic_t *enp, 4600 __in const efx_mae_match_spec_t *left, 4601 __in const efx_mae_match_spec_t *right, 4602 __out boolean_t *have_same_classp); 4603 4604 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX 4605 4606 /* Rule ID */ 4607 typedef struct efx_mae_rule_id_s { 4608 uint32_t id; 4609 } efx_mae_rule_id_t; 4610 4611 /* 4612 * Set the initial recirculation ID. It goes to action rule (AR) lookup. 4613 * 4614 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set(). 4615 */ 4616 LIBEFX_API 4617 extern __checkReturn efx_rc_t 4618 efx_mae_outer_rule_recirc_id_set( 4619 __in efx_mae_match_spec_t *spec, 4620 __in uint8_t recirc_id); 4621 4622 LIBEFX_API 4623 extern __checkReturn efx_rc_t 4624 efx_mae_outer_rule_insert( 4625 __in efx_nic_t *enp, 4626 __in const efx_mae_match_spec_t *spec, 4627 __in efx_tunnel_protocol_t encap_type, 4628 __out efx_mae_rule_id_t *or_idp); 4629 4630 LIBEFX_API 4631 extern __checkReturn efx_rc_t 4632 efx_mae_outer_rule_remove( 4633 __in efx_nic_t *enp, 4634 __in const efx_mae_rule_id_t *or_idp); 4635 4636 LIBEFX_API 4637 extern __checkReturn efx_rc_t 4638 efx_mae_match_spec_outer_rule_id_set( 4639 __in efx_mae_match_spec_t *spec, 4640 __in const efx_mae_rule_id_t *or_idp); 4641 4642 /* MAC address entry ID */ 4643 typedef struct efx_mae_mac_id_s { 4644 uint32_t id; 4645 } efx_mae_mac_id_t; 4646 4647 LIBEFX_API 4648 extern __checkReturn efx_rc_t 4649 efx_mae_mac_addr_alloc( 4650 __in efx_nic_t *enp, 4651 __in uint8_t addr_bytes[EFX_MAC_ADDR_LEN], 4652 __out efx_mae_mac_id_t *mac_idp); 4653 4654 LIBEFX_API 4655 extern __checkReturn efx_rc_t 4656 efx_mae_mac_addr_free( 4657 __in efx_nic_t *enp, 4658 __in const efx_mae_mac_id_t *mac_idp); 4659 4660 /* See description before efx_mae_action_set_populate_set_dst_mac(). */ 4661 LIBEFX_API 4662 extern __checkReturn efx_rc_t 4663 efx_mae_action_set_fill_in_dst_mac_id( 4664 __in efx_mae_actions_t *spec, 4665 __in const efx_mae_mac_id_t *mac_idp); 4666 4667 /* See description before efx_mae_action_set_populate_set_src_mac(). */ 4668 LIBEFX_API 4669 extern __checkReturn efx_rc_t 4670 efx_mae_action_set_fill_in_src_mac_id( 4671 __in efx_mae_actions_t *spec, 4672 __in const efx_mae_mac_id_t *mac_idp); 4673 4674 /* Encap. header ID */ 4675 typedef struct efx_mae_eh_id_s { 4676 uint32_t id; 4677 } efx_mae_eh_id_t; 4678 4679 LIBEFX_API 4680 extern __checkReturn efx_rc_t 4681 efx_mae_encap_header_alloc( 4682 __in efx_nic_t *enp, 4683 __in efx_tunnel_protocol_t encap_type, 4684 __in_bcount(header_size) uint8_t *header_data, 4685 __in size_t header_size, 4686 __out efx_mae_eh_id_t *eh_idp); 4687 4688 LIBEFX_API 4689 extern __checkReturn efx_rc_t 4690 efx_mae_encap_header_free( 4691 __in efx_nic_t *enp, 4692 __in const efx_mae_eh_id_t *eh_idp); 4693 4694 /* See description before efx_mae_action_set_populate_encap(). */ 4695 LIBEFX_API 4696 extern __checkReturn efx_rc_t 4697 efx_mae_action_set_fill_in_eh_id( 4698 __in efx_mae_actions_t *spec, 4699 __in const efx_mae_eh_id_t *eh_idp); 4700 4701 typedef struct efx_counter_s { 4702 uint32_t id; 4703 } efx_counter_t; 4704 4705 LIBEFX_API 4706 extern __checkReturn unsigned int 4707 efx_mae_action_set_get_nb_count( 4708 __in const efx_mae_actions_t *spec); 4709 4710 /* See description before efx_mae_action_set_populate_count(). */ 4711 LIBEFX_API 4712 extern __checkReturn efx_rc_t 4713 efx_mae_action_set_fill_in_counter_id( 4714 __in efx_mae_actions_t *spec, 4715 __in const efx_counter_t *counter_idp); 4716 4717 /* Action set ID */ 4718 typedef struct efx_mae_aset_id_s { 4719 uint32_t id; 4720 } efx_mae_aset_id_t; 4721 4722 LIBEFX_API 4723 extern __checkReturn efx_rc_t 4724 efx_mae_action_set_alloc( 4725 __in efx_nic_t *enp, 4726 __in const efx_mae_actions_t *spec, 4727 __out efx_mae_aset_id_t *aset_idp); 4728 4729 /* 4730 * Generation count has two purposes: 4731 * 4732 * 1) Distinguish between counter packets that belong to freed counter 4733 * and the packets that belong to reallocated counter (with the same ID); 4734 * 2) Make sure that all packets are received for a counter that was freed; 4735 * 4736 * API users should provide generation count out parameter in allocation 4737 * function if counters can be reallocated and consistent counter values are 4738 * required. 4739 * 4740 * API users that need consistent final counter values after counter 4741 * deallocation or counter stream stop should provide the parameter in 4742 * functions that free the counters and stop the counter stream. 4743 */ 4744 LIBEFX_API 4745 extern __checkReturn efx_rc_t 4746 efx_mae_counters_alloc( 4747 __in efx_nic_t *enp, 4748 __in uint32_t n_counters, 4749 __out uint32_t *n_allocatedp, 4750 __out_ecount(n_counters) efx_counter_t *countersp, 4751 __out_opt uint32_t *gen_countp); 4752 4753 LIBEFX_API 4754 extern __checkReturn efx_rc_t 4755 efx_mae_counters_free( 4756 __in efx_nic_t *enp, 4757 __in uint32_t n_counters, 4758 __out uint32_t *n_freedp, 4759 __in_ecount(n_counters) const efx_counter_t *countersp, 4760 __out_opt uint32_t *gen_countp); 4761 4762 /* When set, include counters with a value of zero */ 4763 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0) 4764 4765 /* 4766 * Set if credit-based flow control is used. In this case the driver 4767 * must call efx_mae_counters_stream_give_credits() to notify the 4768 * packetiser of descriptors written. 4769 */ 4770 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0) 4771 4772 LIBEFX_API 4773 extern __checkReturn efx_rc_t 4774 efx_mae_counters_stream_start( 4775 __in efx_nic_t *enp, 4776 __in uint16_t rxq_id, 4777 __in uint16_t packet_size, 4778 __in uint32_t flags_in, 4779 __out uint32_t *flags_out); 4780 4781 LIBEFX_API 4782 extern __checkReturn efx_rc_t 4783 efx_mae_counters_stream_stop( 4784 __in efx_nic_t *enp, 4785 __in uint16_t rxq_id, 4786 __out_opt uint32_t *gen_countp); 4787 4788 LIBEFX_API 4789 extern __checkReturn efx_rc_t 4790 efx_mae_counters_stream_give_credits( 4791 __in efx_nic_t *enp, 4792 __in uint32_t n_credits); 4793 4794 LIBEFX_API 4795 extern __checkReturn efx_rc_t 4796 efx_mae_action_set_free( 4797 __in efx_nic_t *enp, 4798 __in const efx_mae_aset_id_t *aset_idp); 4799 4800 /* Action set list ID */ 4801 typedef struct efx_mae_aset_list_id_s { 4802 uint32_t id; 4803 } efx_mae_aset_list_id_t; 4804 4805 /* 4806 * Either action set list ID or action set ID must be passed to this API, 4807 * but not both. 4808 */ 4809 LIBEFX_API 4810 extern __checkReturn efx_rc_t 4811 efx_mae_action_rule_insert( 4812 __in efx_nic_t *enp, 4813 __in const efx_mae_match_spec_t *spec, 4814 __in const efx_mae_aset_list_id_t *asl_idp, 4815 __in const efx_mae_aset_id_t *as_idp, 4816 __out efx_mae_rule_id_t *ar_idp); 4817 4818 LIBEFX_API 4819 extern __checkReturn efx_rc_t 4820 efx_mae_action_rule_remove( 4821 __in efx_nic_t *enp, 4822 __in const efx_mae_rule_id_t *ar_idp); 4823 4824 LIBEFX_API 4825 extern __checkReturn efx_rc_t 4826 efx_mcdi_mport_alloc_alias( 4827 __in efx_nic_t *enp, 4828 __out efx_mport_id_t *mportp, 4829 __out_opt uint32_t *labelp); 4830 4831 LIBEFX_API 4832 extern __checkReturn efx_rc_t 4833 efx_mae_mport_free( 4834 __in efx_nic_t *enp, 4835 __in const efx_mport_id_t *mportp); 4836 4837 typedef __checkReturn efx_rc_t 4838 (efx_mae_read_mport_journal_cb)( 4839 __in void *cb_datap, 4840 __in efx_mport_desc_t *mportp, 4841 __in size_t mport_len); 4842 4843 /* 4844 * Read mport descriptions from the MAE journal (which describes added and 4845 * removed mports) and pass them to a user-supplied callback. The user gets 4846 * only one chance to process the data it's given. Once the callback function 4847 * finishes, that particular mport description will be gone. 4848 * The journal will be fully repopulated on PCI reset (efx_nic_reset function). 4849 */ 4850 LIBEFX_API 4851 extern __checkReturn efx_rc_t 4852 efx_mae_read_mport_journal( 4853 __in efx_nic_t *enp, 4854 __in efx_mae_read_mport_journal_cb *cbp, 4855 __in void *cb_datap); 4856 4857 #endif /* EFSYS_OPT_MAE */ 4858 4859 #if EFSYS_OPT_VIRTIO 4860 4861 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues 4862 * while virtio block device has a single virtqueue, 4863 * for further details refer section of 4.2.3 of SF-120734 4864 */ 4865 typedef enum efx_virtio_vq_type_e { 4866 EFX_VIRTIO_VQ_TYPE_NET_RXQ, 4867 EFX_VIRTIO_VQ_TYPE_NET_TXQ, 4868 EFX_VIRTIO_VQ_TYPE_BLOCK, 4869 EFX_VIRTIO_VQ_NTYPES 4870 } efx_virtio_vq_type_t; 4871 4872 typedef struct efx_virtio_vq_dyncfg_s { 4873 /* 4874 * If queue is being created to be migrated then this 4875 * should be the FINAL_PIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 4876 * of the queue being migrated from. Otherwise, it should be zero. 4877 */ 4878 uint32_t evvd_vq_pidx; 4879 /* 4880 * If this queue is being created to be migrated then this 4881 * should be the FINAL_CIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 4882 * of the queue being migrated from. Otherwise, it should be zero. 4883 */ 4884 uint32_t evvd_vq_cidx; 4885 } efx_virtio_vq_dyncfg_t; 4886 4887 /* 4888 * Virtqueue size must be a power of 2, maximum size is 32768 4889 * (see VIRTIO v1.1 section 2.6) 4890 */ 4891 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000 4892 4893 typedef struct efx_virtio_vq_cfg_s { 4894 unsigned int evvc_vq_num; 4895 efx_virtio_vq_type_t evvc_type; 4896 /* 4897 * vDPA as VF : It is target VF number if queue is being created on VF. 4898 * vDPA as PF : If queue to be created on PF then it should be 4899 * EFX_PCI_VF_INVALID. 4900 */ 4901 uint16_t evvc_target_vf; 4902 /* 4903 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and 4904 * virtqueue size 0 means the queue is unavailable. 4905 */ 4906 uint32_t evvc_vq_size; 4907 efsys_dma_addr_t evvc_desc_tbl_addr; 4908 efsys_dma_addr_t evvc_avail_ring_addr; 4909 efsys_dma_addr_t evvc_used_ring_addr; 4910 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */ 4911 uint16_t evvc_msix_vector; 4912 /* 4913 * evvc_pas_id contains a PCIe address space identifier if the queue 4914 * uses PASID. 4915 */ 4916 boolean_t evvc_use_pasid; 4917 uint32_t evvc_pas_id; 4918 /* Negotiated virtio features to be applied to this virtqueue */ 4919 uint64_t evcc_features; 4920 } efx_virtio_vq_cfg_t; 4921 4922 typedef struct efx_virtio_vq_s efx_virtio_vq_t; 4923 4924 typedef enum efx_virtio_device_type_e { 4925 EFX_VIRTIO_DEVICE_TYPE_RESERVED, 4926 EFX_VIRTIO_DEVICE_TYPE_NET, 4927 EFX_VIRTIO_DEVICE_TYPE_BLOCK, 4928 EFX_VIRTIO_DEVICE_NTYPES 4929 } efx_virtio_device_type_t; 4930 4931 LIBEFX_API 4932 extern __checkReturn efx_rc_t 4933 efx_virtio_init( 4934 __in efx_nic_t *enp); 4935 4936 LIBEFX_API 4937 extern void 4938 efx_virtio_fini( 4939 __in efx_nic_t *enp); 4940 4941 /* 4942 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit, 4943 * hypervisor starts configuring all the virtqueues in the device. When the 4944 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues, 4945 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would 4946 * be invoked from dev_conf callback to create the virtqueues, For further 4947 * details refer SF-122427. 4948 */ 4949 LIBEFX_API 4950 extern __checkReturn efx_rc_t 4951 efx_virtio_qcreate( 4952 __in efx_nic_t *enp, 4953 __deref_out efx_virtio_vq_t **evvpp); 4954 4955 LIBEFX_API 4956 extern __checkReturn efx_rc_t 4957 efx_virtio_qstart( 4958 __in efx_virtio_vq_t *evvp, 4959 __in efx_virtio_vq_cfg_t *evvcp, 4960 __in_opt efx_virtio_vq_dyncfg_t *evvdp); 4961 4962 LIBEFX_API 4963 extern __checkReturn efx_rc_t 4964 efx_virtio_qstop( 4965 __in efx_virtio_vq_t *evvp, 4966 __out_opt efx_virtio_vq_dyncfg_t *evvdp); 4967 4968 LIBEFX_API 4969 extern void 4970 efx_virtio_qdestroy( 4971 __in efx_virtio_vq_t *evvp); 4972 4973 /* 4974 * Get the offset in the BAR of the doorbells for a VI. 4975 * net device : doorbell offset of RX & TX queues 4976 * block device : request doorbell offset in the BAR. 4977 * For further details refer section of 4 of SF-119689 4978 */ 4979 LIBEFX_API 4980 extern __checkReturn efx_rc_t 4981 efx_virtio_get_doorbell_offset( 4982 __in efx_virtio_vq_t *evvp, 4983 __out uint32_t *offsetp); 4984 4985 LIBEFX_API 4986 extern __checkReturn efx_rc_t 4987 efx_virtio_get_features( 4988 __in efx_nic_t *enp, 4989 __in efx_virtio_device_type_t type, 4990 __out uint64_t *featuresp); 4991 4992 LIBEFX_API 4993 extern __checkReturn efx_rc_t 4994 efx_virtio_verify_features( 4995 __in efx_nic_t *enp, 4996 __in efx_virtio_device_type_t type, 4997 __in uint64_t features); 4998 4999 #endif /* EFSYS_OPT_VIRTIO */ 5000 5001 LIBEFX_API 5002 extern __checkReturn efx_rc_t 5003 efx_nic_dma_config_add( 5004 __in efx_nic_t *enp, 5005 __in efsys_dma_addr_t trgt_addr, 5006 __in size_t len, 5007 __out_opt efsys_dma_addr_t *nic_basep, 5008 __out_opt efsys_dma_addr_t *trgt_basep, 5009 __out_opt size_t *map_lenp); 5010 5011 LIBEFX_API 5012 extern __checkReturn efx_rc_t 5013 efx_nic_dma_reconfigure( 5014 __in efx_nic_t *enp); 5015 5016 typedef enum efx_nic_dma_addr_type_e { 5017 EFX_NIC_DMA_ADDR_MCDI_BUF, 5018 EFX_NIC_DMA_ADDR_MAC_STATS_BUF, 5019 EFX_NIC_DMA_ADDR_EVENT_RING, 5020 EFX_NIC_DMA_ADDR_RX_RING, 5021 EFX_NIC_DMA_ADDR_TX_RING, 5022 EFX_NIC_DMA_ADDR_RX_BUF, 5023 EFX_NIC_DMA_ADDR_TX_BUF, 5024 5025 EFX_NIC_DMA_ADDR_NTYPES 5026 } efx_nic_dma_addr_type_t; 5027 5028 LIBEFX_API 5029 extern __checkReturn efx_rc_t 5030 efx_nic_dma_map( 5031 __in efx_nic_t *enp, 5032 __in efx_nic_dma_addr_type_t addr_type, 5033 __in efsys_dma_addr_t tgt_addr, 5034 __in size_t len, 5035 __out efsys_dma_addr_t *nic_addrp); 5036 5037 #ifdef __cplusplus 5038 } 5039 #endif 5040 5041 #endif /* _SYS_EFX_H */ 5042