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Searched refs:domains (Results 1 – 14 of 14) sorted by relevance

/dpdk/drivers/net/sfc/
H A Dsfc_switch.c131 struct sfc_mae_switch_domains domains; member
136 .domains = TAILQ_HEAD_INITIALIZER(sfc_mae_switch.domains),
148 TAILQ_FOREACH(domain, &sfc_mae_switch.domains, entries) { in sfc_mae_find_switch_domain_by_id()
192 TAILQ_FOREACH(domain, &sfc_mae_switch.domains, entries) { in sfc_mae_find_switch_domain_by_hw_switch_id()
239 TAILQ_INSERT_TAIL(&sfc_mae_switch.domains, domain, entries); in sfc_mae_assign_switch_domain()
/dpdk/drivers/net/mlx5/
H A Drte_pmd_mlx5.h62 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains);
H A Dmlx5_flow_verbs.c2078 flow_verbs_sync_domain(struct rte_eth_dev *dev, uint32_t domains, in flow_verbs_sync_domain() argument
2082 RTE_SET_USED(domains); in flow_verbs_sync_domain()
H A Dmlx5_flow.h1364 uint32_t domains,
H A Dmlx5_flow.c3713 uint32_t domains __rte_unused, in flow_null_sync_domain()
9952 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) in rte_pmd_mlx5_sync_flow() argument
9960 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); in rte_pmd_mlx5_sync_flow()
H A Dmlx5_flow_dv.c18359 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags) in flow_dv_sync_domain() argument
18364 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) { in flow_dv_sync_domain()
18370 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) { in flow_dv_sync_domain()
18375 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) { in flow_dv_sync_domain()
/dpdk/drivers/event/dlb2/pf/base/
H A Ddlb2_hw_types.h348 struct dlb2_hw_domain domains[DLB2_MAX_NUM_DOMAINS]; member
H A Ddlb2_resource.c140 dlb2_init_domain_rsrc_lists(&hw->domains[i]); in dlb2_resource_init()
141 hw->domains[i].parent_func = &hw->pf; in dlb2_resource_init()
147 list = &hw->domains[i].func_list; in dlb2_resource_init()
212 hw->domains[i].id.phys_id = i; in dlb2_resource_init()
213 hw->domains[i].id.vdev_owned = false; in dlb2_resource_init()
1468 return &hw->domains[id]; in dlb2_get_domain_from_id()
6073 struct dlb2_hw_domain *domain = &hw->domains[i]; in dlb2_finish_unmap_qid_procedures()
6098 struct dlb2_hw_domain *domain = &hw->domains[i]; in dlb2_finish_map_qid_procedures()
/dpdk/doc/guides/
H A Dconf.py97 data = app.builder.env.domains['std'].data
/dpdk/doc/guides/faq/
H A Dfaq.rst106 Therefore, each 64B chunk is interleaved across both memory domains.
119 Therefore, packet buffers and descriptor rings are allocated from both memory domains, thus incurri…
/dpdk/doc/guides/rel_notes/
H A Drelease_21_08.rst15 representing sub-domains of functionality. Each auxiliary device
/dpdk/doc/guides/platform/
H A Dcnxk.rst107 This would enable HW accelerated means of communication between two domains
/dpdk/doc/guides/eventdevs/
H A Ddlb2.rst39 DLB supports 32 scheduling domains.
/dpdk/doc/guides/nics/
H A Dmlx5.rst919 NIC Rx steering domains, no ``MARK`` and ``META`` information crosses
924 related actions and items operate within all supported steering domains,
935 related actions and items operate within all supported steering domains,