| /dpdk/drivers/common/qat/qat_adf/ |
| H A D | icp_qat_hw_gen4_comp.h | 29 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
37 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
41 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
65 QAT_FIELD_SET(val32, csr.abd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
69 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
151 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER()
167 QAT_FIELD_SET(val32, csr.lbc, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER()
184 QAT_FIELD_SET(val32, csr.sdc, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER()
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| /dpdk/drivers/raw/ifpga/base/ |
| H A D | ifpga_defines.h | 108 u64 csr; member
127 u64 csr; member
138 u64 csr; member
148 u64 csr; member
185 u64 csr; member
201 u64 csr; member
215 u64 csr; member
227 u64 csr; member
241 u64 csr; member
266 u64 csr; member
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| H A D | ifpga_fme_error.c | 14 fme_error0.csr = readq(&fme_err->fme_err); in fme_err_get_errors()
15 *val = fme_error0.csr; in fme_err_get_errors()
68 header.csr = readq(&fme_err->header); in fme_err_get_revision()
81 pcie0_err.csr = readq(&fme_err->pcie0_err); in fme_err_get_pcie0_errors()
82 *val = pcie0_err.csr; in fme_err_get_pcie0_errors()
99 if (val != pcie0_err.csr) in fme_err_set_pcie0_errors()
119 *val = pcie1_err.csr; in fme_err_get_pcie1_errors()
136 if (val != pcie1_err.csr) in fme_err_set_pcie1_errors()
156 *val = ras_nonfaterr.csr; in fme_err_get_nonfatal_errors()
169 *val = ras_catfaterr.csr; in fme_err_get_catfatal_errors()
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| H A D | ifpga_feature_dev.c | 30 control.csr = readq(&port_hdr->control); in __fpga_port_enable()
32 writeq(control.csr, &port_hdr->control); in __fpga_port_enable()
48 control.csr = readq(&port_hdr->control); in __fpga_port_disable()
50 writeq(control.csr, &port_hdr->control); in __fpga_port_disable()
121 err_mask.csr = PORT_ERR_MASK; in port_err_mask()
123 err_mask.csr = 0; in port_err_mask()
156 status.csr = readq(&port_hdr->status); in port_err_clear()
171 mask.csr = readq(&port_err->port_error); in port_err_clear()
173 if (mask.csr == err) { in port_err_clear()
174 writeq(mask.csr, &port_err->port_error); in port_err_clear()
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| H A D | ifpga_fme_iperf.c | 29 header.csr = readq(&iperf->header); in fme_iperf_get_revision()
42 ctl.csr = readq(&iperf->ch_ctl); in fme_iperf_get_cache_freeze()
58 ctl.csr = readq(&iperf->ch_ctl); in fme_iperf_set_cache_freeze()
60 writeq(ctl.csr, &iperf->ch_ctl); in fme_iperf_set_cache_freeze()
81 ctl.csr = readq(&iperf->ch_ctl); in read_cache_counter()
84 writeq(ctl.csr, &iperf->ch_ctl); in read_cache_counter()
96 ctr0.csr = readq(&iperf->ch_ctr0); in read_cache_counter()
97 ctr1.csr = readq(&iperf->ch_ctr1); in read_cache_counter()
132 ctl.csr = readq(&iperf->vtd_ctl); in fme_iperf_get_vtd_freeze()
149 ctl.csr = readq(&iperf->vtd_ctl); in fme_iperf_set_vtd_freeze()
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| H A D | ifpga_fme_pr.c | 15 fme_pr_status.csr = readq(&fme_pr->ccip_fme_pr_status); in pr_err_handle()
48 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
50 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
61 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
63 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
99 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write()
102 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write()
129 writeq(fme_pr_data.csr, in fme_pr_write()
160 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_complete()
254 fme_capability.csr = readq(&fme_hdr->capability); in fme_pr()
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| H A D | ifpga_fme.c | 68 (unsigned long long)fme_hdr->capability.csr); in fme_hdr_init()
86 header.csr = readq(&fme_hdr->header); in fme_hdr_get_revision()
98 fme_capability.csr = readq(&fme_hdr->capability); in fme_hdr_get_ports_num()
111 pt.csr = readq(&fme_hdr->port[port]); in fme_hdr_get_port_type()
240 tmp_threshold.csr = readq(&thermal->threshold); in fme_thermal_set_threshold1()
257 writeq(tmp_threshold.csr, &thermal->threshold); in fme_thermal_set_threshold1()
289 tmp_threshold.csr = readq(&thermal->threshold); in fme_thermal_set_threshold2()
420 header.csr = readq(&fme_thermal->header); in fme_thermal_get_revision()
522 pm_status.csr = readq(&fme_power->status); in fme_pwr_get_consumed()
640 pm_status.csr = readq(&fme_power->status); in fme_pwr_get_rtl()
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| H A D | ifpga_fme_dperf.c | 29 header.csr = readq(&dperf->header); in fme_dperf_get_revision()
42 ctl.csr = readq(&dperf->fab_ctl); in fabric_pobj_is_enabled()
66 ctl.csr = readq(&dperf->fab_ctl); in read_fabric_counter()
68 writeq(ctl.csr, &dperf->fab_ctl); in read_fabric_counter()
79 ctr.csr = readq(&dperf->fab_ctr); in read_fabric_counter()
138 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_set_fab_port_enable()
146 writeq(ctl.csr, &dperf->fab_ctl); in fme_dperf_set_fab_port_enable()
159 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_get_fab_freeze()
176 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_set_fab_freeze()
178 writeq(ctl.csr, &dperf->fab_ctl); in fme_dperf_set_fab_freeze()
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| H A D | ifpga_enumerate.c | 35 header.csr = readq(start); in feature_revision()
44 header.csr = readq(start); in feature_size()
54 header.csr = readq(start); in feature_id()
172 capability.csr = readq(&port_hdr->capability); in parse_feature_port_uafu()
211 header.csr = readq(&afu_hdr->csr); in parse_feature_afus()
382 header.csr = readq(hdr); in parse_feature_fiu()
399 fiu_header.csr = readq(&fiu_hdr->csr); in parse_feature_fiu()
493 header.csr = readq(hdr); in parse_feature_private()
513 header.csr = readq(hdr); in parse_feature()
548 header.csr = readq(hdr); in parse_feature_list()
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| H A D | ifpga_port.c | 59 header.csr = readq(&port_hdr->header); in port_get_revision()
74 capability.csr = readq(&port_hdr->capability); in port_get_portidx()
88 control.csr = readq(&port_hdr->control); in port_get_latency_tolerance()
103 status.csr = readq(&port_hdr->status); in port_get_ap1_event()
120 status.csr = readq(&port_hdr->status); in port_set_ap1_event()
122 writeq(status.csr, &port_hdr->status); in port_set_ap1_event()
137 status.csr = readq(&port_hdr->status); in port_get_ap2_event()
154 status.csr = readq(&port_hdr->status); in port_set_ap2_event()
156 writeq(status.csr, &port_hdr->status); in port_set_ap2_event()
171 status.csr = readq(&port_hdr->status); in port_get_power_state()
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| H A D | ifpga_port_error.c | 14 header.csr = readq(&port_err->header); in port_err_get_revision()
27 error.csr = readq(&port_err->port_error); in port_err_get_errors()
28 *val = error.csr; in port_err_get_errors()
40 first_error.csr = readq(&port_err->port_first_error); in port_err_get_first_error()
41 *val = first_error.csr; in port_err_get_first_error()
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| H A D | ifpga_compat.h | 44 value.csr = readq(_reg_addr); \
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| /dpdk/drivers/net/nfp/nfpcore/ |
| H A D | nfp_cpp_pcie_ops.c | 104 char *csr; member
257 bar->csr = nfp->cfg + in nfp_bar_write()
260 *(uint32_t *)(bar->csr) = newcfg; in nfp_bar_write()
328 bar->csr = nfp->cfg + in nfp_enable_bars()
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| /dpdk/drivers/raw/ifpga/ |
| H A D | ifpga_rawdev.c | 1262 fme_error0.csr = val; in fme_err_handle_error0()
1293 fme_catfatal.csr = val; in fme_err_handle_catfatal_error()
1322 nonfaterr.csr = val; in fme_err_handle_nonfaterror()
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