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Searched refs:cqe (Results 1 – 25 of 29) sorted by relevance

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/dpdk/drivers/net/mlx5/
H A Dmlx5_rx.c72 volatile struct mlx5_cqe *cqe; in rx_queue_count() local
93 op_own = cqe->op_own; in rx_queue_count()
287 pmc->addr = &cqe->op_own; in mlx5_get_monitor_addr()
419 volatile struct mlx5_cqe *cqe; in mlx5_rx_err_handle() member
621 op_own = cqe->op_own; in mlx5_rx_poll_len()
737 mark = cqe->sop_drop_qpn; in rxq_cq_to_mbuf()
825 rte_prefetch0(cqe); in mlx5_rx_burst()
865 if (cqe->lro_num_seg > 1) { in mlx5_rx_burst()
1096 cqe->wqe_counter : in mlx5_rx_burst_mprq()
1124 if (cqe->lro_num_seg > 1) { in mlx5_rx_burst_mprq()
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H A Dmlx5_flow_aso.c410 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], in mlx5_aso_dump_err_objs()
411 cqe[i + 2], cqe[i + 3]); in mlx5_aso_dump_err_objs()
429 volatile struct mlx5_err_cqe *cqe = in mlx5_aso_cqe_err_handle() local
530 volatile struct mlx5_cqe *restrict cqe; in mlx5_aso_completion_handle() local
544 cqe = &cq->cq_obj.cqes[idx]; in mlx5_aso_completion_handle()
545 ret = check_cqe(cqe, cq_size, cq->cq_ci); in mlx5_aso_completion_handle()
752 volatile struct mlx5_cqe *restrict cqe; in mlx5_aso_mtr_completion_handle() local
771 cqe = &cq->cq_obj.cqes[idx]; in mlx5_aso_mtr_completion_handle()
772 ret = check_cqe(cqe, cq_size, cq->cq_ci); in mlx5_aso_mtr_completion_handle()
1117 volatile struct mlx5_cqe *restrict cqe; in mlx5_aso_ct_completion_handle() local
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H A Dmlx5_txpp.c529 uint64_t *cqe = (uint64_t *)from; in mlx5_atomic_read_cqe()
540 tm = __atomic_load_n(cqe + 0, __ATOMIC_RELAXED); in mlx5_atomic_read_cqe()
541 op = __atomic_load_n(cqe + 1, __ATOMIC_RELAXED); in mlx5_atomic_read_cqe()
543 if (tm != __atomic_load_n(cqe + 0, __ATOMIC_RELAXED)) in mlx5_atomic_read_cqe()
545 if (op != __atomic_load_n(cqe + 1, __ATOMIC_RELAXED)) in mlx5_atomic_read_cqe()
582 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128); in mlx5_txpp_update_timestamp()
655 volatile struct mlx5_cqe *cqe; in mlx5_txpp_handle_rearm_queue() local
657 cqe = &wq->cq_obj.cqes[cq_ci & (MLX5_TXPP_REARM_CQ_SIZE - 1)]; in mlx5_txpp_handle_rearm_queue()
658 ret = check_cqe(cqe, MLX5_TXPP_REARM_CQ_SIZE, cq_ci); in mlx5_txpp_handle_rearm_queue()
990 struct mlx5_cqe *cqe = in mlx5_txpp_read_clock() local
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H A Dmlx5_tx.c191 volatile struct mlx5_cqe *cqe; in mlx5_tx_handle_completion() local
193 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m]; in mlx5_tx_handle_completion()
194 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci); in mlx5_tx_handle_completion()
209 (txq, (volatile struct mlx5_err_cqe *)cqe); in mlx5_tx_handle_completion()
233 cqe->wqe_counter); in mlx5_tx_handle_completion()
237 last_cqe = cqe; in mlx5_tx_handle_completion()
H A Dmlx5_txq.c146 volatile struct mlx5_cqe *cqe; in txq_sync_cq() local
151 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m]; in txq_sync_cq()
152 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci); in txq_sync_cq()
164 cqe = &txq->cqes[i]; in txq_sync_cq()
165 cqe->op_own = MLX5_CQE_INVALIDATE; in txq_sync_cq()
H A Dmlx5_rxq.c428 volatile struct mlx5_cqe *cqe; in rxq_sync_cq() local
433 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask]; in rxq_sync_cq()
434 ret = check_cqe(cqe, cqe_n, rxq->cq_ci); in rxq_sync_cq()
442 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) { in rxq_sync_cq()
447 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt); in rxq_sync_cq()
452 cqe = &(*rxq->cqes)[i]; in rxq_sync_cq()
453 cqe->op_own = MLX5_CQE_INVALIDATE; in rxq_sync_cq()
/dpdk/drivers/net/mlx4/
H A Dmlx4_rxtx.c309 volatile struct mlx4_cqe *cqe; in mlx4_txq_complete() local
331 (volatile struct mlx4_err_cqe *)cqe; in mlx4_txq_complete()
1154 flags = (rte_be_to_cpu_32(cqe->status) & in mlx4_cqe_flags()
1157 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) & in mlx4_cqe_flags()
1180 volatile struct mlx4_cqe *cqe = NULL; in mlx4_cq_poll_one() local
1195 ret = rte_be_to_cpu_32(cqe->byte_cnt); in mlx4_cq_poll_one()
1198 *out = cqe; in mlx4_cq_poll_one()
1228 volatile struct mlx4_cqe *cqe; in mlx4_rx_burst() local
1261 len = mlx4_cq_poll_one(rxq, &cqe); in mlx4_rx_burst()
1278 pkt->hash.rss = cqe->immed_rss_invalid; in mlx4_rx_burst()
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H A Dmlx4_glue.c123 mlx4_glue_create_cq(struct ibv_context *context, int cqe, void *cq_context, in mlx4_glue_create_cq() argument
126 return ibv_create_cq(context, cqe, cq_context, channel, comp_vector); in mlx4_glue_create_cq()
H A Dmlx4_glue.h50 struct ibv_cq *(*create_cq)(struct ibv_context *context, int cqe,
/dpdk/drivers/compress/mlx5/
H A Dmlx5_compress.c535 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, in mlx5_compress_dump_err_objs() argument
542 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], in mlx5_compress_dump_err_objs()
543 cqe[i + 2], cqe[i + 3]); in mlx5_compress_dump_err_objs()
559 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) in mlx5_compress_cqe_err_handle() local
581 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); in mlx5_compress_cqe_err_handle()
582 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, in mlx5_compress_cqe_err_handle()
594 volatile struct mlx5_cqe *restrict cqe; in mlx5_compress_dequeue_burst() local
613 cqe = &qp->cq.cqes[idx]; in mlx5_compress_dequeue_burst()
614 ret = check_cqe(cqe, cq_size, qp->ci); in mlx5_compress_dequeue_burst()
628 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); in mlx5_compress_dequeue_burst()
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/dpdk/drivers/net/qede/
H A Dqede_rxtx.c1369 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0])); in qede_rx_process_tpa_cont_cqe()
1372 cqe->len_list[0]); in qede_rx_process_tpa_cont_cqe()
1383 cqe->len_list[0]); in qede_rx_process_tpa_end_cqe()
1387 rx_mb->nb_segs = cqe->num_of_bds; in qede_rx_process_tpa_end_cqe()
1391 " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason, in qede_rx_process_tpa_end_cqe()
1521 union eth_rx_cqe *cqe; in qede_recv_pkts_regular() local
1579 cqe = in qede_recv_pkts_regular()
1744 union eth_rx_cqe *cqe; in qede_recv_pkts() local
1805 cqe = in qede_recv_pkts()
2734 orig_cqe = cqe;
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/dpdk/drivers/regex/mlx5/
H A Dmlx5_regex_fastpath.c487 volatile struct mlx5_cqe *cqe; in poll_one() local
491 cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset); in poll_one()
494 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); in poll_one()
504 return cqe; in poll_one()
530 volatile struct mlx5_cqe *cqe; in mlx5_regexdev_dequeue() local
533 while ((cqe = poll_one(cq))) { in mlx5_regexdev_dequeue()
535 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & in mlx5_regexdev_dequeue()
537 size_t hw_qpid = cqe->user_index_bytes[2]; in mlx5_regexdev_dequeue()
/dpdk/drivers/event/cnxk/
H A Dcn10k_worker.h160 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0]; in cn10k_process_vwqe() local
163 mbuf = (struct rte_mbuf *)((char *)cqe - in cn10k_process_vwqe()
171 const uint64_t cq_w1 = *((const uint64_t *)cqe + 1); in cn10k_process_vwqe()
172 const uint64_t cq_w5 = *((const uint64_t *)cqe + 5); in cn10k_process_vwqe()
179 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem, in cn10k_process_vwqe()
182 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) + in cn10k_process_vwqe()
/dpdk/drivers/net/qede/base/
H A Decore_sp_api.h41 struct eth_slow_path_rx_cqe *cqe);
H A Decore_spq.c480 *cqe, in ecore_cqe_completion()
484 return OSAL_VF_CQE_COMPLETION(p_hwfn, cqe, protocol); in ecore_cqe_completion()
490 return ecore_spq_completion(p_hwfn, cqe->echo, 0, OSAL_NULL); in ecore_cqe_completion()
494 struct eth_slow_path_rx_cqe *cqe) in ecore_eth_cqe_completion() argument
498 rc = ecore_cqe_completion(p_hwfn, cqe, PROTOCOLID_ETH); in ecore_eth_cqe_completion()
502 cqe->ramrod_cmd_id); in ecore_eth_cqe_completion()
H A Deth_common.h513 union eth_rx_cqe cqe /* CQE data itself */; member
/dpdk/drivers/net/hinic/
H A Dhinic_pmd_rx.c995 struct hinic_rq_cqe cqe; in hinic_recv_pkts() local
1012 hinic_rq_cqe_be_to_cpu32(&cqe, (volatile void *)rx_cqe); in hinic_recv_pkts()
1013 vlan_len = cqe.vlan_len; in hinic_recv_pkts()
1047 offload_type = cqe.offload_type; in hinic_recv_pkts()
1054 rxm->ol_flags |= hinic_rx_csum(cqe.status, rxq); in hinic_recv_pkts()
1057 rss_hash = cqe.rss_hash; in hinic_recv_pkts()
1062 lro_num = HINIC_GET_RX_NUM_LRO(cqe.status); in hinic_recv_pkts()
/dpdk/drivers/dma/hisilicon/
H A Dhisi_dmadev.c299 hw->cqe = (void *)((char *)iomz->addr + sq_size); in hisi_dma_alloc_iomem()
318 hw->cqe = NULL; in hisi_dma_free_iomem()
631 volatile struct hisi_dma_cqe *cqe; in hisi_dma_scan_cq() local
638 cqe = &hw->cqe[cq_head]; in hisi_dma_scan_cq()
639 misc = cqe->misc; in hisi_dma_scan_cq()
H A Dhisi_dmadev.h189 volatile struct hisi_dma_cqe *cqe; member
/dpdk/drivers/common/mlx5/
H A Dmlx5_common_devx.c41 volatile struct mlx5_cqe *cqe = cq_obj->cqes; in mlx5_cq_init() local
44 for (i = 0; i < cq_size; i++, cqe++) in mlx5_cq_init()
45 cqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK; in mlx5_cq_init()
H A Dmlx5_common.h195 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, in check_cqe() argument
199 const uint8_t op_own = cqe->op_own; in check_cqe()
/dpdk/drivers/crypto/mlx5/
H A Dmlx5_crypto.c475 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) in mlx5_crypto_cqe_err_handle() local
480 DRV_LOG(ERR, "CQE ERR:%x.\n", rte_be_to_cpu_32(cqe->syndrome)); in mlx5_crypto_cqe_err_handle()
488 volatile struct mlx5_cqe *restrict cqe; in mlx5_crypto_dequeue_burst() local
504 cqe = &qp->cq_obj.cqes[idx]; in mlx5_crypto_dequeue_burst()
505 ret = check_cqe(cqe, cq_size, qp->ci); in mlx5_crypto_dequeue_burst()
/dpdk/drivers/net/ena/base/
H A Dena_com.c451 struct ena_admin_acq_entry *cqe) in ena_com_handle_single_admin_completion() argument
456 cmd_id = cqe->acq_common_descriptor.command & in ena_com_handle_single_admin_completion()
468 comp_ctx->comp_status = cqe->acq_common_descriptor.status; in ena_com_handle_single_admin_completion()
471 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); in ena_com_handle_single_admin_completion()
479 struct ena_admin_acq_entry *cqe = NULL; in ena_com_handle_admin_completion() local
487 cqe = &admin_queue->cq.entries[head_masked]; in ena_com_handle_admin_completion()
490 while ((READ_ONCE8(cqe->acq_common_descriptor.flags) & in ena_com_handle_admin_completion()
496 ena_com_handle_single_admin_completion(admin_queue, cqe); in ena_com_handle_admin_completion()
505 cqe = &admin_queue->cq.entries[head_masked]; in ena_com_handle_admin_completion()
/dpdk/drivers/net/mlx5/linux/
H A Dmlx5_verbs.c163 .cqe = cqe_n, in mlx5_rxq_ibv_cq_create()
195 cq_attr.ibv.cqe *= 2; in mlx5_rxq_ibv_cq_create()
1125 .cqe = 1, in mlx5_rxq_ibv_obj_dummy_lb_create()
/dpdk/drivers/common/mlx5/linux/
H A Dmlx5_glue.h174 struct ibv_cq *(*create_cq)(struct ibv_context *context, int cqe,

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