1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #include <rte_atomic.h>
6 #include <rte_bus_pci.h>
7 #include <rte_common.h>
8 #include <rte_devargs.h>
9 #include <rte_eal.h>
10 #include <rte_io.h>
11 #include <rte_kvargs.h>
12 #include <rte_malloc.h>
13 #include <rte_mbuf_pool_ops.h>
14 #include <rte_pci.h>
15
16 #include "roc_api.h"
17
18 #define CNXK_NPA_DEV_NAME RTE_STR(cnxk_npa_dev_)
19 #define CNXK_NPA_DEV_NAME_LEN (sizeof(CNXK_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)
20 #define CNXK_NPA_MAX_POOLS_PARAM "max_pools"
21
22 static inline uint32_t
npa_aura_size_to_u32(uint8_t val)23 npa_aura_size_to_u32(uint8_t val)
24 {
25 if (val == NPA_AURA_SZ_0)
26 return 128;
27 if (val >= NPA_AURA_SZ_MAX)
28 return BIT_ULL(20);
29
30 return 1 << (val + 6);
31 }
32
33 static int
parse_max_pools_handler(const char * key,const char * value,void * extra_args)34 parse_max_pools_handler(const char *key, const char *value, void *extra_args)
35 {
36 RTE_SET_USED(key);
37 uint32_t val;
38
39 val = rte_align32pow2(atoi(value));
40 if (val < npa_aura_size_to_u32(NPA_AURA_SZ_128))
41 val = 128;
42 if (val > npa_aura_size_to_u32(NPA_AURA_SZ_1M))
43 val = BIT_ULL(20);
44
45 *(uint32_t *)extra_args = val;
46 return 0;
47 }
48
49 static inline uint32_t
parse_max_pools(struct rte_devargs * devargs)50 parse_max_pools(struct rte_devargs *devargs)
51 {
52 uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128);
53 struct rte_kvargs *kvlist;
54
55 if (devargs == NULL)
56 goto exit;
57 kvlist = rte_kvargs_parse(devargs->args, NULL);
58 if (kvlist == NULL)
59 goto exit;
60
61 rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM,
62 &parse_max_pools_handler, &max_pools);
63 rte_kvargs_free(kvlist);
64 exit:
65 return max_pools;
66 }
67
68 static int
cnxk_mempool_plt_parse_devargs(struct rte_pci_device * pci_dev)69 cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev)
70 {
71 roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs));
72 return 0;
73 }
74
75 static inline char *
npa_dev_to_name(struct rte_pci_device * pci_dev,char * name)76 npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)
77 {
78 snprintf(name, CNXK_NPA_DEV_NAME_LEN, CNXK_NPA_DEV_NAME PCI_PRI_FMT,
79 pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid,
80 pci_dev->addr.function);
81
82 return name;
83 }
84
85 static int
npa_init(struct rte_pci_device * pci_dev)86 npa_init(struct rte_pci_device *pci_dev)
87 {
88 char name[CNXK_NPA_DEV_NAME_LEN];
89 const struct rte_memzone *mz;
90 struct roc_npa *dev;
91 int rc = -ENOMEM;
92
93 mz = rte_memzone_reserve_aligned(npa_dev_to_name(pci_dev, name),
94 sizeof(*dev), SOCKET_ID_ANY, 0,
95 RTE_CACHE_LINE_SIZE);
96 if (mz == NULL)
97 goto error;
98
99 dev = mz->addr;
100 dev->pci_dev = pci_dev;
101
102 rc = roc_npa_dev_init(dev);
103 if (rc)
104 goto mz_free;
105
106 return 0;
107
108 mz_free:
109 rte_memzone_free(mz);
110 error:
111 plt_err("failed to initialize npa device rc=%d", rc);
112 return rc;
113 }
114
115 static int
npa_fini(struct rte_pci_device * pci_dev)116 npa_fini(struct rte_pci_device *pci_dev)
117 {
118 char name[CNXK_NPA_DEV_NAME_LEN];
119 const struct rte_memzone *mz;
120 int rc;
121
122 mz = rte_memzone_lookup(npa_dev_to_name(pci_dev, name));
123 if (mz == NULL)
124 return -EINVAL;
125
126 rc = roc_npa_dev_fini(mz->addr);
127 if (rc) {
128 if (rc != -EAGAIN)
129 plt_err("Failed to remove npa dev, rc=%d", rc);
130 return rc;
131 }
132 rte_memzone_free(mz);
133
134 return 0;
135 }
136
137 static int
npa_remove(struct rte_pci_device * pci_dev)138 npa_remove(struct rte_pci_device *pci_dev)
139 {
140 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
141 return 0;
142
143 return npa_fini(pci_dev);
144 }
145
146 static int
npa_probe(struct rte_pci_driver * pci_drv,struct rte_pci_device * pci_dev)147 npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
148 {
149 int rc;
150
151 RTE_SET_USED(pci_drv);
152
153 rc = roc_plt_init();
154 if (rc < 0)
155 return rc;
156
157 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
158 return 0;
159
160 return npa_init(pci_dev);
161 }
162
163 static const struct rte_pci_id npa_pci_map[] = {
164 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_PF),
165 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_PF),
166 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_PF),
167 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_PF),
168 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_PF),
169 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_NPA_PF),
170 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_PF),
171 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_VF),
172 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_VF),
173 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_VF),
174 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_VF),
175 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_VF),
176 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_NPA_VF),
177 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_VF),
178 {
179 .vendor_id = 0,
180 },
181 };
182
183 static struct rte_pci_driver npa_pci = {
184 .id_table = npa_pci_map,
185 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
186 .probe = npa_probe,
187 .remove = npa_remove,
188 };
189
190 RTE_PMD_REGISTER_PCI(mempool_cnxk, npa_pci);
191 RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map);
192 RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci");
193 RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk,
194 CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>");
195
RTE_INIT(cnxk_mempool_parse_devargs)196 RTE_INIT(cnxk_mempool_parse_devargs)
197 {
198 roc_npa_lf_init_cb_register(cnxk_mempool_plt_parse_devargs);
199 }
200