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Searched refs:clock (Results 1 – 23 of 23) sorted by relevance

/dpdk/drivers/net/cnxk/
H A Dcnxk_ptp.c8 cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock) in cnxk_nix_read_clock() argument
19 *clock = (rte_get_tsc_cycles() + dev->clk_delta) * dev->clk_freq_mult; in cnxk_nix_read_clock()
80 uint64_t clock, ns; in cnxk_nix_timesync_read_time() local
83 rc = roc_nix_ptp_clock_read(nix, &clock, NULL, false); in cnxk_nix_timesync_read_time()
87 ns = rte_timecounter_update(&dev->systime_tc, clock); in cnxk_nix_timesync_read_time()
H A Dcnxk_ethdev.h554 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
/dpdk/doc/guides/sample_app_ug/
H A Dptpclient.rst8 example of using the DPDK IEEE1588 API to communicate with a PTP master clock
27 * Only the slave clock is implemented.
51 synchronizes the PTP PHC clock with the Linux kernel clock.
74 * ``-T 0``: Update only the PTP slave clock.
75 * ``-T 1``: Update the PTP slave clock and synchronize the Linux Kernel to the PTP clock.
197 …hen we parse the *DELAY RESPONSE* packet, and all conditions are met we adjust the PTP slave clock.
H A Dintro.rst88 master clock to synchronize time on a Network Interface Card (NIC) using the
/dpdk/drivers/common/cnxk/
H A Droc_nix_ptp.c52 roc_nix_ptp_clock_read(struct roc_nix *roc_nix, uint64_t *clock, uint64_t *tsc, in roc_nix_ptp_clock_read() argument
69 if (clock) in roc_nix_ptp_clock_read()
70 *clock = rsp->clk; in roc_nix_ptp_clock_read()
H A Droc_nix.h861 int __roc_api roc_nix_ptp_clock_read(struct roc_nix *roc_nix, uint64_t *clock,
/dpdk/doc/guides/prog_guide/
H A Dprofile_app.rst70 get a wall clock counter in user space. Typically it runs at a lower clock frequency than the CPU c…
71 Cycles counted using this method should be scaled to CPU clock frequency.
78 clock counter is through the ARMv8 PMU subsystem. The PMU cycle counter runs
/dpdk/drivers/common/mlx5/windows/
H A Dmlx5_glue.c290 struct mlx5_devx_clock *clock; in mlx5_glue_query_rt_values() local
298 clock = (struct mlx5_devx_clock *)devx_clock; in mlx5_glue_query_rt_values()
301 &clock->p_iseg_internal_timer, in mlx5_glue_query_rt_values()
302 &clock->clock_frequency_hz, in mlx5_glue_query_rt_values()
303 &clock->is_stable_clock_frequency); in mlx5_glue_query_rt_values()
/dpdk/doc/guides/eventdevs/
H A Dcnxk.rst167 - ``TIM external clock frequency``
169 The ``tim_eclk_freq`` devagrs can be used to pass external clock frequencies
170 when external clock source is selected.
172 External clock frequencies are mapped as follows::
H A Docteontx.rst94 When timvf is used as Event timer adapter the clock source mapping is as
/dpdk/drivers/net/mlx5/windows/
H A Dmlx5_ethdev_os.c389 mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock) in mlx5_read_clock() argument
401 *clock = *(uint64_t volatile *)mlx5_clock.p_iseg_internal_timer; in mlx5_read_clock()
/dpdk/drivers/raw/ifpga/base/
H A Difpga_fme_dperf.c9 static int fme_dperf_get_clock(struct ifpga_fme_hw *fme, u64 *clock) in fme_dperf_get_clock() argument
18 *clock = clk.afu_interf_clock; in fme_dperf_get_clock()
H A Dopae_spi.h58 u16 clock:10; member
H A Difpga_fme_iperf.c9 static int fme_iperf_get_clock(struct ifpga_fme_hw *fme, u64 *clock) in fme_iperf_get_clock() argument
18 *clock = clk.afu_interf_clock; in fme_iperf_get_clock()
H A Dopae_spi.c296 spi_dev->spi_param.clock, in altera_spi_init()
/dpdk/doc/guides/rel_notes/
H A Drelease_16_04.rst320 The MDIO clock speed must be reconfigured after the MAC reset. The MDIO clock
322 The driver now set the MDIO clock speed prior to initializing PHY ops and
/dpdk/drivers/net/mlx5/linux/
H A Dmlx5_ethdev_os.c325 mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock) in mlx5_read_clock() argument
338 *clock = values.raw_clock.tv_nsec; in mlx5_read_clock()
/dpdk/doc/guides/platform/
H A Dcnxk.rst457 CPT clock count pc 5579867595493
/dpdk/lib/ethdev/
H A Drte_ethdev.c5251 rte_eth_read_clock(uint16_t port_id, uint64_t *clock) in rte_eth_read_clock() argument
5258 if (clock == NULL) { in rte_eth_read_clock()
5265 return eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock)); in rte_eth_read_clock()
H A Drte_ethdev.h5087 rte_eth_read_clock(uint16_t port_id, uint64_t *clock);
/dpdk/drivers/net/mlx5/
H A Dmlx5.h1664 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
/dpdk/doc/guides/nics/
H A Dbnxt.rst541 clock using DPDK IEEE1588 APIs. Note that the PTP client application needs to
/dpdk/doc/guides/testpmd_app_ug/
H A Dtestpmd_funcs.rst837 to configure delay (in unspecified device clock units) between bursts
844 * ``inter`` is the delay between the bursts in the device clock units.
853 in the device clock units. The number of packets in the burst is defined
860 and is supposed to be engaged to get the current device clock value