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Searched refs:chip (Results 1 – 25 of 29) sorted by relevance

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/dpdk/drivers/common/cnxk/
H A Droc_bphy_irq.c235 mz = plt_memzone_lookup(chip->mz_name); in roc_bphy_irq_handler_set()
239 sizeof(chip)); in roc_bphy_irq_handler_set()
293 chip->irq_vecs[irq_num].handler = isr; in roc_bphy_irq_handler_set()
298 chip->irq_vecs[irq_num].handler = NULL; in roc_bphy_irq_handler_set()
301 chip->n_handlers++; in roc_bphy_irq_handler_set()
334 if (chip == NULL) in roc_bphy_intr_clear()
342 mz = plt_memzone_lookup(chip->mz_name); in roc_bphy_intr_clear()
367 chip->n_handlers--; in roc_bphy_intr_clear()
368 chip->irq_vecs[irq_num].isr_data = NULL; in roc_bphy_intr_clear()
369 chip->irq_vecs[irq_num].handler = NULL; in roc_bphy_intr_clear()
[all …]
H A Droc_bphy_irq.h38 __roc_api int roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num);
/dpdk/drivers/net/cxgbe/base/
H A Dt4_chip_type.h46 static inline int is_t4(enum chip_type chip) in is_t4() argument
48 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4()
51 static inline int is_t5(enum chip_type chip) in is_t5() argument
53 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
56 static inline int is_t6(enum chip_type chip) in is_t6() argument
58 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
H A Dt4_hw.c2739 CHELSIO_CHIP_RELEASE(adapter->params.chip)); in t4_dump_version_info()
3048 (is_t4(adap->params.chip) ? \ in t4_get_port_stats()
3170 if (is_t4(adap->params.chip)) in t4_clr_port_stats()
3517 if (is_t4(adap->params.chip) || is_t4(chip_compat)) in t4_fixup_host_params_compat()
3596 if (is_t5(adap->params.chip)) in t4_fixup_host_params_compat()
4911 enum chip_type chip = 0; in t4_get_chip_type() local
4917 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); in t4_get_chip_type()
4920 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); in t4_get_chip_type()
4928 return chip; in t4_get_chip_type()
4957 adapter->params.chip = 0; in t4_prep_adapter()
[all …]
H A Dt4vf_hw.c96 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4vf_wr_mbox_core()
315 adapter->params.chip = 0; in t4vf_prep_adapter()
318 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, in t4vf_prep_adapter()
325 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, in t4vf_prep_adapter()
476 return (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4vf_get_pf_from_vf()
H A Dcommon.h257 enum chip_type chip; /* chip code */ member
/dpdk/drivers/net/cxgbe/
H A Dcxgbe_filter.c26 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { in cxgbe_init_hash_filter()
243 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6) in cxgbe_filter_slots()
500 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { in mk_act_open_req6()
552 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { in mk_act_open_req()
944 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); in cxgbe_del_filter()
1017 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); in cxgbe_set_filter()
1321 if (is_t5(adapter->params.chip)) { in cxgbe_get_filter_count()
1346 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) { in cxgbe_get_filter_count()
1403 if (is_t5(adapter->params.chip)) in cxgbe_clear_filter_count()
H A Dcxgbe_main.c739 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, in cxgbe_print_port_info()
1021 if (is_t6(adapter->params.chip)) { in configure_pcie_ext_tag()
1433 is_t6(adap->params.chip)) { in adap_init0()
1439 if (is_t4(adap->params.chip)) { in adap_init0()
1481 if (is_t4(adap->params.chip)) { in adap_init0()
2076 int chip; in cxgbe_probe() local
2079 chip = t4_get_chip_type(adapter, in cxgbe_probe()
2081 if (chip < 0) in cxgbe_probe()
2082 return chip; in cxgbe_probe()
2084 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? in cxgbe_probe()
[all …]
H A Dsge.c248 if (is_t4(adap->params.chip)) in ring_fl_db()
680 static u64 hwcsum(enum chip_type chip, const struct rte_mbuf *m) in hwcsum() argument
703 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) in hwcsum()
974 cntrl = hwcsum(adap->params.chip, mbuf) | in tx_do_packet_coalesce()
1157 cntrl = hwcsum(adap->params.chip, m) | in t4_eth_xmit()
1184 if (is_t4(adap->params.chip)) in t4_eth_xmit()
1190 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_eth_xmit()
1823 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_sge_alloc_rxq()
1932 if (is_pf4(adap) && !is_t4(adap->params.chip) && cong >= 0) { in t4_sge_alloc_rxq()
2402 if (is_t4(adap->params.chip) || adap->use_unpacked_mode) in t4_sge_init()
[all …]
H A Dsmt.c43 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) { in write_smt_entry()
H A Dcxgbevf_main.c186 if (!is_t4(adapter->params.chip)) { in cxgbevf_probe()
H A Dcxgbe_ethdev.c1446 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | in cxgbe_get_regs()
1447 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | in cxgbe_get_regs()
/dpdk/doc/guides/freebsd_gsg/
H A Dbuild_dpdk.rst186 ix0@pci0:1:0:0: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00
187 ix1@pci0:1:0:1: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00
188 ix2@pci0:2:0:0: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00
189 ix3@pci0:2:0:1: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_hwdev.c908 err_level = event->event.chip.err_level; in fault_report_show()
921 event->event.chip.func_id); in fault_report_show()
924 event->event.chip.node_id); in fault_report_show()
926 event->event.chip.err_type); in fault_report_show()
928 event->event.chip.err_csr_addr); in fault_report_show()
930 event->event.chip.err_csr_value); in fault_report_show()
H A Dhinic_pmd_hwdev.h185 } chip; member
/dpdk/doc/guides/compressdevs/
H A Dmlx5.rst20 These engines are part of the ARM complex of the BlueField chip, and as
/dpdk/doc/guides/cryptodevs/
H A Dcaam_jr.rst97 of QorIQ® ARM-Architecture-based system on chip (SoC) processors
/dpdk/doc/guides/nics/
H A Denetc.rst102 of QorIQ® ARM-Architecture-based system on chip (SoC) processors
H A Dpfe.rst140 of QorIQ® ARM-Architecture-based system on chip (SoC) processors
H A Dnfp.rst139 to use specific registers inside the chip, the number of secondary processes with PF
H A Dhns3.rst44 - Get the information about Kunpeng920 chip using
H A Dcxgbe.rst725 t5nex0@pci0:2:0:4: class=0x020000 card=0x00001425 chip=0x54011425 rev=0x00
/dpdk/doc/guides/platform/
H A Ddpaa2.rst88 of QorIQ® ARM-Architecture-based system on chip (SoC) processors
H A Ddpaa.rst90 of QorIQ® ARM-Architecture-based system on chip (SoC) processors
/dpdk/doc/guides/rawdevs/
H A Dcnxk_bphy.rst10 backed by ethernet I/O block called CGX or RPM (depending on the chip version).

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