Home
last modified time | relevance | path

Searched refs:channels (Results 1 – 25 of 39) sorted by relevance

12

/dpdk/examples/vm_power_manager/
H A Dchannel_manager.c53 struct channel_info *channels[RTE_MAX_LCORE]; member
342 vm_info->channels[channel_num] = chan_info; in setup_channel_info()
667 vm_info->channels[i]->status = status; in set_channel_status_all()
793 vm_info->channels[i]->channel_path, in get_info_vm()
795 info->channels[channel_num].status = in get_info_vm()
796 vm_info->channels[i]->status; in get_info_vm()
797 info->channels[channel_num].fd = in get_info_vm()
798 vm_info->channels[i]->fd; in get_info_vm()
1019 vm_info->channels[i]); in channel_manager_exit()
1020 close(vm_info->channels[i]->fd); in channel_manager_exit()
[all …]
H A Dchannel_manager.h75 struct channel_info channels[RTE_MAX_LCORE]; /**< channel_info array */ member
H A Dvm_power_cli.c76 info.channels[i].channel_path); in cmd_show_vm_parsed()
77 switch (info.channels[i].status) { in cmd_show_vm_parsed()
/dpdk/doc/guides/prog_guide/
H A Dmempool_lib.rst13 …nment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.
33 …ach object starts on a different channel and rank in memory so that all channels are equally loade…
36 …formance can be increased by spreading the start addresses of objects among the different channels.
42 …n, the EAL command line options provide the ability to add the number of memory channels and ranks.
46 The command line must always have the number of memory channels specified for the processor.
60 The Intel® 5520 chipset has three channels, so in most cases,
H A Ddmadev.rst26 * The DMA controller could have multiple hardware DMA channels (aka. hardware
28 * The dmadev could create multiple virtual DMA channels, each virtual DMA
45 ``rte_dma_pmd_allocate`` based on the number of hardware DMA channels.
H A Dvhost_lib.rst110 queues. Vhost leverages the registered DMA channels to free CPU from
436 the flexibility for applications to dynamically use DMA channels in
440 channels. Specifically, one vring can use multiple different DMA channels
442 The reason of enabling one vring to use multiple DMA channels is that
444 the same vring with their own DMA virtual channels. Besides, the number
446 support sharing DMA channels among vrings.
H A Dwriting_efficient_code.rst73 Modern memory controllers have several memory channels that can load or store data in parallel.
75 the number of channels and the way the memory is distributed across the channels varies.
79 …e :ref:`Mempool Library <Mempool_Library>` spreads the addresses of objects among memory channels.
H A Doverview.rst114 …d an alignment helper to ensure that objects are padded to spread them equally on all RAM channels.
/dpdk/doc/guides/sample_app_ug/
H A Dvm_power_management.rst83 - CLI: For adding VM channels to monitor, inspecting and changing channel
91 communications channels between the host and VMs in the form of a
99 where each VM can have several channels up to a maximum of 64 per VM. In this
188 Configure ``virtio-serial`` channels using ``libvirt`` XML.
204 channels can be associated with a single controller, and multiple
278 cores 0 and 1 on a system with four memory channels, issue the command:
298 unique identifier to associate channels with a particular VM and for
311 Add communication channels for the specified VM using the following
312 command. The ``virtio`` channels must be enabled in the VM configuration
315 ``all`` attempts to add all channels for the VM:
[all …]
H A Ddma.rst55 * q NQ: Number of Rx queues used per port equivalent to DMA channels
154 multiple DMA channels per port:
265 mode the user chose, it will enqueue packets to DMA channels and
/dpdk/doc/guides/rawdevs/
H A Difpga.rst96 Each FPGA can provide many channels to PR AFU by software, each channels
/dpdk/drivers/net/netvsc/
H A Dhn_var.h183 struct vmbus_channel *channels[HN_MAX_CHANNELS]; member
193 return hv->channels[0]; in hn_primary_chan()
H A Dhn_ethdev.c547 hv->channels[chn_index] = new_sc; in hn_subchan_configure()
1200 err = rte_vmbus_chan_open(vmbus, &hv->channels[0]); in eth_hn_dev_init()
1204 rte_vmbus_set_latency(hv->vmbus, hv->channels[0], hv->latency); in eth_hn_dev_init()
/dpdk/doc/guides/dmadevs/
H A Dhisilicon.rst9 The DMA PF function supports multiple DMA channels.
/dpdk/drivers/net/sfc/
H A Dsfc_rx.c740 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; in sfc_rx_default_rxq_set_filter()
1218 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 && in sfc_rx_qinit()
1521 if (rss->channels > 0) { in sfc_rx_rss_config()
1830 rss->channels = (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) ? in sfc_rx_configure()
1833 if (rss->channels > 0) { in sfc_rx_configure()
1838 rss->tbl[sw_index] = sw_index % rss->channels; in sfc_rx_configure()
1878 rss->channels = 0; in sfc_rx_close()
H A Dsfc.h111 unsigned int channels; member
H A Dsfc_ethdev.c1686 if (rss->channels == 0) { in sfc_dev_rss_hash_update()
1773 if (rss->channels == 0) in sfc_dev_rss_reta_query()
1810 if (rss->channels == 0) { in sfc_dev_rss_reta_update()
1836 if (grp->reta[grp_idx] >= rss->channels) { in sfc_dev_rss_reta_update()
/dpdk/doc/guides/linux_gsg/
H A Deal_args.include.rst98 * ``-n <number of channels>``
100 Set the number of memory channels to use.
H A Dbuild_sample_apps.rst48 Number of memory channels per processor socket.
114 (assuming the platform has four memory channels per processor socket,
H A Dnic_perf_intel_platform.rst40 The sample output above shows a total of 8 channels, from ``A`` to ``H``, where each channel has 2 …
/dpdk/doc/guides/eventdevs/
H A Ddpaa.rst47 The dpaa eventdev is exposed as a vdev device which consists of a set of channels
/dpdk/drivers/baseband/la12xx/
H A Dbbdev_la12xx_ipc.h183 ipc_channel_us_t *channels[IPC_MAX_CHANNEL_COUNT]; member
/dpdk/drivers/net/af_xdp/
H A Drte_eth_af_xdp.c1618 struct ethtool_channels channels; in xdp_get_channels_info() local
1626 channels.cmd = ETHTOOL_GCHANNELS; in xdp_get_channels_info()
1627 ifr.ifr_data = (void *)&channels; in xdp_get_channels_info()
1639 if (channels.max_combined == 0 || errno == EOPNOTSUPP) { in xdp_get_channels_info()
1646 *max_queues = channels.max_combined; in xdp_get_channels_info()
1647 *combined_queues = channels.combined_count; in xdp_get_channels_info()
/dpdk/doc/guides/nics/
H A Dthunderx.rst229 The loopback block has N channels and contains data buffering that is shared across
230 all channels. Four primary VFs are reserved as loopback ports.
/dpdk/doc/guides/platform/
H A Dcnxk.rst103 The loopback block has N channels and contains data buffering that is shared across
104 all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0's

12