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Searched refs:channel (Results 1 – 25 of 59) sorted by relevance

123

/dpdk/drivers/net/mlx4/
H A Dmlx4_glue.c117 mlx4_glue_destroy_comp_channel(struct ibv_comp_channel *channel) in mlx4_glue_destroy_comp_channel() argument
119 return ibv_destroy_comp_channel(channel); in mlx4_glue_destroy_comp_channel()
124 struct ibv_comp_channel *channel, int comp_vector) in mlx4_glue_create_cq() argument
126 return ibv_create_cq(context, cqe, cq_context, channel, comp_vector); in mlx4_glue_create_cq()
136 mlx4_glue_get_cq_event(struct ibv_comp_channel *channel, struct ibv_cq **cq, in mlx4_glue_get_cq_event() argument
139 return ibv_get_cq_event(channel, cq, cq_context); in mlx4_glue_get_cq_event()
H A Dmlx4_glue.h49 int (*destroy_comp_channel)(struct ibv_comp_channel *channel);
52 struct ibv_comp_channel *channel,
55 int (*get_cq_event)(struct ibv_comp_channel *channel,
H A Dmlx4_intr.c83 if (!rxq || !rxq->channel) { in mlx4_rx_intr_vec_enable()
104 rxq->channel->fd)) in mlx4_rx_intr_vec_enable()
333 if (!rxq || !rxq->channel) { in mlx4_rx_intr_disable()
336 ret = mlx4_glue->get_cq_event(rxq->cq->channel, &ev_cq, in mlx4_rx_intr_disable()
376 if (!rxq || !rxq->channel) { in mlx4_rx_intr_enable()
H A Dmlx4_rxq.c518 rxq->channel, 0); in mlx4_rxq_attach()
880 rxq->channel = mlx4_glue->create_comp_channel(priv->ctx); in mlx4_rx_queue_setup()
881 if (rxq->channel == NULL) { in mlx4_rx_queue_setup()
888 if (mlx4_fd_set_non_blocking(rxq->channel->fd) < 0) { in mlx4_rx_queue_setup()
926 if (rxq->channel) in mlx4_rx_queue_release()
927 claim_zero(mlx4_glue->destroy_comp_channel(rxq->channel)); in mlx4_rx_queue_release()
/dpdk/drivers/bus/vmbus/
H A Drte_bus_vmbus.h234 bool rte_vmbus_chan_rx_empty(const struct vmbus_channel *channel);
257 int rte_vmbus_chan_send(struct vmbus_channel *channel, uint16_t type,
270 void rte_vmbus_chan_signal_tx(const struct vmbus_channel *channel);
304 int rte_vmbus_chan_send_sglist(struct vmbus_channel *channel,
/dpdk/drivers/common/mlx5/linux/
H A Dmlx5_common_os.h108 mlx5_os_get_devx_channel_fd(void *channel) in mlx5_os_get_devx_channel_fd() argument
110 if (!channel) in mlx5_os_get_devx_channel_fd()
112 return ((struct mlx5dv_devx_event_channel *)channel)->fd; in mlx5_os_get_devx_channel_fd()
H A Dmlx5_glue.h173 int (*destroy_comp_channel)(struct ibv_comp_channel *channel);
176 struct ibv_comp_channel *channel,
179 int (*get_cq_event)(struct ibv_comp_channel *channel,
H A Dmlx5_glue.c135 mlx5_glue_destroy_comp_channel(struct ibv_comp_channel *channel) in mlx5_glue_destroy_comp_channel() argument
137 return ibv_destroy_comp_channel(channel); in mlx5_glue_destroy_comp_channel()
142 struct ibv_comp_channel *channel, int comp_vector) in mlx5_glue_create_cq() argument
144 return ibv_create_cq(context, cqe, cq_context, channel, comp_vector); in mlx5_glue_create_cq()
154 mlx5_glue_get_cq_event(struct ibv_comp_channel *channel, struct ibv_cq **cq, in mlx5_glue_get_cq_event() argument
157 return ibv_get_cq_event(channel, cq, cq_context); in mlx5_glue_get_cq_event()
/dpdk/doc/guides/nics/
H A Dcnxk.rst319 - ``Inline IPsec device channel and mask`` (default ``none``)
321 Set channel and channel mask configuration for the inline IPSec device. This
325 By default, RTE Flow API sets the channel number of the port on which the
333 With the above configuration, RTE Flow rules API will set the channel
334 and channel mask as 0x100 and 0xF00 in the MCAM entries of the flow rules
335 created with RTE_FLOW_ACTION_TYPE_SECURITY action. Since channel number is
339 - ``SDP device channel and mask`` (default ``none``)
340 Set channel and channel mask configuration for the SDP device. This
344 channel number and mask to cover the entire SDP channel range in the channel
352 With the above configuration, RTE Flow rules API will set the channel
[all …]
/dpdk/doc/guides/prog_guide/
H A Dpdump_lib.rst12 The library uses a generic multi process channel to facilitate communication
53 multi process channel to facilitate communication with secondary process, so the
60 channel using ``rte_mp_action_register()`` API. The primary process will listen to secondary proces…
61 to enable or disable the packet capture over the multi process channel.
65 the request to the primary process over the multi process channel. The primary process takes this r…
81 the request to the primary process over the multi process channel. The primary process takes this r…
H A Ddmadev.rst27 DMA queues), each hardware DMA channel should be represented by a dmadev.
29 channel represents a different transfer context.
30 * The DMA operation request must be submitted to the virtual DMA channel.
/dpdk/drivers/bus/dpaa/base/qbman/
H A Dqman_driver.c59 qpcfg.channel = map.channel; in fsl_qman_portal_init()
169 q_pcfg->channel = q_map.channel; in fsl_qman_fq_portal_create()
H A Dqman.c691 c->channel; in qman_create_affine_portal()
1665 mcc->initfq.fqd.dest.channel = p->config->channel; in qman_init_fq()
2036 mcc->querywq.channel.id = cpu_to_be16(wq->channel.id); in qman_query_wq()
2045 wq->channel.id = be16_to_cpu(mcr->querywq.channel.id); in qman_query_wq()
2535 cgr->chan = p->config->channel; in qman_create_cgr()
2641 cgr->chan, p->config->channel); in qman_delete_cgr()
2687 u32 channel, wq; in qman_shutdown_fq() local
2714 channel = dest_wq & 0x7; in qman_shutdown_fq()
2749 dequeue_wq = (channel - in qman_shutdown_fq()
2757 fqid, channel); in qman_shutdown_fq()
[all …]
/dpdk/drivers/net/cnxk/
H A Dcnxk_ethdev_sec.c14 uint16_t channel; member
172 ((struct inl_cpt_channel *)extra_args)->channel = chan; in parse_inl_cpt_channel()
212 inl_dev->channel = cpt_channel.channel; in nix_inl_parse_devargs()
H A Dcnxk_ethdev_devargs.c12 uint16_t channel; member
225 ((struct sdp_channel *)extra_args)->channel = chan; in parse_sdp_channel_mask()
334 dev->npc.sdp_channel = sdp_chan.channel; in cnxk_ethdev_parse_devargs()
/dpdk/drivers/common/mlx5/windows/
H A Dmlx5_common_os.h71 mlx5_os_get_devx_channel_fd(void *channel) in mlx5_os_get_devx_channel_fd() argument
73 if (!channel) in mlx5_os_get_devx_channel_fd()
/dpdk/doc/guides/sample_app_ug/
H A Dvm_power_management.rst71 - Each lcore has exclusive access to a single channel
100 example, each DPDK lcore on a VM has exclusive access to a channel.
197 <channel type='unix'>
201 </channel>
207 channel. Likewise, the port value ``{N}`` must be incremented for each
208 channel.
226 ``vm_channel_num`` is typically the lcore channel to be used in
229 Each channel on a VM is present at:
277 and the other for the channel endpoint monitor. For example, to run on
354 each channel:
[all …]
/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_cpp.h253 #define NFP_CPP_INTERFACE(type, unit, channel) \ argument
256 (((channel) & 0xff) << 0))
/dpdk/doc/guides/vdpadevs/
H A Dfeatures_overview.rst43 Control channel is available.
46 Control channel RX mode support.
/dpdk/drivers/common/cnxk/
H A Droc_npc_mcam.c502 struct npc_mcam_write_entry_req *req, uint16_t channel, in npc_mcam_set_channel() argument
513 chan = (channel | NIX_CHAN_CPT_CH_START); in npc_mcam_set_channel()
522 chan = (channel & NIX_CHAN_CPT_X2P_MASK); in npc_mcam_set_channel()
605 npc_mcam_set_channel(flow, req, inl_dev->channel, in npc_mcam_alloc_and_write()
612 npc_mcam_set_channel(flow, req, npc->channel, in npc_mcam_alloc_and_write()
H A Droc_nix_inl_priv.h80 uint16_t channel; member
H A Droc_npc.c159 roc_npc->channel = nix->rx_chan_base; in roc_npc_init()
161 npc->channel = roc_npc->channel; in roc_npc_init()
1209 npc->channel = roc_npc->channel; in roc_npc_flow_create()
/dpdk/drivers/bus/dpaa/include/
H A Dfsl_qman.h72 static inline u32 QM_SDQCR_CHANNELS_POOL_CONV(u16 channel) in QM_SDQCR_CHANNELS_POOL_CONV() argument
74 return QM_SDQCR_CHANNELS_POOL(channel + 1 - dpaa_get_qm_channel_pool()); in QM_SDQCR_CHANNELS_POOL_CONV()
470 u16 channel:13; /* qm_channel */ member
474 u16 channel:13; /* qm_channel */
799 } __packed channel; member
1014 } __packed channel; member
H A Dprocess.h63 u16 channel; member
/dpdk/doc/guides/linux_gsg/
H A Dnic_perf_intel_platform.rst15 Ensure that each memory channel has at least one memory DIMM inserted, and that the memory size for…
40 The sample output above shows a total of 8 channels, from ``A`` to ``H``, where each channel has 2 …
64 This aligns with the previous output which showed that each channel has one memory bar.

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