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/dpdk/drivers/net/bnxt/tf_ulp/generic_templates/
H A Dulp_template_db_class.c1326 .hdr_sig = { .bits =
1341 .hdr_sig = { .bits =
1357 .hdr_sig = { .bits =
1373 .hdr_sig = { .bits =
1390 .hdr_sig = { .bits =
1405 .hdr_sig = { .bits =
1421 .hdr_sig = { .bits =
1437 .hdr_sig = { .bits =
1454 .hdr_sig = { .bits =
1470 .hdr_sig = { .bits =
[all …]
H A Dulp_template_db_act.c119 .act_sig = { .bits =
127 .act_sig = { .bits =
136 .act_sig = { .bits =
145 .act_sig = { .bits =
154 .act_sig = { .bits =
163 .act_sig = { .bits =
173 .act_sig = { .bits =
183 .act_sig = { .bits =
192 .act_sig = { .bits =
202 .act_sig = { .bits =
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/dpdk/drivers/net/bnxt/tf_ulp/
H A Dulp_rte_parser.c318 ULP_BITMAP_SET(params->hdr_bitmap.bits, in ulp_post_process_normal_flow()
320 ULP_BITMAP_SET(params->act_bitmap.bits, in ulp_post_process_normal_flow()
350 params->hdr_bitmap.bits |= params->hdr_fp_bit.bits; in ulp_post_process_normal_flow()
701 ULP_BITMAP_SET(params->hdr_bitmap.bits, in ulp_rte_phy_port_hdr_handler()
715 ULP_BITMAP_SET(param->hdr_fp_bit.bits, in ulp_rte_l2_proto_type_update()
719 ULP_BITMAP_SET(param->hdr_fp_bit.bits, in ulp_rte_l2_proto_type_update()
725 ULP_BITMAP_SET(param->hdr_fp_bit.bits, in ulp_rte_l2_proto_type_update()
729 ULP_BITMAP_SET(param->hdr_fp_bit.bits, in ulp_rte_l2_proto_type_update()
917 ULP_BITMAP_SET(params->hdr_bitmap.bits, in ulp_rte_vlan_hdr_handler()
932 ULP_BITMAP_SET(params->hdr_bitmap.bits, in ulp_rte_vlan_hdr_handler()
[all …]
H A Dulp_tun.c131 if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4)) in ulp_get_tun_entry()
195 if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits, in ulp_tunnel_offload_process()
197 !ULP_BITMAP_ISSET(params->hdr_bitmap.bits, in ulp_tunnel_offload_process()
207 if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, in ulp_tunnel_offload_process()
212 ULP_BITMAP_RESET(params->act_bitmap.bits, in ulp_tunnel_offload_process()
217 } else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, in ulp_tunnel_offload_process()
219 ULP_BITMAP_RESET(params->hdr_bitmap.bits, in ulp_tunnel_offload_process()
222 ULP_BITMAP_SET(params->act_bitmap.bits, in ulp_tunnel_offload_process()
H A Dulp_matcher.c56 class_hid = ulp_matcher_class_hash_calculate((params->hdr_bitmap.bits ^ in ulp_matcher_pattern_match()
58 params->fld_s_bitmap.bits); in ulp_matcher_pattern_match()
115 act_hid = ulp_matcher_action_hash_calculate(params->act_bitmap.bits, in ulp_matcher_action_match()
H A Dulp_template_struct.h42 uint64_t bits; member
46 uint64_t bits; member
58 uint64_t bits; member
133 uint64_t bits; member
H A Dulp_utils.h25 #define ULP_BITMAP_CMP(b1, b2) memcmp(&(b1)->bits, \
26 &(b2)->bits, sizeof((b1)->bits))
/dpdk/drivers/net/igc/
H A Digc_ethdev.h267 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits) in igc_read_reg_check_set_bits() argument
271 bits |= reg_val; in igc_read_reg_check_set_bits()
272 if (bits == reg_val) in igc_read_reg_check_set_bits()
275 IGC_WRITE_REG(hw, reg, bits); in igc_read_reg_check_set_bits()
279 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits) in igc_read_reg_check_clear_bits() argument
283 bits = reg_val & ~bits; in igc_read_reg_check_clear_bits()
284 if (bits == reg_val) in igc_read_reg_check_clear_bits()
287 IGC_WRITE_REG(hw, reg, bits); in igc_read_reg_check_clear_bits()
/dpdk/drivers/bus/dpaa/include/
H A Ddpaa_bits.h22 static inline void dpaa_set_bit(int idx, volatile unsigned long *bits) in dpaa_set_bit() argument
24 dpaa_set_bits(BITS_MASK(idx), bits + BITS_IDX(idx)); in dpaa_set_bit()
34 volatile unsigned long *bits) in dpaa_clear_bit() argument
36 dpaa_clear_bits(BITS_MASK(idx), bits + BITS_IDX(idx)); in dpaa_clear_bit()
/dpdk/drivers/common/cnxk/
H A Droc_hash.c7 #define lrot32(bits, word) (((word) << (bits)) | ((word) >> (32 - (bits)))) argument
8 #define rrot32(bits, word) lrot32(32 - (bits), word) argument
9 #define lrot64(bits, word) (((word) << (bits)) | ((word) >> (64 - (bits)))) argument
10 #define rrot64(bits, word) lrot64(64 - (bits), word) argument
/dpdk/lib/member/
H A Drte_member_vbf.c63 uint32_t bits = ceil((num_keys_per_bf * in rte_member_create_vbf() local
68 ss->bits = rte_align32pow2(bits); in rte_member_create_vbf()
70 ss->num_hashes = (uint32_t)(log(2.0) * bits / num_keys_per_bf); in rte_member_create_vbf()
71 ss->bit_mask = ss->bits - 1; in rte_member_create_vbf()
78 float new_fp = pow((1 - pow((1 - 1.0 / ss->bits), num_keys_per_bf * in rte_member_create_vbf()
92 new_fp = pow((1 - pow((1 - 1.0 / ss->bits), num_keys_per_bf * in rte_member_create_vbf()
118 num_keys_per_bf, ss->bits, ss->num_hashes, fp_one_bf, new_fp); in rte_member_create_vbf()
120 ss->table = rte_zmalloc_socket(NULL, ss->num_set * (ss->bits >> 3), in rte_member_create_vbf()
319 memset(vbf, 0, (ss->num_set * ss->bits) >> 3); in rte_member_reset_vbf()
/dpdk/lib/acl/
H A Dacl_bld.c222 dst->bits[n] = (dst->bits[n] & mask) | src->bits[n]; in acl_include()
237 dst->bits[n] = src1->bits[n] & ~src2->bits[n]; in acl_exclude()
238 all_bits |= dst->bits[n]; in acl_exclude()
250 struct rte_acl_bitset *bits) in acl_add_ptr() argument
317 bitset.bits[n] = 0; in acl_add_ptr_range()
339 bitset->bits[n] = 0; in acl_gen_mask()
371 intersect->bits[n] = a_bits->bits[n] & b_bits->bits[n]; in acl_intersect_type()
372 a_superset |= a_bits->bits[n] ^ intersect->bits[n]; in acl_intersect_type()
373 b_superset |= b_bits->bits[n] ^ intersect->bits[n]; in acl_intersect_type()
462 struct rte_acl_bitset bits; in acl_copy_ptr() local
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H A Dacl_gen.c118 struct rte_acl_bitset *bits; in acl_node_fill_dfa() local
132 bits = &node->ptrs[x].values; in acl_node_fill_dfa()
135 if (bits->bits[n / (sizeof(bits_t) * CHAR_BIT)] & in acl_node_fill_dfa()
157 acl_count_sequential_groups(struct rte_acl_bitset *bits, int zero_one) in acl_count_sequential_groups() argument
165 if (bits->bits[n / (sizeof(bits_t) * 8)] & in acl_count_sequential_groups()
177 if (bits->bits[n / (sizeof(bits_t) * 8)] & in acl_count_sequential_groups()
/dpdk/doc/guides/prog_guide/
H A Dlpm6_lib.rst29 In this implementation, the user data is 21-bits long and is called "next hop",
55 or number of bits inspected on each level varies from level to level.
56 Specifically, 24 bits are inspected on the root node, and the remaining 104 bits are inspected in g…
73 are indexed using the rest of the bytes of the IP address, in chunks of 8 bits.
123 If the rule's depth is exactly 24 bits, then:
132 If the rule's depth is bigger than 24 bits but a multiple of 8, then:
134 * Use the first 24 bits of the rule as an index to the tbl24.
142 * Use the following 8 bits of the rule as an index to the next tbl8.
150 As a simple example, let's assume the depth is 20 bits.
167 * Use the first 24 bits of the IP address as an index to the tbl24.
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H A Dlpm_lib.rst57 while the second table(s), called tbl8, is indexed using the last 8 bits of the IP address.
64 Instead, this approach takes advantage of the fact that rules longer than 24 bits are very rare.
116 If the rule's depth is exactly 24 bits, then:
125 If the rule's depth is exactly 32 bits, then:
127 * Use the first 24 bits of the rule as an index to the tbl24.
137 As a simple example, let's assume the depth is 20 bits.
159 Prefix expansion is performed if the rule's depth is not exactly 24 bits or 32 bits.
185 * Use the first 24 bits of the IP address as an index to the tbl24.
191 and the last 8 bits of the IP address as an index to this table.
210 and the first 24 bits of this rule are not the same as the first 24 bits of a rule previously added.
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H A Dtoeplitz_hash_lib.rst76 of the least significant bits (LSB) of the hash value are used to indicate an
102 * Use the helper run time to calculate the adjustable bits of the tuple to
113 corresponding NIC. It reflects the number of least significant bits of the
133 sequence in the hash key for all the bits of the subtuple. However, the
134 collision generation task requires only the ``log2(RETA_SZ)`` bits in the
155 * A length of the subtuple to be modified. The length is counted in bits.
158 is also counted in bits.
167 Calculation of the complementary bits to adjust the subtuple
172 context initialization) to be xored with N least significant bits of the
308 /* Get the adjustment bits for the src port to get a new port. */
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H A Dfib_lib.rst91 Note that all available bits except one are used to store the actual next hop ID.
110 The first table ``tbl24``, is indexed using the first 24 bits of the IP address to be looked up,
111 while the second table(s) ``tbl8``, is indexed using the last 8 bits of the IP address.
118 Instead, this approach takes advantage of the fact that rules longer than 24 bits are very rare.
137 which are 63 bits long (using ``RTE_FIB_DIR24_8_8B`` as a next hop size).
138 These use cases could include storing two next hop IDs inside the 63 bits of the next hop.
/dpdk/lib/eal/x86/include/
H A Drte_memcpy.h222 size_t bits; in rte_memcpy_generic() local
290 bits = n; in rte_memcpy_generic()
292 bits -= n; in rte_memcpy_generic()
294 dst = (uint8_t *)dst + bits; in rte_memcpy_generic()
303 bits = n; in rte_memcpy_generic()
305 bits -= n; in rte_memcpy_generic()
307 dst = (uint8_t *)dst + bits; in rte_memcpy_generic()
411 size_t bits; in rte_memcpy_generic() local
485 bits = n; in rte_memcpy_generic()
487 bits -= n; in rte_memcpy_generic()
[all …]
/dpdk/drivers/net/ipn3ke/
H A Dipn3ke_flow.h66 #define BITS_TO_BYTES(bits) \ argument
67 (((bits) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
/dpdk/drivers/net/ice/base/
H A Dice_osdep.h296 u8 bits = 0; in ice_hweight8() local
300 bits += (u8)(num & 0x1); in ice_hweight8()
304 return bits; in ice_hweight8()
310 u8 bits = 0; in ice_hweight32() local
314 bits += (u8)(num & 0x1); in ice_hweight32()
318 return bits; in ice_hweight32()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_82598.c979 u32 bits; in ixgbe_set_vfta_82598() local
997 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); in ixgbe_set_vfta_82598()
998 bits &= (~(0x0F << bitindex)); in ixgbe_set_vfta_82598()
999 bits |= (vind << bitindex); in ixgbe_set_vfta_82598()
1000 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); in ixgbe_set_vfta_82598()
1005 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); in ixgbe_set_vfta_82598()
1008 bits |= (1 << bitindex); in ixgbe_set_vfta_82598()
1011 bits &= ~(1 << bitindex); in ixgbe_set_vfta_82598()
1012 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); in ixgbe_set_vfta_82598()
/dpdk/drivers/net/ngbe/base/
H A Dngbe_hw.c1306 u32 bits; in ngbe_find_vlvf_slot() local
1328 bits = rd32(hw, NGBE_PSRVLAN); in ngbe_find_vlvf_slot()
1329 if (bits == vlan) in ngbe_find_vlvf_slot()
1331 if (!first_empty_slot && !bits) in ngbe_find_vlvf_slot()
1423 u32 bits; in ngbe_set_vlvf() local
1446 bits = rd32(hw, NGBE_PSRVLANPLM(vind / 32)); in ngbe_set_vlvf()
1449 bits |= 1 << (vind % 32); in ngbe_set_vlvf()
1454 bits ^= 1 << (vind % 32); in ngbe_set_vlvf()
1456 if (!bits && in ngbe_set_vlvf()
1490 wr32(hw, NGBE_PSRVLANPLM(vind / 32), bits); in ngbe_set_vlvf()
/dpdk/drivers/bus/dpaa/base/qbman/
H A Dqman.c68 unsigned long bits; member
572 portal->bits = 0; in qman_init_portal()
1093 int qman_irqsource_add(u32 bits) in qman_irqsource_add() argument
1097 bits = bits & QM_PIRQ_VISIBLE; in qman_irqsource_add()
1103 qm_isr_status_clear(&p->p, bits); in qman_irqsource_add()
1104 dpaa_set_bits(bits, &p->irq_sources); in qman_irqsource_add()
1112 bits = bits & QM_PIRQ_VISIBLE; in qman_fq_portal_irqsource_add()
1118 qm_isr_status_clear(&p->p, bits); in qman_fq_portal_irqsource_add()
1125 int qman_irqsource_remove(u32 bits) in qman_irqsource_remove() argument
1140 bits &= QM_PIRQ_VISIBLE; in qman_irqsource_remove()
[all …]
/dpdk/doc/guides/cryptodevs/
H A Dkasumi.rst124 between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
125 Note that the actual message can be any length, specified in bits.
/dpdk/doc/guides/vdpadevs/
H A Dfeatures_overview.rst118 Support 32bits x86 architecture.
121 Support 64bits x86 architecture.

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