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Searched refs:base_addr (Results 1 – 25 of 53) sorted by relevance

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/dpdk/drivers/common/qat/
H A Dqat_qp.c224 queue->base_addr = (char *)qp_mz->addr; in qat_queue_create()
253 memset(queue->base_addr, 0x7F, queue_size_bytes); in qat_queue_create()
368 void *base_addr, rte_spinlock_t *lock) in adf_queue_arb_enable() argument
381 void *base_addr, rte_spinlock_t *lock) in adf_queue_arb_disable() argument
558 register uint8_t *base_addr; in qat_enqueue_op_burst() local
566 base_addr = (uint8_t *)queue->base_addr; in qat_enqueue_op_burst()
609 ret = op_build_request(*ops, base_addr + tail, in qat_enqueue_op_burst()
644 register uint8_t *base_addr; in qat_enqueue_comp_op_burst() local
656 base_addr = (uint8_t *)queue->base_addr; in qat_enqueue_comp_op_burst()
878 ((uint8_t *)queue->base_addr + queue->head); in qat_cq_dequeue_response()
[all …]
/dpdk/drivers/net/bnxt/hcapi/cfa/
H A Dhcapi_cfa_p4.c149 memcpy((uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, in hcapi_cfa_p4_key_hw_op_put()
161 (uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, in hcapi_cfa_p4_key_hw_op_get()
177 (uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, in hcapi_cfa_p4_key_hw_op_add()
186 memcpy((uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, in hcapi_cfa_p4_key_hw_op_add()
202 (uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, in hcapi_cfa_p4_key_hw_op_del()
225 memset((uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, 0, key_obj->size); in hcapi_cfa_p4_key_hw_op_del()
248 op->hw.base_addr = hcapi_get_table_page(em_tbl, page); in hcapi_cfa_p4_key_hw_op()
252 if (op->hw.base_addr == 0) in hcapi_cfa_p4_key_hw_op()
/dpdk/drivers/net/fm10k/base/
H A Dfm10k_vf.c258 u32 base_addr; in fm10k_read_mac_addr_vf() local
262 base_addr = FM10K_READ_REG(hw, FM10K_TDBAL(0)); in fm10k_read_mac_addr_vf()
265 if (base_addr << 24) in fm10k_read_mac_addr_vf()
268 perm_addr[3] = (u8)(base_addr >> 24); in fm10k_read_mac_addr_vf()
269 perm_addr[4] = (u8)(base_addr >> 16); in fm10k_read_mac_addr_vf()
270 perm_addr[5] = (u8)(base_addr >> 8); in fm10k_read_mac_addr_vf()
272 base_addr = FM10K_READ_REG(hw, FM10K_TDBAH(0)); in fm10k_read_mac_addr_vf()
275 if ((~base_addr) >> 24) in fm10k_read_mac_addr_vf()
278 perm_addr[0] = (u8)(base_addr >> 16); in fm10k_read_mac_addr_vf()
279 perm_addr[1] = (u8)(base_addr >> 8); in fm10k_read_mac_addr_vf()
[all …]
/dpdk/drivers/common/qat/dev/
H A Dqat_dev_gen1.c119 void *base_addr, rte_spinlock_t *lock) in qat_qp_adf_arb_enable_gen1() argument
127 value = ADF_CSR_RD(base_addr, in qat_qp_adf_arb_enable_gen1()
130 ADF_CSR_WR(base_addr, arb_csr_offset, value); in qat_qp_adf_arb_enable_gen1()
136 void *base_addr, rte_spinlock_t *lock) in qat_qp_adf_arb_disable_gen1() argument
143 value = ADF_CSR_RD(base_addr, arb_csr_offset); in qat_qp_adf_arb_disable_gen1()
145 ADF_CSR_WR(base_addr, arb_csr_offset, value); in qat_qp_adf_arb_disable_gen1()
H A Dqat_dev_gen4.c160 void *base_addr, rte_spinlock_t *lock) in qat_qp_adf_arb_enable_gen4() argument
168 value = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, in qat_qp_adf_arb_enable_gen4()
171 ADF_CSR_WR(base_addr, arb_csr_offset, value); in qat_qp_adf_arb_enable_gen4()
177 void *base_addr, rte_spinlock_t *lock) in qat_qp_adf_arb_disable_gen4() argument
185 value = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, in qat_qp_adf_arb_disable_gen4()
188 ADF_CSR_WR(base_addr, arb_csr_offset, value); in qat_qp_adf_arb_disable_gen4()
H A Dqat_dev_gens.h33 void *base_addr, rte_spinlock_t *lock);
37 void *base_addr, rte_spinlock_t *lock);
/dpdk/drivers/crypto/qat/dev/
H A Dqat_sym_pmd_gen1.c474 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_cipher_gen1()
478 rte_prefetch0((uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_cipher_gen1()
526 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_cipher_jobs_gen1()
582 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_auth_gen1()
634 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_auth_jobs_gen1()
690 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_chain_gen1()
744 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_chain_jobs_gen1()
808 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_aead_gen1()
859 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_aead_jobs_gen1()
959 (uint8_t *)rx_queue->base_addr + head); in qat_sym_dp_dequeue_burst_gen1()
[all …]
H A Dqat_crypto_pmd_gen3.c420 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_aead_gen3()
424 rte_prefetch0((uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_aead_gen3()
471 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_aead_jobs_gen3()
530 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_auth_gen3()
535 rte_prefetch0((uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_auth_gen3()
578 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_auth_jobs_gen3()
H A Dqat_crypto_pmd_gen4.c249 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_aead_gen4()
253 rte_prefetch0((uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_single_aead_gen4()
300 (uint8_t *)tx_queue->base_addr + tail); in qat_sym_dp_enqueue_aead_jobs_gen4()
/dpdk/drivers/net/atlantic/hw_atl/
H A Dhw_atl_b0.c416 int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr, in hw_atl_b0_hw_ring_rx_init() argument
419 u32 dma_desc_addr_lsw = (u32)base_addr; in hw_atl_b0_hw_ring_rx_init()
420 u32 dma_desc_addr_msw = (u32)(base_addr >> 32); in hw_atl_b0_hw_ring_rx_init()
454 int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, in hw_atl_b0_hw_ring_tx_init() argument
457 u32 dma_desc_lsw_addr = (u32)base_addr; in hw_atl_b0_hw_ring_tx_init()
458 u32 dma_desc_msw_addr = (u32)(base_addr >> 32); in hw_atl_b0_hw_ring_tx_init()
H A Dhw_atl_b0.h16 int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr,
18 int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr,
/dpdk/drivers/net/ngbe/
H A Dngbe_regs_group.h13 uint32_t base_addr; member
26 reg_buf[i] = rd32(hw, reg->base_addr + i * reg->stride); in ngbe_read_regs()
/dpdk/drivers/net/txgbe/
H A Dtxgbe_regs_group.h13 uint32_t base_addr; member
27 reg->base_addr + i * reg->stride); in txgbe_read_regs()
/dpdk/drivers/crypto/bcmfs/hw/
H A Dbcmfs5_rm.c413 (uint8_t *)txq->base_addr + txq->tx_write_ptr, in bcmfs5_enqueue_single_request_qp()
414 txq->base_addr, in bcmfs5_enqueue_single_request_qp()
415 (uint8_t *)txq->base_addr + txq->queue_size); in bcmfs5_enqueue_single_request_qp()
426 (uint8_t *)txq->base_addr); in bcmfs5_enqueue_single_request_qp()
491 desc = *((uint64_t *)((uint8_t *)hwq->base_addr + in bcmfs5_dequeue_qp()
554 rm_write_desc((uint8_t *)tx_queue->base_addr + off, d); in bcmfs5_start_qp()
613 rm_write_desc((uint8_t *)cmpl_queue->base_addr + off, 0x0); in bcmfs5_start_qp()
H A Dbcmfs4_rm.c489 (uint8_t *)txq->base_addr + txq->tx_write_ptr, in bcmfs4_enqueue_single_request_qp()
491 txq->base_addr, in bcmfs4_enqueue_single_request_qp()
492 (uint8_t *)txq->base_addr + txq->queue_size); in bcmfs4_enqueue_single_request_qp()
503 (uint8_t *)txq->base_addr); in bcmfs4_enqueue_single_request_qp()
560 desc = *((uint64_t *)((uint8_t *)hwq->base_addr + in bcmfs4_dequeue_qp()
623 rm_write_desc((uint8_t *)tx_queue->base_addr + off, d); in bcmfs4_start_qp()
682 rm_write_desc((uint8_t *)cmpl_queue->base_addr + off, 0x0); in bcmfs4_start_qp()
/dpdk/drivers/net/bnxt/tf_core/
H A Dtf_shadow_tcam.c79 (ctxt)->shadow_ctxt.base_addr)
83 (ctxt)->shadow_ctxt.base_addr)
134 uint32_t base_addr; member
252 uint16_t base_addr) in tf_shadow_tcam_ctxt_create() argument
303 ctxt->shadow_ctxt.base_addr = base_addr; in tf_shadow_tcam_ctxt_create()
812 base = parms->cfg->base_addr[i]; in tf_shadow_tcam_create_db()
H A Dtf_shadow_tcam.h32 uint16_t base_addr[TF_TCAM_TBL_TYPE_MAX]; member
/dpdk/drivers/net/hns3/
H A Dhns3_rxtx_vec_sve.c390 svuint64_t base_addr, buf_iova, data_off, data_len, addr; in hns3_tx_fill_hw_ring_sve() local
396 base_addr = svld1_u64(pg, (uint64_t *)pkts); in hns3_tx_fill_hw_ring_sve()
398 buf_iova = svadd_n_u64_z(pg, base_addr, in hns3_tx_fill_hw_ring_sve()
401 data_off = svadd_n_u64_z(pg, base_addr, in hns3_tx_fill_hw_ring_sve()
404 data_len = svadd_n_u64_z(pg, base_addr, in hns3_tx_fill_hw_ring_sve()
407 svst1_u64(pg, (uint64_t *)tx_entry, base_addr); in hns3_tx_fill_hw_ring_sve()
/dpdk/drivers/crypto/nitrox/
H A Dnitrox_hal.c68 uint64_t base_addr, reg_addr; in setup_nps_pkt_input_ring() local
75 base_addr = raddr; in setup_nps_pkt_input_ring()
76 nitrox_write_csr(bar_addr, reg_addr, base_addr); in setup_nps_pkt_input_ring()
/dpdk/drivers/net/e1000/
H A Digb_regs.h10 uint32_t base_addr; member
165 reg->base_addr + i * reg->stride); in igb_read_regs()
/dpdk/drivers/net/octeontx_ep/
H A Dotx_ep_common.h87 #define otx_ep_write64(value, base_addr, reg_off) \ argument
93 rte_write64(val, ((base_addr) + off)); \
187 uint8_t *base_addr; member
/dpdk/drivers/net/ixgbe/
H A Dixgbe_regs.h11 uint32_t base_addr; member
319 reg->base_addr + i * reg->stride); in ixgbe_read_regs()
/dpdk/drivers/common/mlx5/
H A Dmlx5_common.c1282 void *base_addr; in mlx5_devx_alloc_uar() local
1323 base_addr = mlx5_os_get_devx_uar_base_addr(uar); in mlx5_devx_alloc_uar()
1324 if (base_addr) in mlx5_devx_alloc_uar()
1360 void *base_addr; in mlx5_devx_uar_prepare() local
1376 base_addr = mlx5_os_get_devx_uar_base_addr(uar_obj); in mlx5_devx_uar_prepare()
1379 uar->cq_db.db = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL); in mlx5_devx_uar_prepare()
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_nicio.h24 #define HINIC_CI_VADDR(base_addr, q_id) \ argument
25 ((u8 *)(base_addr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
/dpdk/drivers/net/bnx2x/
H A Dbnx2x_ethdev.c659 sc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr; in bnx2x_common_dev_init()
661 sc->bar[BAR1].base_addr = (void *) in bnx2x_common_dev_init()
664 sc->bar[BAR1].base_addr = pci_dev->mem_resource[2].addr; in bnx2x_common_dev_init()
666 assert(sc->bar[BAR0].base_addr); in bnx2x_common_dev_init()
667 assert(sc->bar[BAR1].base_addr); in bnx2x_common_dev_init()

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