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Searched refs:barrier (Results 1 – 6 of 6) sorted by relevance

/dpdk/lib/eal/windows/include/
H A Dpthread.h37 #define pthread_barrier_init(barrier, attr, count) \ argument
38 !InitializeSynchronizationBarrier(barrier, count, -1)
39 #define pthread_barrier_wait(barrier) EnterSynchronizationBarrier(barrier, \ argument
41 #define pthread_barrier_destroy(barrier) \ argument
42 !DeleteSynchronizationBarrier(barrier)
/dpdk/drivers/common/dpaax/
H A Dcompat.h180 #define barrier() { asm volatile ("" : : : "memory"); } macro
181 #define cpu_relax barrier
/dpdk/doc/guides/platform/
H A Dmlx5.rst622 memory barrier after writing to doorbell, it might increase the needed CPU
626 cached memory, the PMD will not perform the extra write memory barrier after
631 barrier should be performed. For bursts with size multiple of recommended one
633 extra memory barrier (it is supposed to be issued in the next coming burst,
/dpdk/doc/guides/prog_guide/
H A Dwriting_efficient_code.rst215 are not allowed to move above the lock. In this case, the full memory barrier
219 section are not allowed to move below the unlock. So the full barrier in the
/dpdk/doc/guides/rel_notes/
H A Ddeprecation.rst27 * rte_smp_*mb: These APIs provide full barrier functionality. However, many
H A Drelease_17_02.rst27 Weakly-ordered architectures like ARM need an additional I/O barrier for
31 does not have an additional I/O memory barrier, which is useful in accessing