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/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_cpp_pcie_ops.c174 bar->index); in nfp_compute_bar()
205 bar->index); in nfp_compute_bar()
319 bar = &nfp->bar[x - 1]; in nfp_enable_bars()
325 bar->base = 0; in nfp_enable_bars()
327 bar->lock = 0; in nfp_enable_bars()
332 bar->iomem = nfp->cfg + (bar->index << bar->bitsize); in nfp_enable_bars()
351 bar = &nfp->bar[x - 1]; in nfp_alloc_bar()
354 return bar; in nfp_alloc_bar()
375 bar = &nfp->bar[x - 1]; in nfp_disable_bars()
398 int bar; member
[all …]
/dpdk/kernel/freebsd/nic_uio/
H A Dnic_uio.c103 unsigned bar = *offset/PAGE_SIZE; in nic_uio_mmap_single() local
106 if (bar >= MAX_BARS) in nic_uio_mmap_single()
109 if (sc->bar_res[bar] == NULL) { in nic_uio_mmap_single()
110 sc->bar_id[bar] = PCIR_BAR(bar); in nic_uio_mmap_single()
114 &sc->bar_id[bar], RF_ACTIVE); in nic_uio_mmap_single()
117 &sc->bar_id[bar], RF_ACTIVE); in nic_uio_mmap_single()
119 if (sc->bar_res[bar] == NULL) in nic_uio_mmap_single()
122 sc->bar_start[bar] = rman_get_start(sc->bar_res[bar]); in nic_uio_mmap_single()
123 sc->bar_size[bar] = rman_get_size(sc->bar_res[bar]); in nic_uio_mmap_single()
126 sc->bar_start[bar], sc->bar_size[bar]); in nic_uio_mmap_single()
[all …]
/dpdk/drivers/bus/pci/linux/
H A Dpci_vfio.c522 if (bar->size == 0) { in pci_vfio_mmap_bar()
547 bar->size = 0; in pci_vfio_mmap_bar()
548 bar->addr = 0; in pci_vfio_mmap_bar()
552 memreg[0].offset = bar->offset; in pci_vfio_mmap_bar()
554 if (bar->size < table_end) { in pci_vfio_mmap_bar()
574 memreg[0].offset = bar->offset; in pci_vfio_mmap_bar()
575 memreg[0].size = bar->size; in pci_vfio_mmap_bar()
579 bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE | in pci_vfio_mmap_bar()
608 bar->offset)); in pci_vfio_mmap_bar()
617 munmap(bar_addr, bar->size); in pci_vfio_mmap_bar()
[all …]
H A Dpci_init.h40 int pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
74 int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
H A Dpci_uio.c397 pci_uio_ioport_map(struct rte_pci_device *dev, int bar, in pci_uio_ioport_map() argument
419 for (i = 0; i < bar + 1; i++) { in pci_uio_ioport_map()
444 base = (unsigned long)dev->mem_resource[bar].addr; in pci_uio_ioport_map()
488 pci_uio_ioport_map(struct rte_pci_device *dev, int bar, in pci_uio_ioport_map() argument
508 for (i = 0; i < bar + 1; i++) { in pci_uio_ioport_map()
518 RTE_LOG(ERR, EAL, "BAR %d is not an IO resource\n", bar); in pci_uio_ioport_map()
523 dev->addr.devid, dev->addr.function, bar); in pci_uio_ioport_map()
H A Dpci.c692 rte_pci_ioport_map(struct rte_pci_device *dev, int bar, in rte_pci_ioport_map() argument
701 ret = pci_vfio_ioport_map(dev, bar, p); in rte_pci_ioport_map()
706 ret = pci_uio_ioport_map(dev, bar, p); in rte_pci_ioport_map()
/dpdk/drivers/vdpa/ifc/base/
H A Difcvf.c11 u8 bar = cap->bar; in get_cap_addr() local
15 if (bar > IFCVF_PCI_MAX_RESOURCE - 1) { in get_cap_addr()
16 DEBUGOUT("invalid bar: %u\n", bar); in get_cap_addr()
26 if (offset + length > hw->mem_resource[cap->bar].len) { in get_cap_addr()
28 offset, length, (u32)hw->mem_resource[cap->bar].len); in get_cap_addr()
32 return hw->mem_resource[bar].addr + offset; in get_cap_addr()
60 "len: %u\n", cap.cfg_type, cap.bar, in ifcvf_init_hw()
76 hw->notify_region = cap.bar; in ifcvf_init_hw()
H A Difcvf.h66 u8 bar; /* Where to find it. */ member
/dpdk/drivers/bus/pci/bsd/
H A Dpci.c215 struct pci_bar_io bar; in pci_scan_one() local
275 bar.pbi_sel = conf->pc_sel; in pci_scan_one()
276 bar.pbi_reg = PCIR_BAR(i); in pci_scan_one()
277 if (ioctl(dev_pci_fd, PCIOCGETBAR, &bar) < 0) in pci_scan_one()
280 dev->mem_resource[i].len = bar.pbi_length; in pci_scan_one()
281 if (PCI_BAR_IO(bar.pbi_base)) { in pci_scan_one()
282 dev->mem_resource[i].addr = (void *)(bar.pbi_base & ~((uint64_t)0xf)); in pci_scan_one()
285 dev->mem_resource[i].phys_addr = bar.pbi_base & ~((uint64_t)0xf); in pci_scan_one()
493 rte_pci_ioport_map(struct rte_pci_device *dev, int bar, in rte_pci_ioport_map() argument
506 if ((uintptr_t) dev->mem_resource[bar].addr <= UINT16_MAX) { in rte_pci_ioport_map()
[all …]
/dpdk/drivers/crypto/virtio/
H A Dvirtio_pci.c310 uint8_t bar = cap->bar; in get_cfg_addr() local
315 if (bar >= PCI_MAX_RESOURCE) { in get_cfg_addr()
316 VIRTIO_CRYPTO_INIT_LOG_ERR("invalid bar: %u", bar); in get_cfg_addr()
326 if (offset + length > dev->mem_resource[bar].len) { in get_cfg_addr()
329 offset + length, dev->mem_resource[bar].len); in get_cfg_addr()
333 base = dev->mem_resource[bar].addr; in get_cfg_addr()
335 VIRTIO_CRYPTO_INIT_LOG_ERR("bar %u base addr is NULL", bar); in get_cfg_addr()
393 pos, cap.cfg_type, cap.bar, cap.offset, cap.length); in virtio_read_caps()
/dpdk/drivers/raw/ntb/
H A Dntb_hw_intel.c122 uint8_t bar; in intel_ntb_dev_init() local
157 bar = intel_ntb_bar[i]; in intel_ntb_dev_init()
158 hw->mw_size[i] = hw->pci_dev->mem_resource[bar].len; in intel_ntb_dev_init()
174 uint8_t bar; in intel_ntb_get_peer_mw_addr() local
187 bar = intel_ntb_bar[mw_idx]; in intel_ntb_get_peer_mw_addr()
189 return hw->pci_dev->mem_resource[bar].addr; in intel_ntb_get_peer_mw_addr()
200 uint8_t bar; in intel_ntb_mw_set_trans() local
213 bar = intel_ntb_bar[mw_idx]; in intel_ntb_mw_set_trans()
222 limit = hw->pci_dev->mem_resource[bar].phys_addr + size; in intel_ntb_mw_set_trans()
/dpdk/doc/guides/rawdevs/
H A Dntb.rst24 - Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M)
25 on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB).
26 Note that bar size on both hosts should be the same.
57 Get bar base address using ``lspci -vvv -s ae:00.0 | grep Region``.
/dpdk/drivers/net/ionic/
H A Dionic_dev.c16 struct ionic_dev_bar *bar = adapter->bars; in ionic_dev_setup() local
29 if (bar->len < IONIC_BAR0_SIZE) { in ionic_dev_setup()
32 bar->len); in ionic_dev_setup()
36 bar0_base = bar->vaddr; in ionic_dev_setup()
61 bar++; in ionic_dev_setup()
67 idev->db_pages = bar->vaddr; in ionic_dev_setup()
/dpdk/drivers/net/virtio/
H A Dvirtio_pci.c602 uint8_t bar = cap->bar; in get_cfg_addr() local
607 if (bar >= PCI_MAX_RESOURCE) { in get_cfg_addr()
608 PMD_INIT_LOG(ERR, "invalid bar: %u", bar); in get_cfg_addr()
618 if (offset + length > dev->mem_resource[bar].len) { in get_cfg_addr()
621 offset + length, dev->mem_resource[bar].len); in get_cfg_addr()
625 base = dev->mem_resource[bar].addr; in get_cfg_addr()
627 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar); in get_cfg_addr()
703 pos, cap.cfg_type, cap.bar, cap.offset, cap.length); in virtio_read_caps()
H A Dvirtio_pci.h62 uint8_t bar; /* Where to find it. */ member
/dpdk/drivers/net/enic/base/
H A Dvnic_dev.c106 struct vnic_dev_bar *bar, unsigned int num_bars) in vnic_dev_discover_res() argument
116 if (bar->len < VNIC_MAX_RES_HDR_SIZE) { in vnic_dev_discover_res()
121 rh = bar->vaddr; in vnic_dev_discover_res()
122 mrh = bar->vaddr; in vnic_dev_discover_res()
149 uint8_t bar_num = ioread8(&r->bar); in vnic_dev_discover_res()
159 if (!bar[bar_num].len || !bar[bar_num].vaddr) in vnic_dev_discover_res()
169 if (len + bar_offset > bar[bar_num].len) { in vnic_dev_discover_res()
175 bar[bar_num].len); in vnic_dev_discover_res()
188 vdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr + in vnic_dev_discover_res()
190 vdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset; in vnic_dev_discover_res()
[all …]
H A Dvnic_resource.h61 uint8_t bar; member
/dpdk/drivers/raw/ifpga/base/
H A Difpga_enumerate.c567 static int parse_switch_to(struct build_feature_devs_info *binfo, int bar) in parse_switch_to() argument
571 if (!pci_data->region[bar].addr) in parse_switch_to()
574 binfo->ioaddr = pci_data->region[bar].addr; in parse_switch_to()
575 binfo->ioend = (u8 __iomem *)binfo->ioaddr + pci_data->region[bar].len; in parse_switch_to()
576 binfo->phys_addr = pci_data->region[bar].phys_addr; in parse_switch_to()
577 binfo->current_bar = bar; in parse_switch_to()
/dpdk/drivers/event/octeontx/
H A Dssovf_probe.c98 ssovf_bar(enum ssovf_type type, uint8_t id, uint8_t bar) in ssovf_bar() argument
113 switch (bar) { in ssovf_bar()
122 switch (bar) { in ssovf_bar()
H A Dtimvf_probe.c72 timvf_bar(uint8_t vfid, uint8_t bar) in timvf_bar() argument
92 switch (bar) { in timvf_bar()
H A Dssovf_evdev.h187 void *ssovf_bar(enum ssovf_type, uint8_t id, uint8_t bar);
/dpdk/drivers/common/sfc_efx/base/
H A Defx_pci.c202 unsigned int bar; in efx_pci_read_ext_cap_xilinx_table() local
255 bar = EFX_OWORD_FIELD32(vsec, ESF_GZ_VSEC_TBL_BAR); in efx_pci_read_ext_cap_xilinx_table()
284 *barp = bar; in efx_pci_read_ext_cap_xilinx_table()
/dpdk/drivers/net/bnx2x/
H A Dbnx2x_ethdev.c659 sc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr; in bnx2x_common_dev_init()
661 sc->bar[BAR1].base_addr = (void *) in bnx2x_common_dev_init()
664 sc->bar[BAR1].base_addr = pci_dev->mem_resource[2].addr; in bnx2x_common_dev_init()
666 assert(sc->bar[BAR0].base_addr); in bnx2x_common_dev_init()
667 assert(sc->bar[BAR1].base_addr); in bnx2x_common_dev_init()
H A Dbnx2x.h1084 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ member
1441 rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_write8()
1454 rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_write16()
1469 rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_write32()
1477 val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset); in bnx2x_reg_read8()
1495 val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_read16()
1513 val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_read32()
1520 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1582 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
/dpdk/drivers/bus/pci/
H A Drte_bus_pci.h351 int rte_pci_ioport_map(struct rte_pci_device *dev, int bar,

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