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Searched refs:bank (Results 1 – 10 of 10) sorted by relevance

/dpdk/drivers/common/qat/qat_adf/
H A Dadf_transport_access_macros.h94 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
95 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
97 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
98 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
100 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
101 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
104 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
111 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
122 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
129 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
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H A Dadf_transport_access_macros_gen4vf.h13 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ argument
19 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
23 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
28 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ argument
30 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
33 #define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \ argument
35 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
38 #define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \ argument
40 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
43 #define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \ argument
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H A Dadf_transport_access_macros_gen4.h22 #define WRITE_CSR_RING_BASE_GEN4(csr_base_addr, bank, ring, value) \ argument
28 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
32 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
37 #define WRITE_CSR_RING_CONFIG_GEN4(csr_base_addr, bank, ring, value) \ argument
39 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
42 #define WRITE_CSR_RING_TAIL_GEN4(csr_base_addr, bank, ring, value) \ argument
44 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
47 #define WRITE_CSR_RING_HEAD_GEN4(csr_base_addr, bank, ring, value) \ argument
49 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
/dpdk/drivers/net/ice/base/
H A Dice_nvm.c274 switch (bank) { in ice_get_flash_bank_offset()
311 start = ice_get_flash_bank_offset(hw, bank, module); in ice_read_flash_module()
554 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l); in ice_get_nvm_srev()
558 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h); in ice_get_nvm_srev()
582 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver); in ice_get_nvm_ver_info()
591 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); in ice_get_nvm_ver_info()
604 status = ice_get_nvm_srev(hw, bank, &nvm->srev); in ice_get_nvm_ver_info()
675 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, in ice_get_orom_civd_data() argument
690 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, in ice_get_orom_civd_data()
734 status = ice_get_orom_civd_data(hw, bank, &civd); in ice_get_orom_ver_info()
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H A Dice_acl.c346 if (cntrs->bank > ICE_AQC_ACL_MAX_CNT_SINGLE) in ice_aq_acl_cntrs_chk_params()
353 if (cntrs->bank > ICE_AQC_ACL_MAX_CNT_DUAL) in ice_aq_acl_cntrs_chk_params()
393 cmd->bank_alloc = cntrs->bank; in ice_aq_alloc_acl_cntrs()
433 cmd->bank_alloc = cntrs->bank; in ice_aq_dealloc_acl_cntrs()
H A Dice_acl.h120 u8 bank; member
H A Dice_flow.c2080 cntrs.bank = 0; /* Only bank0 for the moment */ in ice_flow_acl_free_act_cntr()
2766 cntrs.bank = 0; /* Only bank0 for the moment */ in ice_flow_acl_check_actions()
/dpdk/drivers/net/e1000/base/
H A De1000_ich8lan.c3350 *bank = 0; in e1000_valid_nvm_bank_detect_ich8lan()
3360 *bank = 0; in e1000_valid_nvm_bank_detect_ich8lan()
3373 *bank = 1; in e1000_valid_nvm_bank_detect_ich8lan()
3385 *bank = 1; in e1000_valid_nvm_bank_detect_ich8lan()
3395 *bank = 0; in e1000_valid_nvm_bank_detect_ich8lan()
3404 *bank = 0; in e1000_valid_nvm_bank_detect_ich8lan()
3416 *bank = 1; in e1000_valid_nvm_bank_detect_ich8lan()
3460 bank = 0; in e1000_read_nvm_spt()
3553 bank = 0; in e1000_read_nvm_ich8lan()
4013 bank = 0; in e1000_update_nvm_checksum_spt()
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/dpdk/drivers/net/bnxt/tf_core/
H A Dtf_sram_mgr.c85 struct tf_sram_bank_info bank[TF_SRAM_BANK_ID_MAX]; member
153 *slice_list = &sram->dir[dir].bank[bank_id].slice[slice_size]; in tf_sram_get_slice_list()
/dpdk/drivers/net/bnx2x/
H A Delink.c6716 uint16_t bank; in elink_set_gmii_tx_driver() local
6731 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; in elink_set_gmii_tx_driver()
6732 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { in elink_set_gmii_tx_driver()
6734 bank, in elink_set_gmii_tx_driver()
6743 bank, in elink_set_gmii_tx_driver()
6800 uint16_t bank, i = 0; in elink_set_preemphasis() local
6803 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; in elink_set_preemphasis()
6804 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) { in elink_set_preemphasis()
6806 bank, in elink_set_preemphasis()
6811 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; in elink_set_preemphasis()
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