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/dpdk/lib/eal/include/generic/
H A Drte_vect.h27 typedef uint8_t rte_v64u8_t __attribute__((vector_size(8), aligned(8)));
34 typedef uint16_t rte_v64u16_t __attribute__((vector_size(8), aligned(8)));
41 typedef uint32_t rte_v64u32_t __attribute__((vector_size(8), aligned(8)));
49 typedef uint8_t rte_v128u8_t __attribute__((vector_size(16), aligned(16)));
56 typedef uint16_t rte_v128u16_t __attribute__((vector_size(16), aligned(16)));
63 typedef uint32_t rte_v128u32_t __attribute__((vector_size(16), aligned(16)));
80 typedef uint8_t rte_v256u8_t __attribute__((vector_size(32), aligned(32)));
112 typedef int8_t rte_v64s8_t __attribute__((vector_size(8), aligned(8)));
119 typedef int16_t rte_v64s16_t __attribute__((vector_size(8), aligned(8)));
126 typedef int32_t rte_v64s32_t __attribute__((vector_size(8), aligned(8)));
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/dpdk/doc/guides/cryptodevs/features/
H A Dkasumi.ini10 Non-Byte aligned data = Y
H A Dzuc.ini10 Non-Byte aligned data = Y
H A Dsnow3g.ini10 Non-Byte aligned data = Y
H A Dchacha20_poly1305.ini10 Non-Byte aligned data = Y
H A Daesni_mb.ini18 Non-Byte aligned data = Y
H A Ddefault.ini32 Non-Byte aligned data =
/dpdk/doc/guides/cryptodevs/
H A Dzuc.rst28 * ZUC (EIA3) supported only if hash offset field is byte-aligned.
29 * ZUC (EEA3) supported only if cipher length, cipher offset fields are byte-aligned.
H A Dsnow3g.rst28 * SNOW 3G (UIA2) supported only if hash offset field is byte-aligned.
30 (if length and/or offset of data to be ciphered is not byte-aligned).
H A Dkasumi.rst28 * KASUMI(F9) supported only if hash offset and length field is byte-aligned.
30 (if length and/or offset of data to be ciphered is not byte-aligned).
H A Dmlx5.rst29 The encryption does not require text to be aligned to the AES block size (128b).
/dpdk/drivers/dma/dpaa/
H A Ddpaa_qdma.c101 *dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr) in dma_pool_alloc() argument
105 virt_addr = rte_malloc("dma pool alloc", size, aligned); in dma_pool_alloc()
189 int size, int aligned) in fsl_qdma_pre_request_enqueue_comp_sd_desc() argument
204 dma_pool_alloc(size, aligned, &comp_temp->bus_addr); in fsl_qdma_pre_request_enqueue_comp_sd_desc()
211 dma_pool_alloc(size, aligned, &comp_temp->desc_bus_addr); in fsl_qdma_pre_request_enqueue_comp_sd_desc()
/dpdk/drivers/mempool/dpaa2/
H A Ddpaa2_hw_mempool.c216 goto aligned; in rte_dpaa2_mbuf_release()
239 aligned: in rte_dpaa2_mbuf_release()
/dpdk/lib/eal/arm/include/
H A Drte_vect.h89 typedef uint8_t poly128_t __attribute__((vector_size(16), aligned(16)));
/dpdk/lib/eal/common/
H A Dmalloc_heap.c207 void *aligned = RTE_PTR_ALIGN_CEIL(data_start, in find_biggest_element() local
210 if (aligned >= data_end) in find_biggest_element()
212 cur_size = RTE_PTR_DIFF(data_end, aligned); in find_biggest_element()
H A Deal_common_memory.c660 uintptr_t aligned = RTE_PTR_ALIGN_FLOOR(virtual, page_size); in rte_mem_lock_page() local
661 return rte_mem_lock((void *)aligned, page_size); in rte_mem_lock_page()
/dpdk/doc/guides/sample_app_ug/
H A Dpipeline.rst10 This application showcases the features of the Software Switch (SWX) pipeline that is aligned with …
/dpdk/doc/guides/contributing/
H A Dabi_policy.rst19 #. Major ABI versions are usually but not always declared aligned with a
293 A new ABI version may be declared aligned with a given release.
H A Dabi_versioning.rst53 Major ABI versions are therefore declared typically aligned with an LTS release
/dpdk/doc/guides/rel_notes/
H A Drelease_2_1.rst745 * **ixgbe: Fix RX with buffer address not word aligned.**
748 aligned.
751 * **ixgbe: Fix RX with buffer address not word aligned.**
H A Drelease_19_02.rst45 * The reset routine was aligned with the DPDK API, so now it can be
H A Drelease_19_05.rst248 defined as cache-line aligned that caused unintended changes in
/dpdk/config/
H A Dmeson.build271 '-Wno-packed-not-aligned',
/dpdk/doc/guides/prog_guide/
H A Dmbuf_lib.rst41 RTE_PKTMBUF_HEADROOM bytes after the beginning of the buffer, which is cache aligned.
H A Dwriting_efficient_code.rst56 * Use a table of structures (one per lcore). In this case, each structure must be cache-aligned.

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