Home
last modified time | relevance | path

Searched refs:W (Results 1 – 9 of 9) sorted by relevance

/dpdk/drivers/common/cnxk/
H A Droc_hash.c31 memcpy(&W[0], msg, 16 * sizeof(W[0])); in roc_hash_sha1_gen()
34 W[i] = htobe32(W[i]); in roc_hash_sha1_gen()
37 W[i] = lrot32(1, W[i - 3] ^ W[i - 8] ^ W[i - 14] ^ W[i - 16]); in roc_hash_sha1_gen()
107 memcpy(&W[0], msg, 16 * sizeof(W[0])); in roc_hash_sha256_gen()
110 W[i] = htobe32(W[i]); in roc_hash_sha256_gen()
113 S0 = rrot32(7, W[i - 15]) ^ rrot32(18, W[i - 15]) ^ in roc_hash_sha256_gen()
115 S1 = rrot32(17, W[i - 2]) ^ rrot32(19, W[i - 2]) ^ in roc_hash_sha256_gen()
117 W[i] = W[i - 16] + S0 + W[i - 7] + S1; in roc_hash_sha256_gen()
219 memcpy(&W[0], msg, 16 * sizeof(W[0])); in roc_hash_sha512_gen()
222 W[i] = htobe64(W[i]); in roc_hash_sha512_gen()
[all …]
/dpdk/doc/guides/sample_app_ug/
H A Dl2_forward_event.rst107 To run application with S/W scheduler, it uses following DPDK services:
114 must be provided as EAL parameters along with the --vdev=event_sw0 to enable S/W
258 Application can use either H/W or S/W based event device scheduler
268 In case of S/W scheduler, application runs eventdev scheduler service on service
270 run S/W scheduler.
290 In case of S/W scheduler, an extra event queue is created which will be used for
307 In case of S/W scheduler, an extra event port is created by DPDK library which
318 Each Ethernet port is assigned a dedicated Rx/Tx adapter for H/W scheduler. Each
329 For S/W scheduler instead of dedicated adapters, common Rx/Tx adapters are
430 depending H/W or S/W scheduler is used.
H A Dl3_forward.rst22 Eventdev can optionally use S/W or H/W (if supported by platform) scheduler
195 If application uses S/W scheduler, it uses following DPDK services:
202 must be provided as EAL parameters along with the --vdev=event_sw0 to enable S/W
/dpdk/doc/guides/
H A Dmeson.build12 extra_sphinx_args += '-W'
/dpdk/doc/guides/rel_notes/
H A Drelease_19_08.rst231 checksum H/W offload irrespective of the platform capability.
232 Cleared IP checksum H/W offload flag from the library. The application must
238 Once reassembly is done, ``mbuf->ol_flags`` are set to enable IP checksum H/W
239 offload irrespective of the platform capability. Cleared IP checksum H/W
/dpdk/.github/workflows/
H A Dbuild.yml85 …{{ matrix.config.os }}-${{ matrix.config.compiler }}-${{ matrix.config.cross }}-'$(date -u +%Y-w%W)
237 echo 'ccache-${{ matrix.config.image }}-${{ matrix.config.compiler }}-'$(date -u +%Y-w%W)
/dpdk/doc/guides/nics/
H A Ddpaa2.rst526 dpaa2 hardware imposes limits on some H/W access devices like Management
527 Control Port and H/W portal. This causes issue in their shared usages in
532 driver reserves extra Management Control Port and H/W portal which can be
/dpdk/doc/guides/platform/
H A Dcnxk.rst7 This document gives an overview of **Marvell OCTEON CN9K and CN10K** RVU H/W block,
150 This section lists dataplane H/W block(s) available in cnxk SoC.
/dpdk/
H A DMAINTAINERS597 M: John W. Linville <[email protected]>