1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
3 */
4 /*$FreeBSD$*/
5
6 #ifndef _E1000_OSDEP_H_
7 #define _E1000_OSDEP_H_
8
9 #include <stdint.h>
10 #include <stdio.h>
11 #include <stdarg.h>
12 #include <stdbool.h>
13 #include <string.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
16 #include <rte_log.h>
17 #include <rte_debug.h>
18 #include <rte_byteorder.h>
19 #include <rte_io.h>
20
21 #include "../e1000_logs.h"
22
23 #define DELAY(x) rte_delay_us_sleep(x)
24 #define usec_delay(x) DELAY(x)
25 #define usec_delay_irq(x) DELAY(x)
26 #define msec_delay(x) DELAY(1000*(x))
27 #define msec_delay_irq(x) DELAY(1000*(x))
28
29 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
30 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
31 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
32 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
33 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
34 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
35 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
36
37 #ifndef UNREFERENCED_PARAMETER
38 #define UNREFERENCED_PARAMETER(_p)
39 #endif
40 #define UNREFERENCED_1PARAMETER(_p)
41 #define UNREFERENCED_2PARAMETER(_p, _q)
42 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
43 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
44
45 #define FALSE 0
46 #define TRUE 1
47
48 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
49
50 /* Mutex used in the shared code */
51 #define E1000_MUTEX uintptr_t
52 #define E1000_MUTEX_INIT(mutex) (*(mutex) = 0)
53 #define E1000_MUTEX_LOCK(mutex) (*(mutex) = 1)
54 #define E1000_MUTEX_UNLOCK(mutex) (*(mutex) = 0)
55
56 typedef uint64_t u64;
57 typedef uint32_t u32;
58 typedef uint16_t u16;
59 typedef uint8_t u8;
60 typedef int64_t s64;
61 typedef int32_t s32;
62 typedef int16_t s16;
63 typedef int8_t s8;
64
65 #define __le16 u16
66 #define __le32 u32
67 #define __le64 u64
68
69 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
70
71 #define E1000_PCI_REG(reg) rte_read32(reg)
72
73 #define E1000_PCI_REG16(reg) rte_read16(reg)
74
75 #define E1000_PCI_REG_WRITE(reg, value) \
76 rte_write32((rte_cpu_to_le_32(value)), reg)
77
78 #define E1000_PCI_REG_WRITE_RELAXED(reg, value) \
79 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
80
81 #define E1000_PCI_REG_WRITE16(reg, value) \
82 rte_write16((rte_cpu_to_le_16(value)), reg)
83
84 #define E1000_PCI_REG_ADDR(hw, reg) \
85 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
86
87 #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \
88 E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
89
90 #define E1000_PCI_REG_FLASH_ADDR(hw, reg) \
91 ((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
92
e1000_read_addr(volatile void * addr)93 static inline uint32_t e1000_read_addr(volatile void *addr)
94 {
95 return rte_le_to_cpu_32(E1000_PCI_REG(addr));
96 }
97
e1000_read_addr16(volatile void * addr)98 static inline uint16_t e1000_read_addr16(volatile void *addr)
99 {
100 return rte_le_to_cpu_16(E1000_PCI_REG16(addr));
101 }
102
103 /* Necessary defines */
104 #define E1000_MRQC_ENABLE_MASK 0x00000007
105 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
106 #define E1000_ALL_FULL_DUPLEX ( \
107 ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
108
109 #define M88E1543_E_PHY_ID 0x01410EA0
110 #define ULP_SUPPORT
111
112 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
113 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
114
115 /* Register READ/WRITE macros */
116
117 #define E1000_READ_REG(hw, reg) \
118 e1000_read_addr(E1000_PCI_REG_ADDR((hw), (reg)))
119
120 #define E1000_WRITE_REG(hw, reg, value) \
121 E1000_PCI_REG_WRITE(E1000_PCI_REG_ADDR((hw), (reg)), (value))
122
123 #define E1000_READ_REG_ARRAY(hw, reg, index) \
124 E1000_PCI_REG(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
125
126 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
127 E1000_PCI_REG_WRITE(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
128
129 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
130 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
131
132 #define E1000_ACCESS_PANIC(x, hw, reg, value) \
133 rte_panic("%s:%u\t" RTE_STR(x) "(%p, 0x%x, 0x%x)", \
134 __FILE__, __LINE__, (hw), (reg), (unsigned int)(value))
135
136 /*
137 * To be able to do IO write, we need to map IO BAR
138 * (bar 2/4 depending on device).
139 * Right now mapping multiple BARs is not supported by DPDK.
140 * Fortunatelly we need it only for legacy hw support.
141 */
142
143 #define E1000_WRITE_REG_IO(hw, reg, value) \
144 E1000_WRITE_REG(hw, reg, value)
145
146 /*
147 * Tested on I217/I218 chipset.
148 */
149
150 #define E1000_READ_FLASH_REG(hw, reg) \
151 e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
152
153 #define E1000_READ_FLASH_REG16(hw, reg) \
154 e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
155
156 #define E1000_WRITE_FLASH_REG(hw, reg, value) \
157 E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
158
159 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \
160 E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
161
162 #define STATIC static
163
164 #ifndef ETH_ADDR_LEN
165 #define ETH_ADDR_LEN 6
166 #endif
167
168 #endif /* _E1000_OSDEP_H_ */
169