Searched refs:PR (Results 1 – 4 of 4) sorted by relevance
| /dpdk/doc/guides/rawdevs/ |
| H A D | ifpga.rst | 11 FPGA uses Partial Reconfigure (PR) Parts of Bit Stream to achieve its
17 By PR (Partial Reconfiguration) AFUs, one FPGA resources can be time-shared by
30 - FPGA PR (Partial Reconfiguration) management
84 but PR and IFPGA Bus scan is triggered by command line using
96 Each FPGA can provide many channels to PR AFU by software, each channels
101 If null, the AFU Bit Stream has been PR in FPGA, if not forces PR and
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| /dpdk/drivers/common/dpaax/caamflib/rta/ |
| H A D | nfifo_cmd.h | 85 { PR, NFIFOENTRY_PR }
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| H A D | sec_run_time_asm.h | 353 #define PR BIT(27) macro
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| /dpdk/drivers/net/axgbe/ |
| H A D | axgbe_ethdev.c | 437 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); in axgbe_dev_promiscuous_enable()
449 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); in axgbe_dev_promiscuous_disable()
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