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Searched refs:PHY (Results 1 – 22 of 22) sorted by relevance

/dpdk/doc/guides/nics/
H A Dpfe.rst71 | PHY | | PHY |
75 The HIF, PFE, MAC and PHY are the hardware blocks, the pfe.ko is a kernel
89 pfe.ko is required for PHY initialisation and also responsible for creating
H A Dtxgbe.rst123 Use to set PHY link mode and enable FFE parameters for user debugging.
129 PHY parameter used for user debugging. Setting other values to
134 PHY parameter used for user debugging. Setting other values to
139 PHY parameter used for user debugging. Setting other values to
H A Denetfec.rst65 | PHY |
70 The MAC and PHY are the hardware blocks.
72 for PHY initialisation and for mapping the allocated memory
H A Ddpaa2.rst191 port/PHY
199 hardware device that connects to an Ethernet PHY and allows
337 PHY
H A Ddpaa.rst109 PHY
/dpdk/devtools/
H A Dwords-case.txt66 PHY
/dpdk/doc/guides/rel_notes/
H A Drelease_2_2.rst69 * Initialized 88E1543 (Marvell 1543) PHY
238 * **e1000/base: Synchronize PHY interface on non-ME systems.**
240 On power up, the MAC - PHY interface needs to be set to PCIe, even if the
278 * **e1000/base: Fix link check for i354 M88E1112 PHY.**
280 The ``e1000_check_for_link_media_swap()`` function is supposed to check PHY
281 page 0 for copper and PHY page 1 for "other" (fiber) links. The driver
311 * **e1000/base: Fix redundant PHY power down for i210.**
313 Bit 11 of PHYREG 0 is used to power down PHY. The use of PHYREG 16 is
H A Drelease_22_03.rst132 * Added support for devices of custom PHY interfaces.
134 - M88E1512 PHY connects to RJ45
135 - M88E1512 PHY connects to RGMII combo
136 - YT8521S PHY connects to SFP
H A Drelease_16_04.rst142 Use the PHY token, shared between software-firmware for PHY access on X550EM_a.
321 speed becomes invalid, therefore the driver reads invalid PHY register values.
322 The driver now set the MDIO clock speed prior to initializing PHY ops and
H A Drelease_21_08.rst105 * **Added Baseband PHY CNXK PMD.**
107 Added Baseband PHY PMD which allows configuration of the BPHY hardware block
H A Dknown_issues.rst764 PHY link up fails when rebinding i40e NICs to kernel driver
769 after DPDK application sets the PHY to link down.
774 function ``i40e_dev_stop()`` which will sets the PHY to link down. Some
776 it retakes control of the device. This is a known PHY link configuration
H A Drelease_16_11.rst72 * Added X550em_a 10G PHY support.
73 * Added support for flow control auto negotiation for X550em_a 1G PHY.
H A Drelease_2_1.rst156 * Added new X550 PHY ids.
160 * Added X557 PHY LEDs support.
628 * **i40e/base: Workaround for PHY type with firmware < 4.4.**
631 * **i40e: Disable setting of PHY configuration.**
H A Drelease_20_02.rst86 * Extended PHY access AQ cmd.
H A Drelease_16_07.rst56 * Added new PHY definitions for M88E1500.
H A Drelease_19_05.rst72 N3000 with SPI interface access, I2C Read/Write, and Ethernet PHY configuration.
/dpdk/drivers/net/qede/
H A Dqede_ethdev.h326 PHY = 7, enumerator
H A Dqede_debug.c7771 PHY = 7, enumerator
/dpdk/doc/guides/prog_guide/
H A Dglossary.rst158 PHY
H A Dpoll_mode_drv.rst166 * Set up the PHY and the link
/dpdk/doc/guides/platform/
H A Dcnxk.rst158 #. **Baseband PHY Driver**
159 See :doc:`../rawdevs/cnxk_bphy` for Baseband PHY driver information.
/dpdk/doc/guides/testpmd_app_ug/
H A Dtestpmd_funcs.rst2098 PMD: eth_ixgbe_dev_init(): MAC: 2, PHY: 18, SFP+: 5