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/dpdk/lib/acl/
H A Dacl_vect.h40 #define ACL_TR_CALC_ADDR(P, S, \ argument
58 r = _##P##_srli_epi32(in, 30); \
59 r = _##P##_add_epi8(r, range_base); \
60 t = _##P##_srli_epi32(in, 24); \
61 r = _##P##_shuffle_epi8(tr_hi, r); \
63 dfa_ofs = _##P##_sub_epi32(t, r); \
66 t = _##P##_cmpgt_epi8(in, tr_hi); \
67 t = _##P##_sign_epi8(t, t); \
68 t = _##P##_maddubs_epi16(t, t); \
69 quad_ofs = _##P##_madd_epi16(t, ones_16); \
[all …]
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_type.h2874 #define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P))) argument
2880 #define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P))) argument
2886 #define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \ argument
2892 #define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \ argument
2894 #define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \ argument
2896 #define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \ argument
2898 #define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \ argument
2900 #define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \ argument
2902 #define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \ argument
2904 #define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \ argument
[all …]
/dpdk/doc/guides/nics/features/
H A Dixgbe_vf.ini22 CRC offload = P
23 VLAN offload = P
24 QinQ offload = P
25 L3 checksum offload = P
26 L4 checksum offload = P
27 Inner L3 checksum = P
28 Inner L4 checksum = P
H A Dtxgbe_vf.ini22 CRC offload = P
23 VLAN offload = P
24 QinQ offload = P
25 L3 checksum offload = P
26 L4 checksum offload = P
27 Inner L3 checksum = P
28 Inner L4 checksum = P
H A Dixgbe.ini31 CRC offload = P
32 VLAN offload = P
33 QinQ offload = P
34 L3 checksum offload = P
35 L4 checksum offload = P
36 MACsec offload = P
37 Inner L3 checksum = P
38 Inner L4 checksum = P
H A Dice_dcf.ini6 ; A feature with "P" indicates only be supported when non-vector path
12 RSS hash = P
14 L3 checksum offload = P
15 L4 checksum offload = P
16 Inner L3 checksum = P
17 Inner L4 checksum = P
H A Dice.ini6 ; A feature with "P" indicates only be supported when non-vector path
14 Fast mbuf free = P
30 QinQ offload = P
31 L3 checksum offload = P
32 L4 checksum offload = P
33 Timestamp offload = P
34 Inner L3 checksum = P
35 Inner L4 checksum = P
H A Dtxgbe.ini30 CRC offload = P
31 VLAN offload = P
32 QinQ offload = P
33 L3 checksum offload = P
34 L4 checksum offload = P
35 Inner L3 checksum = P
36 Inner L4 checksum = P
H A Di40e.ini11 Fast mbuf free = P
32 QinQ offload = P
33 L3 checksum offload = P
34 L4 checksum offload = P
35 Inner L3 checksum = P
36 Inner L4 checksum = P
63 ipv6_frag_ext = P
H A Dvirtio.ini7 Speed capabilities = P
12 Scattered Rx = P
17 RSS hash = P
23 Extended stats = P
H A Diavf.ini25 L3 checksum offload = P
26 L4 checksum offload = P
27 Timestamp offload = P
H A Denetc.ini15 L3 checksum offload = P
16 L4 checksum offload = P
H A Dsfc.ini26 VLAN offload = P
48 mark = P
68 jump = P
H A Docteontx.ini11 Queue start/stop = P
17 VLAN offload = P
H A Docteontx_ep.ini7 Speed capabilities = P
H A Dnfb.ini7 Speed capabilities = P
H A Dbnx2x.ini7 Speed capabilities = P
H A Dnetvsc.ini7 Speed capabilities = P
H A Dvmxnet3.ini7 Speed capabilities = P
H A Dfm10k_vf.ini7 Speed capabilities = P
H A Dthunderx.ini20 VLAN offload = P
H A Dliquidio.ini19 VLAN offload = P
H A Dtap.ini7 Speed capabilities = P
/dpdk/doc/guides/sample_app_ug/
H A Dl3_forward_power_man.rst12 with the power management algorithms to control the P-states and
21 by leveraging the Power library to control P-state and C-state of processor based on packet load.
42 Processor performance states (P-states) are the capability of an Intel processor
50 This application includes a P-state power management algorithm to generate a frequency hint to be s…
127 It changes the P-state governor to userspace for specific cores that are under control.
149 and use them to control P-state and C-state of processors via the power management library.
150 Frequency (P-state) control and sleep state (C-state) control work individually for each logical co…
155 And those numbers of specific queue are passed to P-state and C-state heuristic algorithms
167 P-State Heuristic Algorithm
239 -- -p 0x3 -P --config="(0,0,xx),(1,0,xx)" --empty-poll="0,0,0" -l 14 -m 9 -h 1
[all …]
/dpdk/doc/guides/tools/
H A Dtesteventdev.rst85 P or p : Parallel schedule type
384 The perf queue test configures the eventdev with Q queues and P ports, where
385 Q and P is a function of the number of workers, the number of producers and
513 and P ports, where Q and P is a function of the number of workers and number of
618 The pipeline queue test configures the eventdev with Q queues and P ports,
619 where Q and P is a function of the number of workers, the number of producers
745 The pipeline atq test configures the eventdev with Q queues and P ports,
746 where Q and P is a function of the number of workers, the number of producers

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