1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #ifndef _OTX_EP_COMMON_H_ 5 #define _OTX_EP_COMMON_H_ 6 7 8 #define OTX_EP_NW_PKT_OP 0x1220 9 #define OTX_EP_NW_CMD_OP 0x1221 10 11 #define OTX_EP_MAX_RINGS_PER_VF (8) 12 #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF 13 #define OTX_EP_64BYTE_INSTR (64) 14 #define OTX_EP_MIN_IQ_DESCRIPTORS (128) 15 #define OTX_EP_MIN_OQ_DESCRIPTORS (128) 16 #define OTX_EP_MAX_IQ_DESCRIPTORS (8192) 17 #define OTX_EP_MAX_OQ_DESCRIPTORS (8192) 18 #define OTX_EP_OQ_BUF_SIZE (2048) 19 #define OTX_EP_MIN_RX_BUF_SIZE (64) 20 21 #define OTX_EP_OQ_INFOPTR_MODE (0) 22 #define OTX_EP_OQ_REFIL_THRESHOLD (16) 23 24 /* IQ instruction req types */ 25 #define OTX_EP_REQTYPE_NONE (0) 26 #define OTX_EP_REQTYPE_NORESP_INSTR (1) 27 #define OTX_EP_REQTYPE_NORESP_NET_DIRECT (2) 28 #define OTX_EP_REQTYPE_NORESP_NET OTX_EP_REQTYPE_NORESP_NET_DIRECT 29 #define OTX_EP_REQTYPE_NORESP_GATHER (3) 30 #define OTX_EP_NORESP_OHSM_SEND (4) 31 #define OTX_EP_NORESP_LAST (4) 32 #define OTX_EP_PCI_RING_ALIGN 65536 33 #define SDP_PKIND 40 34 #define SDP_OTX2_PKIND 57 35 36 #define ORDERED_TAG 0 37 #define ATOMIC_TAG 1 38 #define NULL_TAG 2 39 #define NULL_NULL_TAG 3 40 41 #define OTX_EP_BUSY_LOOP_COUNT (10000) 42 #define OTX_EP_MAX_IOQS_PER_VF 8 43 #define OTX_CUST_DATA_LEN 0 44 45 #define otx_ep_info(fmt, args...) \ 46 rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \ 47 "%s():%u " fmt "\n", \ 48 __func__, __LINE__, ##args) 49 50 #define otx_ep_err(fmt, args...) \ 51 rte_log(RTE_LOG_ERR, otx_net_ep_logtype, \ 52 "%s():%u " fmt "\n", \ 53 __func__, __LINE__, ##args) 54 55 #define otx_ep_dbg(fmt, args...) \ 56 rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \ 57 "%s():%u " fmt "\n", \ 58 __func__, __LINE__, ##args) 59 60 /* Input Request Header format */ 61 union otx_ep_instr_irh { 62 uint64_t u64; 63 struct { 64 /* Request ID */ 65 uint64_t rid:16; 66 67 /* PCIe port to use for response */ 68 uint64_t pcie_port:3; 69 70 /* Scatter indicator 1=scatter */ 71 uint64_t scatter:1; 72 73 /* Size of Expected result OR no. of entries in scatter list */ 74 uint64_t rlenssz:14; 75 76 /* Desired destination port for result */ 77 uint64_t dport:6; 78 79 /* Opcode Specific parameters */ 80 uint64_t param:8; 81 82 /* Opcode for the return packet */ 83 uint64_t opcode:16; 84 } s; 85 }; 86 87 #define otx_ep_write64(value, base_addr, reg_off) \ 88 {\ 89 typeof(value) val = (value); \ 90 typeof(reg_off) off = (reg_off); \ 91 otx_ep_dbg("octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\n", \ 92 (unsigned long)off, (unsigned long long)val); \ 93 rte_write64(val, ((base_addr) + off)); \ 94 } 95 96 /* Instruction Header - for OCTEON-TX models */ 97 typedef union otx_ep_instr_ih { 98 uint64_t u64; 99 struct { 100 /** Data Len */ 101 uint64_t tlen:16; 102 103 /** Reserved */ 104 uint64_t rsvd:20; 105 106 /** PKIND for OTX_EP */ 107 uint64_t pkind:6; 108 109 /** Front Data size */ 110 uint64_t fsz:6; 111 112 /** No. of entries in gather list */ 113 uint64_t gsz:14; 114 115 /** Gather indicator 1=gather*/ 116 uint64_t gather:1; 117 118 /** Reserved3 */ 119 uint64_t reserved3:1; 120 } s; 121 } otx_ep_instr_ih_t; 122 123 /* OTX_EP IQ request list */ 124 struct otx_ep_instr_list { 125 void *buf; 126 uint32_t reqtype; 127 }; 128 #define OTX_EP_IQREQ_LIST_SIZE (sizeof(struct otx_ep_instr_list)) 129 130 /* Input Queue statistics. Each input queue has four stats fields. */ 131 struct otx_ep_iq_stats { 132 uint64_t instr_posted; /* Instructions posted to this queue. */ 133 uint64_t instr_processed; /* Instructions processed in this queue. */ 134 uint64_t instr_dropped; /* Instructions that could not be processed */ 135 uint64_t tx_pkts; 136 uint64_t tx_bytes; 137 }; 138 139 /* Structure to define the configuration attributes for each Input queue. */ 140 struct otx_ep_iq_config { 141 /* Max number of IQs available */ 142 uint16_t max_iqs; 143 144 /* Command size - 32 or 64 bytes */ 145 uint16_t instr_type; 146 147 /* Pending list size, usually set to the sum of the size of all IQs */ 148 uint32_t pending_list_size; 149 }; 150 151 /** The instruction (input) queue. 152 * The input queue is used to post raw (instruction) mode data or packet data 153 * to OCTEON 9 device from the host. Each IQ of a OTX_EP EP VF device has one 154 * such structure to represent it. 155 */ 156 struct otx_ep_instr_queue { 157 struct otx_ep_device *otx_ep_dev; 158 159 uint32_t q_no; 160 uint32_t pkt_in_done; 161 162 /* Flag for 64 byte commands. */ 163 uint32_t iqcmd_64B:1; 164 uint32_t rsvd:17; 165 uint32_t status:8; 166 167 /* Number of descriptors in this ring. */ 168 uint32_t nb_desc; 169 170 /* Input ring index, where the driver should write the next packet */ 171 uint32_t host_write_index; 172 173 /* Input ring index, where the OCTEON 9 should read the next packet */ 174 uint32_t otx_read_index; 175 176 uint32_t reset_instr_cnt; 177 178 /** This index aids in finding the window in the queue where OCTEON 9 179 * has read the commands. 180 */ 181 uint32_t flush_index; 182 183 /* This keeps track of the instructions pending in this queue. */ 184 uint64_t instr_pending; 185 186 /* Pointer to the Virtual Base addr of the input ring. */ 187 uint8_t *base_addr; 188 189 /* This IQ request list */ 190 struct otx_ep_instr_list *req_list; 191 192 /* OTX_EP doorbell register for the ring. */ 193 void *doorbell_reg; 194 195 /* OTX_EP instruction count register for this ring. */ 196 void *inst_cnt_reg; 197 198 /* Number of instructions pending to be posted to OCTEON 9. */ 199 uint32_t fill_cnt; 200 201 /* Statistics for this input queue. */ 202 struct otx_ep_iq_stats stats; 203 204 /* DMA mapped base address of the input descriptor ring. */ 205 uint64_t base_addr_dma; 206 207 /* Memory zone */ 208 const struct rte_memzone *iq_mz; 209 }; 210 211 /** Descriptor format. 212 * The descriptor ring is made of descriptors which have 2 64-bit values: 213 * -# Physical (bus) address of the data buffer. 214 * -# Physical (bus) address of a otx_ep_droq_info structure. 215 * The device DMA's incoming packets and its information at the address 216 * given by these descriptor fields. 217 */ 218 struct otx_ep_droq_desc { 219 /* The buffer pointer */ 220 uint64_t buffer_ptr; 221 222 /* The Info pointer */ 223 uint64_t info_ptr; 224 }; 225 #define OTX_EP_DROQ_DESC_SIZE (sizeof(struct otx_ep_droq_desc)) 226 227 /* Receive Header */ 228 union otx_ep_rh { 229 uint64_t rh64; 230 }; 231 #define OTX_EP_RH_SIZE (sizeof(union otx_ep_rh)) 232 233 /** Information about packet DMA'ed by OCTEON 9. 234 * The format of the information available at Info Pointer after OCTEON 9 235 * has posted a packet. Not all descriptors have valid information. Only 236 * the Info field of the first descriptor for a packet has information 237 * about the packet. 238 */ 239 struct otx_ep_droq_info { 240 /* The Length of the packet. */ 241 uint64_t length; 242 243 /* The Output Receive Header. */ 244 union otx_ep_rh rh; 245 }; 246 #define OTX_EP_DROQ_INFO_SIZE (sizeof(struct otx_ep_droq_info)) 247 248 /* DROQ statistics. Each output queue has four stats fields. */ 249 struct otx_ep_droq_stats { 250 /* Number of packets received in this queue. */ 251 uint64_t pkts_received; 252 253 /* Bytes received by this queue. */ 254 uint64_t bytes_received; 255 256 /* Num of failures of rte_pktmbuf_alloc() */ 257 uint64_t rx_alloc_failure; 258 259 /* Rx error */ 260 uint64_t rx_err; 261 262 /* packets with data got ready after interrupt arrived */ 263 uint64_t pkts_delayed_data; 264 265 /* packets dropped due to zero length */ 266 uint64_t dropped_zlp; 267 }; 268 269 /* Structure to define the configuration attributes for each Output queue. */ 270 struct otx_ep_oq_config { 271 /* Max number of OQs available */ 272 uint16_t max_oqs; 273 274 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */ 275 uint16_t info_ptr; 276 277 /** The number of buffers that were consumed during packet processing by 278 * the driver on this Output queue before the driver attempts to 279 * replenish the descriptor ring with new buffers. 280 */ 281 uint32_t refill_threshold; 282 }; 283 284 /* The Descriptor Ring Output Queue(DROQ) structure. */ 285 struct otx_ep_droq { 286 struct otx_ep_device *otx_ep_dev; 287 /* The 8B aligned descriptor ring starts at this address. */ 288 struct otx_ep_droq_desc *desc_ring; 289 290 uint32_t q_no; 291 uint64_t last_pkt_count; 292 293 struct rte_mempool *mpool; 294 295 /* Driver should read the next packet at this index */ 296 uint32_t read_idx; 297 298 /* OCTEON 9 will write the next packet at this index */ 299 uint32_t write_idx; 300 301 /* At this index, the driver will refill the descriptor's buffer */ 302 uint32_t refill_idx; 303 304 /* Packets pending to be processed */ 305 uint64_t pkts_pending; 306 307 /* Number of descriptors in this ring. */ 308 uint32_t nb_desc; 309 310 /* The number of descriptors pending to refill. */ 311 uint32_t refill_count; 312 313 uint32_t refill_threshold; 314 315 /* The 8B aligned info ptrs begin from this address. */ 316 struct otx_ep_droq_info *info_list; 317 318 /* receive buffer list contains mbuf ptr list */ 319 struct rte_mbuf **recv_buf_list; 320 321 /* The size of each buffer pointed by the buffer pointer. */ 322 uint32_t buffer_size; 323 324 /** Pointer to the mapped packet credit register. 325 * Host writes number of info/buffer ptrs available to this register 326 */ 327 void *pkts_credit_reg; 328 329 /** Pointer to the mapped packet sent register. OCTEON 9 writes the 330 * number of packets DMA'ed to host memory in this register. 331 */ 332 void *pkts_sent_reg; 333 334 /* Statistics for this DROQ. */ 335 struct otx_ep_droq_stats stats; 336 337 /* DMA mapped address of the DROQ descriptor ring. */ 338 size_t desc_ring_dma; 339 340 /* Info_ptr list is allocated at this virtual address. */ 341 size_t info_base_addr; 342 343 /* DMA mapped address of the info list */ 344 size_t info_list_dma; 345 346 /* Allocated size of info list. */ 347 uint32_t info_alloc_size; 348 349 /* Memory zone **/ 350 const struct rte_memzone *desc_ring_mz; 351 352 const struct rte_memzone *info_mz; 353 }; 354 #define OTX_EP_DROQ_SIZE (sizeof(struct otx_ep_droq)) 355 356 /* IQ/OQ mask */ 357 struct otx_ep_io_enable { 358 uint64_t iq; 359 uint64_t oq; 360 uint64_t iq64B; 361 }; 362 363 /* Structure to define the configuration. */ 364 struct otx_ep_config { 365 /* Input Queue attributes. */ 366 struct otx_ep_iq_config iq; 367 368 /* Output Queue attributes. */ 369 struct otx_ep_oq_config oq; 370 371 /* Num of desc for IQ rings */ 372 uint32_t num_iqdef_descs; 373 374 /* Num of desc for OQ rings */ 375 uint32_t num_oqdef_descs; 376 377 /* OQ buffer size */ 378 uint32_t oqdef_buf_size; 379 }; 380 381 /* SRIOV information */ 382 struct otx_ep_sriov_info { 383 /* Number of rings assigned to VF */ 384 uint32_t rings_per_vf; 385 386 /* Number of VF devices enabled */ 387 uint32_t num_vfs; 388 }; 389 390 /* Required functions for each VF device */ 391 struct otx_ep_fn_list { 392 void (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no); 393 394 void (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no); 395 396 void (*setup_device_regs)(struct otx_ep_device *otx_ep); 397 398 int (*enable_io_queues)(struct otx_ep_device *otx_ep); 399 void (*disable_io_queues)(struct otx_ep_device *otx_ep); 400 401 int (*enable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no); 402 void (*disable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no); 403 404 int (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no); 405 void (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no); 406 }; 407 408 /* OTX_EP EP VF device data structure */ 409 struct otx_ep_device { 410 /* PCI device pointer */ 411 struct rte_pci_device *pdev; 412 413 uint16_t chip_id; 414 415 uint32_t pkind; 416 417 struct rte_eth_dev *eth_dev; 418 419 int port_id; 420 421 /* Memory mapped h/w address */ 422 uint8_t *hw_addr; 423 424 struct otx_ep_fn_list fn_list; 425 426 uint32_t max_tx_queues; 427 428 uint32_t max_rx_queues; 429 430 /* Num IQs */ 431 uint32_t nb_tx_queues; 432 433 /* The input instruction queues */ 434 struct otx_ep_instr_queue *instr_queue[OTX_EP_MAX_IOQS_PER_VF]; 435 436 /* Num OQs */ 437 uint32_t nb_rx_queues; 438 439 /* The DROQ output queues */ 440 struct otx_ep_droq *droq[OTX_EP_MAX_IOQS_PER_VF]; 441 442 /* IOQ mask */ 443 struct otx_ep_io_enable io_qmask; 444 445 /* SR-IOV info */ 446 struct otx_ep_sriov_info sriov_info; 447 448 /* Device configuration */ 449 const struct otx_ep_config *conf; 450 451 uint64_t rx_offloads; 452 453 uint64_t tx_offloads; 454 }; 455 456 int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no, 457 int num_descs, unsigned int socket_id); 458 int otx_ep_delete_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no); 459 460 int otx_ep_setup_oqs(struct otx_ep_device *otx_ep, int oq_no, int num_descs, 461 int desc_size, struct rte_mempool *mpool, 462 unsigned int socket_id); 463 int otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no); 464 465 struct otx_ep_sg_entry { 466 /** The first 64 bit gives the size of data in each dptr. */ 467 union { 468 uint16_t size[4]; 469 uint64_t size64; 470 } u; 471 472 /** The 4 dptr pointers for this entry. */ 473 uint64_t ptr[4]; 474 }; 475 476 #define OTX_EP_SG_ENTRY_SIZE (sizeof(struct otx_ep_sg_entry)) 477 478 /** Structure of a node in list of gather components maintained by 479 * driver for each network device. 480 */ 481 struct otx_ep_gather { 482 /** number of gather entries. */ 483 int num_sg; 484 485 /** Gather component that can accommodate max sized fragment list 486 * received from the IP layer. 487 */ 488 struct otx_ep_sg_entry *sg; 489 }; 490 491 struct otx_ep_buf_free_info { 492 struct rte_mbuf *mbuf; 493 struct otx_ep_gather g; 494 }; 495 496 #define OTX_EP_MAX_PKT_SZ 64000U 497 #define OTX_EP_MAX_MAC_ADDRS 1 498 #define OTX_EP_SG_ALIGN 8 499 #define OTX_EP_CLEAR_ISIZE_BSIZE 0x7FFFFFULL 500 #define OTX_EP_CLEAR_OUT_INT_LVLS 0x3FFFFFFFFFFFFFULL 501 #define OTX_EP_CLEAR_IN_INT_LVLS 0xFFFFFFFF 502 #define OTX_EP_CLEAR_SDP_IN_INT_LVLS 0x3FFFFFFFFFFFFFUL 503 #define OTX_EP_DROQ_BUFSZ_MASK 0xFFFF 504 #define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF 505 #define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF 506 507 /* PCI IDs */ 508 #define PCI_VENDOR_ID_CAVIUM 0x177D 509 510 extern int otx_net_ep_logtype; 511 #endif /* _OTX_EP_COMMON_H_ */ 512