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Searched refs:MS16 (Results 1 – 6 of 6) sorted by relevance

/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_mvl.h14 #define MVL_CTRL_RESET MS16(15, 0x1)
16 #define MVL_CTRL_ANE MS16(12, 0x1)
17 #define MVL_CTRL_PWDN MS16(11, 0x1)
18 #define MVL_CTRL_RESTART_AN MS16(9, 0x1)
19 #define MVL_CTRL_DUPLEX MS16(8, 0x1)
24 #define MVL_CANA_PAUSE MS16(10, 0x1)
49 #define MVL_PHYSR_LINK MS16(10, 0x1)
54 #define MVL_INTR_ANC MS16(11, 0x1)
55 #define MVL_INTR_LSC MS16(10, 0x1)
63 #define MVL_LEDFCR_CTL1 MS16(4, 0xF)
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H A Dngbe_phy_yt.h14 #define YT_SMI_PHY_SW_RST MS16(15, 0x1)
17 #define YT_CHIP_SW_RST MS16(15, 0x1)
18 #define YT_CHIP_SW_LDO_EN MS16(6, 0x1)
19 #define YT_CHIP_MODE_MASK MS16(0, 0x7)
22 #define YT_RGMII_CONF1_MODE MS16(15, 0x1)
36 #define YT_BCR_RESET MS16(15, 0x1)
38 #define YT_BCR_ANE MS16(12, 0x1)
39 #define YT_BCR_PWDN MS16(11, 0x1)
40 #define YT_BCR_RESTART_AN MS16(9, 0x1)
41 #define YT_BCR_DUPLEX MS16(8, 0x1)
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H A Dngbe_phy_rtl.h15 #define RTL_BMCR_RESET MS16(15, 0x1)
17 #define RTL_BMCR_ANE MS16(12, 0x1)
19 #define RTL_BMCR_DUPLEX MS16(8, 0x1)
22 #define RTL_BMSR_ANC MS16(5, 0x1)
29 #define RTL_ANAR_100F MS16(8, 0x1)
30 #define RTL_ANAR_100H MS16(7, 0x1)
31 #define RTL_ANAR_10F MS16(6, 0x1)
32 #define RTL_ANAR_10H MS16(5, 0x1)
39 #define RTL_GSR_ST MS16(0, 0x7)
42 #define RTL_INER_LSC MS16(4, 0x1)
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H A Dngbe_regs.h20 #define MS16(shift, mask) (((u16)(mask)) << (shift)) macro
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.h23 #define SR_XS_PCS_KR_STS1_PLU MS16(12, 0x1)
30 #define SR_PMA_KR_PMD_CTRL_EN_TR MS16(1, 0x1)
31 #define SR_PMA_KR_PMD_CTRL_RS_TR MS16(0, 0x1)
34 #define SR_PMA_KR_PMD_STS_RCV MS16(0, 0x1)
37 #define SR_PMA_KR_LP_CESTS_RR MS16(15, 0x1)
40 #define SR_PMA_KR_LD_CESTS_RR MS16(15, 0x1)
42 #define SR_PMA_KR_FEC_CTRL_EN MS16(0, 0x1)
96 #define SR_AN_XNP_TX1_NP MS16(15, 0x1)
105 #define VR_AN_INTR_CMPLT MS16(0, 0x1)
106 #define VR_AN_INTR_LINK MS16(1, 0x1)
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H A Dtxgbe_regs.h20 #define MS16(shift, mask) (((u16)(mask)) << (shift)) macro