Searched refs:MLX5_WQE_DSEG_SIZE (Results 1 – 5 of 5) sorted by relevance
834 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE); in txq_set_params()835 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE; in txq_set_params()837 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE; in txq_set_params()842 MLX5_WQE_DSEG_SIZE * 2); in txq_set_params()864 MLX5_WQE_DSEG_SIZE * 2); in txq_set_params()905 MLX5_WQE_DSEG_SIZE); in txq_set_params()919 MLX5_WQE_DSEG_SIZE); in txq_set_params()
2828 MLX5_WQE_DSEG_SIZE)); in mlx5_tx_burst_empw_inline()2836 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE); in mlx5_tx_burst_empw_inline()2837 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0); in mlx5_tx_burst_empw_inline()2944 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE); in mlx5_tx_burst_empw_inline()2952 room -= MLX5_WQE_DSEG_SIZE; in mlx5_tx_burst_empw_inline()3018 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE)) in mlx5_tx_burst_empw_inline()3206 MLX5_WQE_DSEG_SIZE + in mlx5_tx_burst_single_send()3209 MLX5_WQE_DSEG_SIZE + in mlx5_tx_burst_single_send()
292 MLX5_WQE_DSEG_SIZE * 2); in mlx5_set_txlimit_params()297 MLX5_WQE_DSEG_SIZE - in mlx5_set_txlimit_params()
75 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) macro81 MLX5_WQE_DSEG_SIZE + \112 MLX5_WQE_DSEG_SIZE)120 MLX5_WQE_DSEG_SIZE + \