Searched refs:MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO (Results 1 – 2 of 2) sorted by relevance
785 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | in mlx5_devx_tir_attr_set()
2449 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, enumerator