Searched refs:MLX5_DBR_SIZE (Results 1 – 2 of 2) sorted by relevance
106 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_devx_cq_create()107 umem_size += MLX5_DBR_SIZE; in mlx5_devx_cq_create()224 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_devx_sq_create()225 umem_size += MLX5_DBR_SIZE; in mlx5_devx_sq_create()369 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_devx_qp_create()370 umem_size += MLX5_DBR_SIZE; in mlx5_devx_qp_create()475 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_devx_wq_init()476 umem_size += MLX5_DBR_SIZE; in mlx5_devx_wq_init()
269 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE macro