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Searched refs:IGU_REG_PF_CONFIGURATION (Results 1 – 4 of 4) sorted by relevance

/dpdk/drivers/net/qede/base/
H A Decore_int.c1957 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); in ecore_int_igu_enable_int()
2018 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); in ecore_int_igu_disable_int()
2763 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); in ecore_pf_flr_igu_cleanup()
H A Dreg_addr.h348 #define IGU_REG_PF_CONFIGURATION \ macro
/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c5609 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_enable()
5629 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
5638 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
5689 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_disable()
5699 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
5700 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) { in bnx2x_igu_int_disable()
9972 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9976 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
11218 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
H A Decore_reg.h464 #define IGU_REG_PF_CONFIGURATION 0x130154 macro