1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
3 */
4
5 #ifndef _ICE_TYPE_H_
6 #define _ICE_TYPE_H_
7
8 #define ETH_ALEN 6
9
10 #define ETH_HEADER_LEN 14
11
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
14
15 #define BITS_PER_BYTE 8
16
17 #define _FORCE_
18
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
22
23 /**
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
27 *
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
30 */
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
32
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
34
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
36
37 #define STRUCT_HACK_VAR_LEN
38 /**
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
43 */
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
46
47 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
48
49 #include "ice_status.h"
50 #include "ice_hw_autogen.h"
51 #include "ice_devids.h"
52 #include "ice_osdep.h"
53 #include "ice_bitops.h" /* Must come before ice_controlq.h */
54 #include "ice_controlq.h"
55 #include "ice_lan_tx_rx.h"
56 #include "ice_flex_type.h"
57 #include "ice_protocol_type.h"
58 #include "ice_sbq_cmd.h"
59 #include "ice_vlan_mode.h"
60
61 /**
62 * ice_is_pow2 - check if integer value is a power of 2
63 * @val: unsigned integer to be validated
64 */
ice_is_pow2(u64 val)65 static inline bool ice_is_pow2(u64 val)
66 {
67 return (val && !(val & (val - 1)));
68 }
69
70 /**
71 * ice_ilog2 - Calculates integer log base 2 of a number
72 * @n: number on which to perform operation
73 */
ice_ilog2(u64 n)74 static inline int ice_ilog2(u64 n)
75 {
76 int i;
77
78 for (i = 63; i >= 0; i--)
79 if (((u64)1 << i) & n)
80 return i;
81
82 return -1;
83 }
84
ice_is_tc_ena(ice_bitmap_t bitmap,u8 tc)85 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
86 {
87 return ice_is_bit_set(&bitmap, tc);
88 }
89
90 #define DIV_64BIT(n, d) ((n) / (d))
91
round_up_64bit(u64 a,u32 b)92 static inline u64 round_up_64bit(u64 a, u32 b)
93 {
94 return DIV_64BIT(((a) + (b) / 2), (b));
95 }
96
ice_round_to_num(u32 N,u32 R)97 static inline u32 ice_round_to_num(u32 N, u32 R)
98 {
99 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
100 ((((N) + (R) - 1) / (R)) * (R)));
101 }
102
103 /* Driver always calls main vsi_handle first */
104 #define ICE_MAIN_VSI_HANDLE 0
105
106 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
107 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
108
109 /* Data type manipulation macros. */
110 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
111 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
112 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
113 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
114
115 /* debug masks - set these bits in hw->debug_mask to control output */
116 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
117 #define ICE_DBG_INIT BIT_ULL(1)
118 #define ICE_DBG_RELEASE BIT_ULL(2)
119 #define ICE_DBG_FW_LOG BIT_ULL(3)
120 #define ICE_DBG_LINK BIT_ULL(4)
121 #define ICE_DBG_PHY BIT_ULL(5)
122 #define ICE_DBG_QCTX BIT_ULL(6)
123 #define ICE_DBG_NVM BIT_ULL(7)
124 #define ICE_DBG_LAN BIT_ULL(8)
125 #define ICE_DBG_FLOW BIT_ULL(9)
126 #define ICE_DBG_DCB BIT_ULL(10)
127 #define ICE_DBG_DIAG BIT_ULL(11)
128 #define ICE_DBG_FD BIT_ULL(12)
129 #define ICE_DBG_SW BIT_ULL(13)
130 #define ICE_DBG_SCHED BIT_ULL(14)
131
132 #define ICE_DBG_PKG BIT_ULL(16)
133 #define ICE_DBG_RES BIT_ULL(17)
134 #define ICE_DBG_ACL BIT_ULL(18)
135 #define ICE_DBG_PTP BIT_ULL(19)
136 #define ICE_DBG_AQ_MSG BIT_ULL(24)
137 #define ICE_DBG_AQ_DESC BIT_ULL(25)
138 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
139 #define ICE_DBG_AQ_CMD BIT_ULL(27)
140 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
141 ICE_DBG_AQ_DESC | \
142 ICE_DBG_AQ_DESC_BUF | \
143 ICE_DBG_AQ_CMD)
144 #define ICE_DBG_PARSER BIT_ULL(28)
145
146 #define ICE_DBG_USER BIT_ULL(31)
147 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
148
149 #define __ALWAYS_UNUSED
150
151 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
152 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
153 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
154 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
155
156 enum ice_aq_res_ids {
157 ICE_NVM_RES_ID = 1,
158 ICE_SPD_RES_ID,
159 ICE_CHANGE_LOCK_RES_ID,
160 ICE_GLOBAL_CFG_LOCK_RES_ID
161 };
162
163 /* FW update timeout definitions are in milliseconds */
164 #define ICE_NVM_TIMEOUT 180000
165 #define ICE_CHANGE_LOCK_TIMEOUT 1000
166 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
167
168 enum ice_aq_res_access_type {
169 ICE_RES_READ = 1,
170 ICE_RES_WRITE
171 };
172
173 struct ice_driver_ver {
174 u8 major_ver;
175 u8 minor_ver;
176 u8 build_ver;
177 u8 subbuild_ver;
178 u8 driver_string[32];
179 };
180
181 enum ice_fc_mode {
182 ICE_FC_NONE = 0,
183 ICE_FC_RX_PAUSE,
184 ICE_FC_TX_PAUSE,
185 ICE_FC_FULL,
186 ICE_FC_AUTO,
187 ICE_FC_PFC,
188 ICE_FC_DFLT
189 };
190
191 enum ice_phy_cache_mode {
192 ICE_FC_MODE = 0,
193 ICE_SPEED_MODE,
194 ICE_FEC_MODE
195 };
196
197 enum ice_fec_mode {
198 ICE_FEC_NONE = 0,
199 ICE_FEC_RS,
200 ICE_FEC_BASER,
201 ICE_FEC_AUTO
202 };
203
204 struct ice_phy_cache_mode_data {
205 union {
206 enum ice_fec_mode curr_user_fec_req;
207 enum ice_fc_mode curr_user_fc_req;
208 u16 curr_user_speed_req;
209 } data;
210 };
211
212 enum ice_set_fc_aq_failures {
213 ICE_SET_FC_AQ_FAIL_NONE = 0,
214 ICE_SET_FC_AQ_FAIL_GET,
215 ICE_SET_FC_AQ_FAIL_SET,
216 ICE_SET_FC_AQ_FAIL_UPDATE
217 };
218
219 /* These are structs for managing the hardware information and the operations */
220 /* MAC types */
221 enum ice_mac_type {
222 ICE_MAC_UNKNOWN = 0,
223 ICE_MAC_E810,
224 ICE_MAC_GENERIC,
225 };
226
227 /* Media Types */
228 enum ice_media_type {
229 ICE_MEDIA_UNKNOWN = 0,
230 ICE_MEDIA_FIBER,
231 ICE_MEDIA_BASET,
232 ICE_MEDIA_BACKPLANE,
233 ICE_MEDIA_DA,
234 ICE_MEDIA_AUI,
235 };
236
237 /* Software VSI types. */
238 enum ice_vsi_type {
239 ICE_VSI_PF = 0,
240 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
241 ICE_VSI_LB = 6,
242 };
243
244 struct ice_link_status {
245 /* Refer to ice_aq_phy_type for bits definition */
246 u64 phy_type_low;
247 u64 phy_type_high;
248 u8 topo_media_conflict;
249 u16 max_frame_size;
250 u16 link_speed;
251 u16 req_speeds;
252 u8 link_cfg_err;
253 u8 lse_ena; /* Link Status Event notification */
254 u8 link_info;
255 u8 an_info;
256 u8 ext_info;
257 u8 fec_info;
258 u8 pacing;
259 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
260 * ice_aqc_get_phy_caps structure
261 */
262 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
263 };
264
265 /* Different data queue types: These are mainly for SW consumption. */
266 enum ice_q {
267 ICE_DATA_Q_DOORBELL,
268 ICE_DATA_Q_CMPL,
269 ICE_DATA_Q_QUANTA,
270 ICE_DATA_Q_RX,
271 ICE_DATA_Q_TX,
272 };
273
274 /* Different reset sources for which a disable queue AQ call has to be made in
275 * order to clean the Tx scheduler as a part of the reset
276 */
277 enum ice_disq_rst_src {
278 ICE_NO_RESET = 0,
279 ICE_VM_RESET,
280 };
281
282 /* PHY info such as phy_type, etc... */
283 struct ice_phy_info {
284 struct ice_link_status link_info;
285 struct ice_link_status link_info_old;
286 u64 phy_type_low;
287 u64 phy_type_high;
288 enum ice_media_type media_type;
289 u8 get_link_info;
290 /* Please refer to struct ice_aqc_get_link_status_data to get
291 * detail of enable bit in curr_user_speed_req
292 */
293 u16 curr_user_speed_req;
294 enum ice_fec_mode curr_user_fec_req;
295 enum ice_fc_mode curr_user_fc_req;
296 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
297 };
298
299 #define ICE_MAX_NUM_MIRROR_RULES 64
300
301 /* protocol enumeration for filters */
302 enum ice_fltr_ptype {
303 /* NONE - used for undef/error */
304 ICE_FLTR_PTYPE_NONF_NONE = 0,
305 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
306 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
307 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
308 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
309 ICE_FLTR_PTYPE_NONF_IPV4_GTPU,
310 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
311 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
312 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
313 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
314 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
315 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
316 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH,
317 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
318 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
319 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
320 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6,
321 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP,
322 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP,
323 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW,
324 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4,
325 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP,
326 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP,
327 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6,
328 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP,
329 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP,
330 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP,
331 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4,
332 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP,
333 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP,
334 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6,
335 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP,
336 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP,
337 ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
338 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH,
339 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW,
340 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP,
341 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
342 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
343 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
344 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
345 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
346 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
347 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
348 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
349 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
350 ICE_FLTR_PTYPE_NONF_IPV4_AH,
351 ICE_FLTR_PTYPE_NONF_IPV6_AH,
352 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
353 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
354 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
355 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
356 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
357 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
358 ICE_FLTR_PTYPE_NON_IP_L2,
359 ICE_FLTR_PTYPE_NONF_ECPRI_TP0,
360 ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
361 ICE_FLTR_PTYPE_FRAG_IPV4,
362 ICE_FLTR_PTYPE_FRAG_IPV6,
363 ICE_FLTR_PTYPE_NONF_IPV4_GRE,
364 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4,
365 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_UDP,
366 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_TCP,
367 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6,
368 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_UDP,
369 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_TCP,
370 ICE_FLTR_PTYPE_NONF_IPV6_GRE,
371 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4,
372 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_UDP,
373 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_TCP,
374 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6,
375 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP,
376 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP,
377 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU,
378 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4,
379 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_UDP,
380 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_TCP,
381 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6,
382 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_UDP,
383 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_TCP,
384 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU,
385 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4,
386 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4_UDP,
387 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4_TCP,
388 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6,
389 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6_UDP,
390 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6_TCP,
391 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU,
392 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4,
393 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_UDP,
394 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_TCP,
395 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6,
396 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_UDP,
397 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_TCP,
398 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU,
399 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4,
400 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4_UDP,
401 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4_TCP,
402 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6,
403 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6_UDP,
404 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6_TCP,
405 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH,
406 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4,
407 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_UDP,
408 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_TCP,
409 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6,
410 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_UDP,
411 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_TCP,
412 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH,
413 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4,
414 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4_UDP,
415 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4_TCP,
416 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6,
417 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6_UDP,
418 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6_TCP,
419 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH,
420 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4,
421 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_UDP,
422 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_TCP,
423 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6,
424 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_UDP,
425 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_TCP,
426 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH,
427 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4,
428 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4_UDP,
429 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4_TCP,
430 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6,
431 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6_UDP,
432 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6_TCP,
433 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW,
434 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4,
435 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
436 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
437 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6,
438 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
439 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
440 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW,
441 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4,
442 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4_UDP,
443 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4_TCP,
444 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6,
445 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6_UDP,
446 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6_TCP,
447 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW,
448 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4,
449 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
450 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
451 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6,
452 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
453 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
454 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW,
455 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4,
456 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4_UDP,
457 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4_TCP,
458 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6,
459 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6_UDP,
460 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6_TCP,
461 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP,
462 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4,
463 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
464 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
465 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6,
466 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
467 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
468 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP,
469 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4,
470 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4_UDP,
471 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4_TCP,
472 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6,
473 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6_UDP,
474 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6_TCP,
475 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP,
476 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4,
477 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
478 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
479 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6,
480 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
481 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
482 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP,
483 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4,
484 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4_UDP,
485 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4_TCP,
486 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6,
487 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6_UDP,
488 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6_TCP,
489 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
490 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
491 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
492 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
493 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,
494 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_UDP,
495 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_TCP,
496 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_SCTP,
497 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_OTHER,
498 ICE_FLTR_PTYPE_MAX,
499 };
500
501 enum ice_fd_hw_seg {
502 ICE_FD_HW_SEG_NON_TUN = 0,
503 ICE_FD_HW_SEG_TUN,
504 ICE_FD_HW_SEG_MAX,
505 };
506
507 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
508 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
509
510 struct ice_fd_hw_prof {
511 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
512 int cnt;
513 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
514 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
515 };
516
517 /* Common HW capabilities for SW use */
518 struct ice_hw_common_caps {
519 /* Write CSR protection */
520 u64 wr_csr_prot;
521 u32 switching_mode;
522 /* switching mode supported - EVB switching (including cloud) */
523 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
524
525 /* Manageablity mode & supported protocols over MCTP */
526 u32 mgmt_mode;
527 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
528 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
529 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
530
531 u32 mgmt_protocols_mctp;
532 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
533 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
534 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
535 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
536
537 u32 os2bmc;
538 u32 valid_functions;
539 /* DCB capabilities */
540 u32 active_tc_bitmap;
541 u32 maxtc;
542
543 /* RSS related capabilities */
544 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
545 u32 rss_table_entry_width; /* RSS Entry width in bits */
546
547 /* Tx/Rx queues */
548 u32 num_rxq; /* Number/Total Rx queues */
549 u32 rxq_first_id; /* First queue ID for Rx queues */
550 u32 num_txq; /* Number/Total Tx queues */
551 u32 txq_first_id; /* First queue ID for Tx queues */
552
553 /* MSI-X vectors */
554 u32 num_msix_vectors;
555 u32 msix_vector_first_id;
556
557 /* Max MTU for function or device */
558 u32 max_mtu;
559
560 /* WOL related */
561 u32 num_wol_proxy_fltr;
562 u32 wol_proxy_vsi_seid;
563
564 /* LED/SDP pin count */
565 u32 led_pin_num;
566 u32 sdp_pin_num;
567
568 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
569 #define ICE_MAX_SUPPORTED_GPIO_LED 12
570 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
571 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
572 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
573
574 /* EVB capabilities */
575 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
576 u8 evb_802_1_qbh; /* Bridge Port Extension */
577
578 u8 dcb;
579 u8 iscsi;
580 u8 ieee_1588;
581 u8 mgmt_cem;
582
583 /* WoL and APM support */
584 #define ICE_WOL_SUPPORT_M BIT(0)
585 #define ICE_ACPI_PROG_MTHD_M BIT(1)
586 #define ICE_PROXY_SUPPORT_M BIT(2)
587 u8 apm_wol_support;
588 u8 acpi_prog_mthd;
589 u8 proxy_support;
590 bool sec_rev_disabled;
591 bool update_disabled;
592 bool nvm_unified_update;
593 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
594 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
595 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
596 /* PCIe reset avoidance */
597 bool pcie_reset_avoidance; /* false: not supported, true: supported */
598 /* Post update reset restriction */
599 bool reset_restrict_support; /* false: not supported, true: supported */
600
601 /* External topology device images within the NVM */
602 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4
603 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
604 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
605 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
606 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8
607 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \
608 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
609 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
610 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
611 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
612 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
613 };
614
615 /* IEEE 1588 TIME_SYNC specific info */
616 /* Function specific definitions */
617 #define ICE_TS_FUNC_ENA_M BIT(0)
618 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
619 #define ICE_TS_TMR_ENA_M BIT(2)
620 #define ICE_TS_TMR_IDX_OWND_S 4
621 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
622 #define ICE_TS_CLK_FREQ_S 16
623 #define ICE_TS_CLK_FREQ_M MAKEMASK(0x7, ICE_TS_CLK_FREQ_S)
624 #define ICE_TS_CLK_SRC_S 20
625 #define ICE_TS_CLK_SRC_M BIT(20)
626 #define ICE_TS_TMR_IDX_ASSOC_S 24
627 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
628
629 /* TIME_REF clock rate specification */
630 enum ice_time_ref_freq {
631 ICE_TIME_REF_FREQ_25_000 = 0,
632 ICE_TIME_REF_FREQ_122_880 = 1,
633 ICE_TIME_REF_FREQ_125_000 = 2,
634 ICE_TIME_REF_FREQ_153_600 = 3,
635 ICE_TIME_REF_FREQ_156_250 = 4,
636 ICE_TIME_REF_FREQ_245_760 = 5,
637
638 NUM_ICE_TIME_REF_FREQ
639 };
640
641 /* Clock source specification */
642 enum ice_clk_src {
643 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
644 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
645
646 NUM_ICE_CLK_SRC
647 };
648
649 struct ice_ts_func_info {
650 /* Function specific info */
651 enum ice_time_ref_freq time_ref;
652 u8 clk_freq;
653 u8 clk_src;
654 u8 tmr_index_assoc;
655 u8 ena;
656 u8 tmr_index_owned;
657 u8 src_tmr_owned;
658 u8 tmr_ena;
659 };
660
661 /* Device specific definitions */
662 #define ICE_TS_TMR0_OWNR_M 0x7
663 #define ICE_TS_TMR0_OWND_M BIT(3)
664 #define ICE_TS_TMR1_OWNR_S 4
665 #define ICE_TS_TMR1_OWNR_M MAKEMASK(0x7, ICE_TS_TMR1_OWNR_S)
666 #define ICE_TS_TMR1_OWND_M BIT(7)
667 #define ICE_TS_DEV_ENA_M BIT(24)
668 #define ICE_TS_TMR0_ENA_M BIT(25)
669 #define ICE_TS_TMR1_ENA_M BIT(26)
670
671 struct ice_ts_dev_info {
672 /* Device specific info */
673 u32 ena_ports;
674 u32 tmr_own_map;
675 u32 tmr0_owner;
676 u32 tmr1_owner;
677 u8 tmr0_owned;
678 u8 tmr1_owned;
679 u8 ena;
680 u8 tmr0_ena;
681 u8 tmr1_ena;
682 };
683
684 /* Function specific capabilities */
685 struct ice_hw_func_caps {
686 struct ice_hw_common_caps common_cap;
687 u32 guar_num_vsi;
688 u32 fd_fltr_guar; /* Number of filters guaranteed */
689 u32 fd_fltr_best_effort; /* Number of best effort filters */
690 struct ice_ts_func_info ts_func_info;
691 };
692
693 /* Device wide capabilities */
694 struct ice_hw_dev_caps {
695 struct ice_hw_common_caps common_cap;
696 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
697 u32 num_flow_director_fltr; /* Number of FD filters available */
698 struct ice_ts_dev_info ts_dev_info;
699 u32 num_funcs;
700 };
701
702 /* Information about MAC such as address, etc... */
703 struct ice_mac_info {
704 u8 lan_addr[ETH_ALEN];
705 u8 perm_addr[ETH_ALEN];
706 u8 port_addr[ETH_ALEN];
707 u8 wol_addr[ETH_ALEN];
708 };
709
710 /* PCI bus types */
711 enum ice_bus_type {
712 ice_bus_unknown = 0,
713 ice_bus_pci_express,
714 ice_bus_embedded, /* Is device Embedded versus card */
715 ice_bus_reserved
716 };
717
718 /* PCI bus speeds */
719 enum ice_pcie_bus_speed {
720 ice_pcie_speed_unknown = 0xff,
721 ice_pcie_speed_2_5GT = 0x14,
722 ice_pcie_speed_5_0GT = 0x15,
723 ice_pcie_speed_8_0GT = 0x16,
724 ice_pcie_speed_16_0GT = 0x17
725 };
726
727 /* PCI bus widths */
728 enum ice_pcie_link_width {
729 ice_pcie_lnk_width_resrv = 0x00,
730 ice_pcie_lnk_x1 = 0x01,
731 ice_pcie_lnk_x2 = 0x02,
732 ice_pcie_lnk_x4 = 0x04,
733 ice_pcie_lnk_x8 = 0x08,
734 ice_pcie_lnk_x12 = 0x0C,
735 ice_pcie_lnk_x16 = 0x10,
736 ice_pcie_lnk_x32 = 0x20,
737 ice_pcie_lnk_width_unknown = 0xff,
738 };
739
740 /* Reset types used to determine which kind of reset was requested. These
741 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
742 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
743 * because its reset source is different than the other types listed.
744 */
745 enum ice_reset_req {
746 ICE_RESET_POR = 0,
747 ICE_RESET_INVAL = 0,
748 ICE_RESET_CORER = 1,
749 ICE_RESET_GLOBR = 2,
750 ICE_RESET_EMPR = 3,
751 ICE_RESET_PFR = 4,
752 };
753
754 /* Bus parameters */
755 struct ice_bus_info {
756 enum ice_pcie_bus_speed speed;
757 enum ice_pcie_link_width width;
758 enum ice_bus_type type;
759 u16 domain_num;
760 u16 device;
761 u8 func;
762 u8 bus_num;
763 };
764
765 /* Flow control (FC) parameters */
766 struct ice_fc_info {
767 enum ice_fc_mode current_mode; /* FC mode in effect */
768 enum ice_fc_mode req_mode; /* FC mode requested by caller */
769 };
770
771 /* Option ROM version information */
772 struct ice_orom_info {
773 u8 major; /* Major version of OROM */
774 u8 patch; /* Patch version of OROM */
775 u16 build; /* Build version of OROM */
776 u32 srev; /* Security revision */
777 };
778
779 /* NVM version information */
780 struct ice_nvm_info {
781 u32 eetrack;
782 u32 srev;
783 u8 major;
784 u8 minor;
785 };
786
787 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
788 * of the flash image.
789 */
790 enum ice_flash_bank {
791 ICE_INVALID_FLASH_BANK,
792 ICE_1ST_FLASH_BANK,
793 ICE_2ND_FLASH_BANK,
794 };
795
796 /* Enumeration of which flash bank is desired to read from, either the active
797 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
798 * code which just wants to read the active or inactive flash bank.
799 */
800 enum ice_bank_select {
801 ICE_ACTIVE_FLASH_BANK,
802 ICE_INACTIVE_FLASH_BANK,
803 };
804
805 /* information for accessing NVM, OROM, and Netlist flash banks */
806 struct ice_bank_info {
807 u32 nvm_ptr; /* Pointer to 1st NVM bank */
808 u32 nvm_size; /* Size of NVM bank */
809 u32 orom_ptr; /* Pointer to 1st OROM bank */
810 u32 orom_size; /* Size of OROM bank */
811 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
812 u32 netlist_size; /* Size of Netlist bank */
813 enum ice_flash_bank nvm_bank; /* Active NVM bank */
814 enum ice_flash_bank orom_bank; /* Active OROM bank */
815 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
816 };
817
818 /* Flash Chip Information */
819 struct ice_flash_info {
820 struct ice_orom_info orom; /* Option ROM version info */
821 struct ice_nvm_info nvm; /* NVM version information */
822 struct ice_bank_info banks; /* Flash Bank information */
823 u16 sr_words; /* Shadow RAM size in words */
824 u32 flash_size; /* Size of available flash in bytes */
825 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
826 };
827
828 struct ice_link_default_override_tlv {
829 u8 options;
830 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
831 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
832 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
833 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
834 #define ICE_LINK_OVERRIDE_EN BIT(3)
835 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
836 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
837 u8 phy_config;
838 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
839 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
840 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
841 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
842 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
843 u8 fec_options;
844 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
845 u8 rsvd1;
846 u64 phy_type_low;
847 u64 phy_type_high;
848 };
849
850 #define ICE_NVM_VER_LEN 32
851
852 /* Max number of port to queue branches w.r.t topology */
853 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
854
855 #define ice_for_each_traffic_class(_i) \
856 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
857
858 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
859 * to driver defined policy for default aggregator
860 */
861 #define ICE_INVAL_TEID 0xFFFFFFFF
862 #define ICE_DFLT_AGG_ID 0
863
864 struct ice_sched_node {
865 struct ice_sched_node *parent;
866 struct ice_sched_node *sibling; /* next sibling in the same layer */
867 struct ice_sched_node **children;
868 struct ice_aqc_txsched_elem_data info;
869 u32 agg_id; /* aggregator group ID */
870 u16 vsi_handle;
871 u8 in_use; /* suspended or in use */
872 u8 tx_sched_layer; /* Logical Layer (1-9) */
873 u8 num_children;
874 u8 tc_num;
875 u8 owner;
876 #define ICE_SCHED_NODE_OWNER_LAN 0
877 #define ICE_SCHED_NODE_OWNER_AE 1
878 #define ICE_SCHED_NODE_OWNER_RDMA 2
879 };
880
881 /* Access Macros for Tx Sched Elements data */
882 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
883 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
884 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
885 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
886 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
887 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
888 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
889 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
890 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
891 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
892 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
893
894 struct ice_sched_rl_profile {
895 u32 rate; /* In Kbps */
896 struct ice_aqc_rl_profile_elem info;
897 };
898
899 /* The aggregator type determines if identifier is for a VSI group,
900 * aggregator group, aggregator of queues, or queue group.
901 */
902 enum ice_agg_type {
903 ICE_AGG_TYPE_UNKNOWN = 0,
904 ICE_AGG_TYPE_TC,
905 ICE_AGG_TYPE_AGG, /* aggregator */
906 ICE_AGG_TYPE_VSI,
907 ICE_AGG_TYPE_QG,
908 ICE_AGG_TYPE_Q
909 };
910
911 /* Rate limit types */
912 enum ice_rl_type {
913 ICE_UNKNOWN_BW = 0,
914 ICE_MIN_BW, /* for CIR profile */
915 ICE_MAX_BW, /* for EIR profile */
916 ICE_SHARED_BW /* for shared profile */
917 };
918
919 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
920 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
921 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
922 #define ICE_SCHED_NO_PRIORITY 0
923 #define ICE_SCHED_NO_BW_WT 0
924 #define ICE_SCHED_DFLT_RL_PROF_ID 0
925 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
926 #define ICE_SCHED_DFLT_BW_WT 4
927 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
928 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
929
930 /* Access Macros for Tx Sched RL Profile data */
931 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
932 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
933 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
934 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
935 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
936
937 /* The following tree example shows the naming conventions followed under
938 * ice_port_info struct for default scheduler tree topology.
939 *
940 * A tree on a port
941 * * ---> root node
942 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
943 * * * * * * * * * |
944 * / |
945 * * |
946 * / |-> num_elements (range:1 - 9)
947 * * | implies num_of_layers
948 * / |
949 * (a)* |
950 *
951 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
952 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
953 * need TEID of (a) to add queues.
954 *
955 * This tree
956 * -> has 8 branches (one for each TC)
957 * -> First branch (TC0) has 4 elements
958 * -> has 4 layers
959 * -> (a) is the topmost layer node created by firmware on branch 0
960 *
961 * Note: Above asterisk tree covers only basic terminology and scenario.
962 * Refer to the documentation for more info.
963 */
964
965 /* Data structure for saving BW information */
966 enum ice_bw_type {
967 ICE_BW_TYPE_PRIO,
968 ICE_BW_TYPE_CIR,
969 ICE_BW_TYPE_CIR_WT,
970 ICE_BW_TYPE_EIR,
971 ICE_BW_TYPE_EIR_WT,
972 ICE_BW_TYPE_SHARED,
973 ICE_BW_TYPE_CNT /* This must be last */
974 };
975
976 struct ice_bw {
977 u32 bw;
978 u16 bw_alloc;
979 };
980
981 struct ice_bw_type_info {
982 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
983 u8 generic;
984 struct ice_bw cir_bw;
985 struct ice_bw eir_bw;
986 u32 shared_bw;
987 };
988
989 /* VSI queue context structure for given TC */
990 struct ice_q_ctx {
991 u16 q_handle;
992 u32 q_teid;
993 /* bw_t_info saves queue BW information */
994 struct ice_bw_type_info bw_t_info;
995 };
996
997 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
998 struct ice_sched_vsi_info {
999 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
1000 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
1001 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
1002 /* bw_t_info saves VSI BW information */
1003 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
1004 };
1005
1006 /* CEE or IEEE 802.1Qaz ETS Configuration data */
1007 struct ice_dcb_ets_cfg {
1008 u8 willing;
1009 u8 cbs;
1010 u8 maxtcs;
1011 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
1012 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
1013 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
1014 };
1015
1016 /* CEE or IEEE 802.1Qaz PFC Configuration data */
1017 struct ice_dcb_pfc_cfg {
1018 u8 willing;
1019 u8 mbc;
1020 u8 pfccap;
1021 u8 pfcena;
1022 };
1023
1024 /* CEE or IEEE 802.1Qaz Application Priority data */
1025 struct ice_dcb_app_priority_table {
1026 u16 prot_id;
1027 u8 priority;
1028 u8 selector;
1029 };
1030
1031 #define ICE_MAX_USER_PRIORITY 8
1032 #define ICE_DCBX_MAX_APPS 64
1033 #define ICE_DSCP_NUM_VAL 64
1034 #define ICE_LLDPDU_SIZE 1500
1035 #define ICE_TLV_STATUS_OPER 0x1
1036 #define ICE_TLV_STATUS_SYNC 0x2
1037 #define ICE_TLV_STATUS_ERR 0x4
1038 #define ICE_APP_PROT_ID_FCOE 0x8906
1039 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
1040 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
1041 #define ICE_APP_PROT_ID_FIP 0x8914
1042 #define ICE_APP_SEL_ETHTYPE 0x1
1043 #define ICE_APP_SEL_TCPIP 0x2
1044 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
1045 #define ICE_CEE_APP_SEL_TCPIP 0x1
1046
1047 struct ice_dcbx_cfg {
1048 u32 numapps;
1049 u32 tlv_status; /* CEE mode TLV status */
1050 struct ice_dcb_ets_cfg etscfg;
1051 struct ice_dcb_ets_cfg etsrec;
1052 struct ice_dcb_pfc_cfg pfc;
1053 #define ICE_QOS_MODE_VLAN 0x0
1054 #define ICE_QOS_MODE_DSCP 0x1
1055 u8 pfc_mode;
1056 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
1057 /* when DSCP mapping defined by user set its bit to 1 */
1058 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
1059 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
1060 u8 dscp_map[ICE_DSCP_NUM_VAL];
1061 u8 dcbx_mode;
1062 #define ICE_DCBX_MODE_CEE 0x1
1063 #define ICE_DCBX_MODE_IEEE 0x2
1064 u8 app_mode;
1065 #define ICE_DCBX_APPS_NON_WILLING 0x1
1066 };
1067
1068 struct ice_qos_cfg {
1069 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
1070 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
1071 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
1072 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
1073 u8 is_sw_lldp : 1;
1074 };
1075
1076 struct ice_port_info {
1077 struct ice_sched_node *root; /* Root Node per Port */
1078 struct ice_hw *hw; /* back pointer to HW instance */
1079 u32 last_node_teid; /* scheduler last node info */
1080 u16 sw_id; /* Initial switch ID belongs to port */
1081 u16 pf_vf_num;
1082 u8 port_state;
1083 #define ICE_SCHED_PORT_STATE_INIT 0x0
1084 #define ICE_SCHED_PORT_STATE_READY 0x1
1085 u8 lport;
1086 #define ICE_LPORT_MASK 0xff
1087 u16 dflt_tx_vsi_rule_id;
1088 u16 dflt_tx_vsi_num;
1089 u16 dflt_rx_vsi_rule_id;
1090 u16 dflt_rx_vsi_num;
1091 struct ice_fc_info fc;
1092 struct ice_mac_info mac;
1093 struct ice_phy_info phy;
1094 struct ice_lock sched_lock; /* protect access to TXSched tree */
1095 struct ice_sched_node *
1096 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
1097 struct ice_bw_type_info root_node_bw_t_info;
1098 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
1099 struct ice_qos_cfg qos_cfg;
1100 u8 is_vf:1;
1101 };
1102
1103 struct ice_switch_info {
1104 struct LIST_HEAD_TYPE vsi_list_map_head;
1105 struct ice_sw_recipe *recp_list;
1106 u16 prof_res_bm_init;
1107 u16 max_used_prof_index;
1108
1109 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
1110 };
1111
1112 /* Port hardware description */
1113 struct ice_hw {
1114 u8 *hw_addr;
1115 void *back;
1116 struct ice_aqc_layer_props *layer_info;
1117 struct ice_port_info *port_info;
1118 /* 2D Array for each Tx Sched RL Profile type */
1119 struct ice_sched_rl_profile **cir_profiles;
1120 struct ice_sched_rl_profile **eir_profiles;
1121 struct ice_sched_rl_profile **srl_profiles;
1122 /* PSM clock frequency for calculating RL profile params */
1123 u32 psm_clk_freq;
1124 u64 debug_mask; /* BITMAP for debug mask */
1125 enum ice_mac_type mac_type;
1126
1127 u16 fd_ctr_base; /* FD counter base index */
1128 /* pci info */
1129 u16 device_id;
1130 u16 vendor_id;
1131 u16 subsystem_device_id;
1132 u16 subsystem_vendor_id;
1133 u8 revision_id;
1134
1135 u8 pf_id; /* device profile info */
1136 u8 logical_pf_id;
1137
1138 u16 max_burst_size; /* driver sets this value */
1139
1140 /* Tx Scheduler values */
1141 u8 num_tx_sched_layers;
1142 u8 num_tx_sched_phys_layers;
1143 u8 flattened_layers;
1144 u8 max_cgds;
1145 u8 sw_entry_point_layer;
1146 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1147 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
1148 /* List contain profile ID(s) and other params per layer */
1149 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1150 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
1151 u8 evb_veb; /* true for VEB, false for VEPA */
1152 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
1153 struct ice_bus_info bus;
1154 struct ice_flash_info flash;
1155 struct ice_hw_dev_caps dev_caps; /* device capabilities */
1156 struct ice_hw_func_caps func_caps; /* function capabilities */
1157
1158 struct ice_switch_info *switch_info; /* switch filter lists */
1159
1160 /* Control Queue info */
1161 struct ice_ctl_q_info adminq;
1162 struct ice_ctl_q_info sbq;
1163 struct ice_ctl_q_info mailboxq;
1164 /* Additional function to send AdminQ command */
1165 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
1166 void *buf, u16 buf_size);
1167 void *aq_send_cmd_param;
1168 u8 dcf_enabled; /* Device Config Function */
1169
1170 u8 api_branch; /* API branch version */
1171 u8 api_maj_ver; /* API major version */
1172 u8 api_min_ver; /* API minor version */
1173 u8 api_patch; /* API patch version */
1174 u8 fw_branch; /* firmware branch version */
1175 u8 fw_maj_ver; /* firmware major version */
1176 u8 fw_min_ver; /* firmware minor version */
1177 u8 fw_patch; /* firmware patch version */
1178 u32 fw_build; /* firmware build number */
1179
1180 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
1181 * register. Used for determining the ITR/INTRL granularity during
1182 * initialization.
1183 */
1184 #define ICE_MAX_AGG_BW_200G 0x0
1185 #define ICE_MAX_AGG_BW_100G 0X1
1186 #define ICE_MAX_AGG_BW_50G 0x2
1187 #define ICE_MAX_AGG_BW_25G 0x3
1188 /* ITR granularity for different speeds */
1189 #define ICE_ITR_GRAN_ABOVE_25 2
1190 #define ICE_ITR_GRAN_MAX_25 4
1191 /* ITR granularity in 1 us */
1192 u8 itr_gran;
1193 /* INTRL granularity for different speeds */
1194 #define ICE_INTRL_GRAN_ABOVE_25 4
1195 #define ICE_INTRL_GRAN_MAX_25 8
1196 /* INTRL granularity in 1 us */
1197 u8 intrl_gran;
1198
1199 /* true if VSIs can share unicast MAC addr */
1200 u8 umac_shared;
1201
1202 #define ICE_PHY_PER_NAC 1
1203 #define ICE_MAX_QUAD 2
1204 #define ICE_NUM_QUAD_TYPE 2
1205 #define ICE_PORTS_PER_QUAD 4
1206 #define ICE_PHY_0_LAST_QUAD 1
1207 #define ICE_PORTS_PER_PHY 8
1208 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
1209
1210 /* Active package version (currently active) */
1211 struct ice_pkg_ver active_pkg_ver;
1212 u32 pkg_seg_id;
1213 u32 active_track_id;
1214 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
1215 u8 active_pkg_in_nvm;
1216
1217 enum ice_aq_err pkg_dwnld_status;
1218
1219 /* Driver's package ver - (from the Ice Metadata section) */
1220 struct ice_pkg_ver pkg_ver;
1221 u8 pkg_name[ICE_PKG_NAME_SIZE];
1222
1223 /* Driver's Ice segment format version and id (from the Ice seg) */
1224 struct ice_pkg_ver ice_seg_fmt_ver;
1225 u8 ice_seg_id[ICE_SEG_ID_SIZE];
1226
1227 /* Pointer to the ice segment */
1228 struct ice_seg *seg;
1229
1230 /* Pointer to allocated copy of pkg memory */
1231 u8 *pkg_copy;
1232 u32 pkg_size;
1233
1234 /* tunneling info */
1235 struct ice_lock tnl_lock;
1236 struct ice_tunnel_table tnl;
1237 /* dvm boost update information */
1238 struct ice_dvm_table dvm_upd;
1239
1240 struct ice_acl_tbl *acl_tbl;
1241 struct ice_fd_hw_prof **acl_prof;
1242 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1243 /* HW block tables */
1244 struct ice_blk_info blk[ICE_BLK_COUNT];
1245 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1246 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
1247 /* Flow Director filter info */
1248 int fdir_active_fltr;
1249
1250 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
1251 struct LIST_HEAD_TYPE fdir_list_head;
1252
1253 /* Book-keeping of side-band filter count per flow-type.
1254 * This is used to detect and handle input set changes for
1255 * respective flow-type.
1256 */
1257 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1258
1259 struct ice_fd_hw_prof **fdir_prof;
1260 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1261 struct ice_lock rss_locks; /* protect RSS configuration */
1262 struct LIST_HEAD_TYPE rss_list_head;
1263 ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
1264 u8 dvm_ena;
1265 __le16 io_expander_handle;
1266 };
1267
1268 /* Statistics collected by each port, VSI, VEB, and S-channel */
1269 struct ice_eth_stats {
1270 u64 rx_bytes; /* gorc */
1271 u64 rx_unicast; /* uprc */
1272 u64 rx_multicast; /* mprc */
1273 u64 rx_broadcast; /* bprc */
1274 u64 rx_discards; /* rdpc */
1275 u64 rx_unknown_protocol; /* rupp */
1276 u64 tx_bytes; /* gotc */
1277 u64 tx_unicast; /* uptc */
1278 u64 tx_multicast; /* mptc */
1279 u64 tx_broadcast; /* bptc */
1280 u64 tx_discards; /* tdpc */
1281 u64 tx_errors; /* tepc */
1282 u64 rx_no_desc; /* repc */
1283 u64 rx_errors; /* repc */
1284 };
1285
1286 #define ICE_MAX_UP 8
1287
1288 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1289 struct ice_veb_up_stats {
1290 u64 up_rx_pkts[ICE_MAX_UP];
1291 u64 up_rx_bytes[ICE_MAX_UP];
1292 u64 up_tx_pkts[ICE_MAX_UP];
1293 u64 up_tx_bytes[ICE_MAX_UP];
1294 };
1295
1296 /* Statistics collected by the MAC */
1297 struct ice_hw_port_stats {
1298 /* eth stats collected by the port */
1299 struct ice_eth_stats eth;
1300 /* additional port specific stats */
1301 u64 tx_dropped_link_down; /* tdold */
1302 u64 crc_errors; /* crcerrs */
1303 u64 illegal_bytes; /* illerrc */
1304 u64 error_bytes; /* errbc */
1305 u64 mac_local_faults; /* mlfc */
1306 u64 mac_remote_faults; /* mrfc */
1307 u64 rx_len_errors; /* rlec */
1308 u64 link_xon_rx; /* lxonrxc */
1309 u64 link_xoff_rx; /* lxoffrxc */
1310 u64 link_xon_tx; /* lxontxc */
1311 u64 link_xoff_tx; /* lxofftxc */
1312 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1313 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1314 u64 priority_xon_tx[8]; /* pxontxc[8] */
1315 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1316 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1317 u64 rx_size_64; /* prc64 */
1318 u64 rx_size_127; /* prc127 */
1319 u64 rx_size_255; /* prc255 */
1320 u64 rx_size_511; /* prc511 */
1321 u64 rx_size_1023; /* prc1023 */
1322 u64 rx_size_1522; /* prc1522 */
1323 u64 rx_size_big; /* prc9522 */
1324 u64 rx_undersize; /* ruc */
1325 u64 rx_fragments; /* rfc */
1326 u64 rx_oversize; /* roc */
1327 u64 rx_jabber; /* rjc */
1328 u64 tx_size_64; /* ptc64 */
1329 u64 tx_size_127; /* ptc127 */
1330 u64 tx_size_255; /* ptc255 */
1331 u64 tx_size_511; /* ptc511 */
1332 u64 tx_size_1023; /* ptc1023 */
1333 u64 tx_size_1522; /* ptc1522 */
1334 u64 tx_size_big; /* ptc9522 */
1335 u64 mac_short_pkt_dropped; /* mspdc */
1336 /* flow director stats */
1337 u32 fd_sb_status;
1338 u64 fd_sb_match;
1339 };
1340
1341 enum ice_sw_fwd_act_type {
1342 ICE_FWD_TO_VSI = 0,
1343 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1344 ICE_FWD_TO_Q,
1345 ICE_FWD_TO_QGRP,
1346 ICE_DROP_PACKET,
1347 ICE_INVAL_ACT
1348 };
1349
1350 struct ice_aq_get_set_rss_lut_params {
1351 u16 vsi_handle; /* software VSI handle */
1352 u16 lut_size; /* size of the LUT buffer */
1353 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1354 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1355 u8 global_lut_id; /* only valid when lut_type is global */
1356 };
1357
1358 /* Checksum and Shadow RAM pointers */
1359 #define ICE_SR_NVM_CTRL_WORD 0x00
1360 #define ICE_SR_PHY_ANALOG_PTR 0x04
1361 #define ICE_SR_OPTION_ROM_PTR 0x05
1362 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1363 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1364 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1365 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1366 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1367 #define ICE_SR_PE_IMAGE_PTR 0x0C
1368 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1369 #define ICE_SR_MNG_CFG_PTR 0x0E
1370 #define ICE_SR_EMP_MODULE_PTR 0x0F
1371 #define ICE_SR_PBA_BLOCK_PTR 0x16
1372 #define ICE_SR_BOOT_CFG_PTR 0x132
1373 #define ICE_SR_NVM_WOL_CFG 0x19
1374 #define ICE_NVM_OROM_VER_OFF 0x02
1375 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1376 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1377 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1378 #define ICE_SR_NVM_MAP_VER 0x29
1379 #define ICE_SR_NVM_IMAGE_VER 0x2A
1380 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1381 #define ICE_SR_NVM_EETRACK_LO 0x2D
1382 #define ICE_SR_NVM_EETRACK_HI 0x2E
1383 #define ICE_NVM_VER_LO_SHIFT 0
1384 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1385 #define ICE_NVM_VER_HI_SHIFT 12
1386 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1387 #define ICE_OEM_EETRACK_ID 0xffffffff
1388 #define ICE_OROM_VER_PATCH_SHIFT 0
1389 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1390 #define ICE_OROM_VER_BUILD_SHIFT 8
1391 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1392 #define ICE_OROM_VER_SHIFT 24
1393 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1394 #define ICE_SR_VPD_PTR 0x2F
1395 #define ICE_SR_PXE_SETUP_PTR 0x30
1396 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1397 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1398 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1399 #define ICE_SR_VLAN_CFG_PTR 0x37
1400 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1401 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1402 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1403 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1404 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1405 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1406 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1407 #define ICE_SR_PFA_PTR 0x40
1408 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1409 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1410 #define ICE_SR_NVM_BANK_SIZE 0x43
1411 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1412 #define ICE_SR_OROM_BANK_SIZE 0x45
1413 #define ICE_SR_NETLIST_BANK_PTR 0x46
1414 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1415 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1416 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1417 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1418 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1419 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1420
1421 /* CSS Header words */
1422 #define ICE_NVM_CSS_SREV_L 0x14
1423 #define ICE_NVM_CSS_SREV_H 0x15
1424
1425 /* Length of CSS header section in words */
1426 #define ICE_CSS_HEADER_LENGTH 330
1427
1428 /* Offset of Shadow RAM copy in the NVM bank area. */
1429 #define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32)
1430
1431 /* Size in bytes of Option ROM trailer */
1432 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1433
1434 /* The Link Topology Netlist section is stored as a series of words. It is
1435 * stored in the NVM as a TLV, with the first two words containing the type
1436 * and length.
1437 */
1438 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1439 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1440 #define ICE_NETLIST_LEN_OFFSET 0x0001
1441
1442 /* The Link Topology section follows the TLV header. When reading the netlist
1443 * using ice_read_netlist_module, we need to account for the 2-word TLV
1444 * header.
1445 */
1446 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1447
1448 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1449 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1450
1451 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1452
1453 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1454 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1455 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1456
1457 /* netlist ID block field offsets (word offsets) */
1458 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1459 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1460 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1461 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1462 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1463 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1464 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1465 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1466 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1467 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1468
1469 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1470 #define ICE_SR_VPD_SIZE_WORDS 512
1471 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1472 #define ICE_SR_CTRL_WORD_1_S 0x06
1473 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1474 #define ICE_SR_CTRL_WORD_VALID 0x1
1475 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1476 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1477 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1478
1479 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1480
1481 /* Shadow RAM related */
1482 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1483 #define ICE_SR_BUF_ALIGNMENT 4096
1484 #define ICE_SR_WORDS_IN_1KB 512
1485 /* Checksum should be calculated such that after adding all the words,
1486 * including the checksum word itself, the sum should be 0xBABA.
1487 */
1488 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1489
1490 /* Link override related */
1491 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1492 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1493 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1494 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1495 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1496 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1497 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1498 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1499
1500 #define ICE_PBA_FLAG_DFLT 0xFAFA
1501 /* Hash redirection LUT for VSI - maximum array size */
1502 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1503
1504 /*
1505 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1506 * This is needed to determine the BAR0 space for the VFs
1507 */
1508 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1509 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1510 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1511
1512 /* AQ API version for LLDP_FILTER_CONTROL */
1513 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1514 #define ICE_FW_API_LLDP_FLTR_MIN 7
1515 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1516
1517 /* AQ API version for report default configuration */
1518 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1519 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1520 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1521 #endif /* _ICE_TYPE_H_ */
1522