1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
3 */
4
5 #include <string.h>
6 #include <dirent.h>
7 #include <sys/stat.h>
8 #include <unistd.h>
9 #include <sys/types.h>
10 #include <fcntl.h>
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
13 #include <rte_log.h>
14 #include <rte_bus.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
18 #include <rte_pci.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
27 #include <rte_eal.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
32
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
43
44 #define PCI_VENDOR_ID_INTEL 0x8086
45 /* PCI Device ID */
46 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
47 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
48 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
49 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
50 /* VF Device */
51 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
52 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
53 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
54 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
55 #define RTE_MAX_RAW_DEVICE 10
56
57 static const struct rte_pci_id pci_ifpga_map[] = {
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
66 { .vendor_id = 0, /* sentinel */ },
67 };
68
69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
70
71 static int ifpga_monitor_refcnt;
72 static pthread_t ifpga_monitor_start_thread;
73
74 static struct ifpga_rawdev *
75 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
76 static int set_surprise_link_check_aer(
77 struct ifpga_rawdev *ifpga_rdev, int force_disable);
78 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
79 int start, uint32_t cap);
80 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
81
82 struct ifpga_rawdev *
ifpga_rawdev_get(const struct rte_rawdev * rawdev)83 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
84 {
85 struct ifpga_rawdev *dev;
86 unsigned int i;
87
88 if (rawdev == NULL)
89 return NULL;
90
91 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
92 dev = &ifpga_rawdevices[i];
93 if (dev->rawdev == rawdev)
94 return dev;
95 }
96
97 return NULL;
98 }
99
100 static inline uint8_t
ifpga_rawdev_find_free_device_index(void)101 ifpga_rawdev_find_free_device_index(void)
102 {
103 uint16_t dev_id;
104
105 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
106 if (ifpga_rawdevices[dev_id].rawdev == NULL)
107 return dev_id;
108 }
109
110 return IFPGA_RAWDEV_NUM;
111 }
112 static struct ifpga_rawdev *
ifpga_rawdev_allocate(struct rte_rawdev * rawdev)113 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
114 {
115 struct ifpga_rawdev *dev;
116 uint16_t dev_id;
117 int i = 0;
118
119 dev = ifpga_rawdev_get(rawdev);
120 if (dev != NULL) {
121 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
122 return NULL;
123 }
124
125 dev_id = ifpga_rawdev_find_free_device_index();
126 if (dev_id == IFPGA_RAWDEV_NUM) {
127 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
128 return NULL;
129 }
130
131 dev = &ifpga_rawdevices[dev_id];
132 dev->rawdev = rawdev;
133 dev->dev_id = dev_id;
134 for (i = 0; i < IFPGA_MAX_IRQ; i++)
135 dev->intr_handle[i] = NULL;
136 dev->poll_enabled = 0;
137
138 return dev;
139 }
140
141 static int
ifpga_pci_find_next_ext_capability(unsigned int fd,int start,uint32_t cap)142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
143 {
144 uint32_t header;
145 int ttl;
146 int pos = RTE_PCI_CFG_SPACE_SIZE;
147 int ret;
148
149 /* minimum 8 bytes per capability */
150 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
151
152 if (start)
153 pos = start;
154 ret = pread(fd, &header, sizeof(header), pos);
155 if (ret == -1)
156 return -1;
157
158 /*
159 * If we have no capabilities, this is indicated by cap ID,
160 * cap version and next pointer all being 0.
161 */
162 if (header == 0)
163 return 0;
164
165 while (ttl-- > 0) {
166 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
167 return pos;
168
169 pos = RTE_PCI_EXT_CAP_NEXT(header);
170 if (pos < RTE_PCI_CFG_SPACE_SIZE)
171 break;
172 ret = pread(fd, &header, sizeof(header), pos);
173 if (ret == -1)
174 return -1;
175 }
176
177 return 0;
178 }
179
180 static int
ifpga_pci_find_ext_capability(unsigned int fd,uint32_t cap)181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
182 {
183 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
184 }
185
ifpga_get_dev_vendor_id(const char * bdf,uint32_t * dev_id,uint32_t * vendor_id)186 static int ifpga_get_dev_vendor_id(const char *bdf,
187 uint32_t *dev_id, uint32_t *vendor_id)
188 {
189 int fd;
190 char path[1024];
191 int ret;
192 uint32_t header;
193
194 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
195 strlcat(path, bdf, sizeof(path));
196 strlcat(path, "/config", sizeof(path));
197 fd = open(path, O_RDWR);
198 if (fd < 0)
199 return -1;
200 ret = pread(fd, &header, sizeof(header), 0);
201 if (ret == -1) {
202 close(fd);
203 return -1;
204 }
205 (*vendor_id) = header & 0xffff;
206 (*dev_id) = (header >> 16) & 0xffff;
207 close(fd);
208
209 return 0;
210 }
211
ifpga_rawdev_fill_info(struct ifpga_rawdev * ifpga_dev)212 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev)
213 {
214 struct opae_adapter *adapter = NULL;
215 char path[1024] = "/sys/bus/pci/devices/";
216 char link[1024], link1[1024];
217 char dir[1024] = "/sys/devices/";
218 char *c;
219 int ret;
220 char sub_brg_bdf[4][16] = {{0}};
221 int point;
222 DIR *dp = NULL;
223 struct dirent *entry;
224 int i, j;
225
226 unsigned int dom, bus, dev;
227 int func;
228 uint32_t dev_id = 0;
229 uint32_t vendor_id = 0;
230
231 adapter = ifpga_dev ? ifpga_rawdev_get_priv(ifpga_dev->rawdev) : NULL;
232 if (!adapter)
233 return -ENODEV;
234
235 strlcat(path, adapter->name, sizeof(path));
236 memset(link, 0, sizeof(link));
237 memset(link1, 0, sizeof(link1));
238 ret = readlink(path, link, (sizeof(link)-1));
239 if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
240 return -1;
241 link[ret] = 0; /* terminate string with null character */
242 strlcpy(link1, link, sizeof(link1));
243 memset(ifpga_dev->parent_bdf, 0, 16);
244 point = strlen(link);
245 if (point < 39)
246 return -1;
247 point -= 39;
248 link[point] = 0;
249 if (point < 12)
250 return -1;
251 point -= 12;
252 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
253
254 point = strlen(link1);
255 if (point < 26)
256 return -1;
257 point -= 26;
258 link1[point] = 0;
259 if (point < 12)
260 return -1;
261 point -= 12;
262 c = strchr(link1, 'p');
263 if (!c)
264 return -1;
265 strlcat(dir, c, sizeof(dir));
266
267 /* scan folder */
268 dp = opendir(dir);
269 if (dp == NULL)
270 return -1;
271 i = 0;
272 while ((entry = readdir(dp)) != NULL) {
273 if (i >= 4)
274 break;
275 if (entry->d_name[0] == '.')
276 continue;
277 if (strlen(entry->d_name) > 12)
278 continue;
279 if (sscanf(entry->d_name, "%x:%x:%x.%d",
280 &dom, &bus, &dev, &func) < 4)
281 continue;
282 else {
283 strlcpy(sub_brg_bdf[i],
284 entry->d_name,
285 sizeof(sub_brg_bdf[i]));
286 i++;
287 }
288 }
289 closedir(dp);
290
291 /* get fpga and fvl */
292 j = 0;
293 for (i = 0; i < 4; i++) {
294 strlcpy(link, dir, sizeof(link));
295 strlcat(link, "/", sizeof(link));
296 strlcat(link, sub_brg_bdf[i], sizeof(link));
297 dp = opendir(link);
298 if (dp == NULL)
299 return -1;
300 while ((entry = readdir(dp)) != NULL) {
301 if (j >= 8)
302 break;
303 if (entry->d_name[0] == '.')
304 continue;
305
306 if (strlen(entry->d_name) > 12)
307 continue;
308 if (sscanf(entry->d_name, "%x:%x:%x.%d",
309 &dom, &bus, &dev, &func) < 4)
310 continue;
311 else {
312 if (ifpga_get_dev_vendor_id(entry->d_name,
313 &dev_id, &vendor_id))
314 continue;
315 if (vendor_id == 0x8086 &&
316 (dev_id == 0x0CF8 ||
317 dev_id == 0x0D58 ||
318 dev_id == 0x1580)) {
319 strlcpy(ifpga_dev->fvl_bdf[j],
320 entry->d_name,
321 sizeof(ifpga_dev->fvl_bdf[j]));
322 j++;
323 }
324 }
325 }
326 closedir(dp);
327 }
328
329 return 0;
330 }
331
332 #define HIGH_FATAL(_sens, value)\
333 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
334 (value > (_sens)->high_fatal))
335
336 #define HIGH_WARN(_sens, value)\
337 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
338 (value > (_sens)->high_warn))
339
340 #define LOW_FATAL(_sens, value)\
341 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
342 (value > (_sens)->low_fatal))
343
344 #define LOW_WARN(_sens, value)\
345 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
346 (value > (_sens)->low_warn))
347
348 #define AUX_VOLTAGE_WARN 11400
349
350 static int
ifpga_monitor_sensor(struct rte_rawdev * raw_dev,bool * gsd_start)351 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
352 bool *gsd_start)
353 {
354 struct opae_adapter *adapter;
355 struct opae_manager *mgr;
356 struct opae_sensor_info *sensor;
357 unsigned int value;
358 int ret;
359
360 adapter = ifpga_rawdev_get_priv(raw_dev);
361 if (!adapter)
362 return -ENODEV;
363
364 mgr = opae_adapter_get_mgr(adapter);
365 if (!mgr)
366 return -ENODEV;
367
368 opae_mgr_for_each_sensor(mgr, sensor) {
369 if (!(sensor->flags & OPAE_SENSOR_VALID))
370 goto fail;
371
372 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
373 if (ret)
374 goto fail;
375
376 if (value == 0xdeadbeef) {
377 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
378 raw_dev->dev_id, sensor->name, value);
379 continue;
380 }
381
382 /* monitor temperature sensors */
383 if (!strcmp(sensor->name, "Board Temperature") ||
384 !strcmp(sensor->name, "FPGA Die Temperature")) {
385 IFPGA_RAWDEV_PMD_DEBUG("read sensor %s %d %d %d\n",
386 sensor->name, value, sensor->high_warn,
387 sensor->high_fatal);
388
389 if (HIGH_WARN(sensor, value) ||
390 LOW_WARN(sensor, value)) {
391 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
392 sensor->name, value);
393 *gsd_start = true;
394 break;
395 }
396 }
397
398 /* monitor 12V AUX sensor */
399 if (!strcmp(sensor->name, "12V AUX Voltage")) {
400 if (value < AUX_VOLTAGE_WARN) {
401 IFPGA_RAWDEV_PMD_INFO(
402 "%s reach threshold %d mV\n",
403 sensor->name, value);
404 *gsd_start = true;
405 break;
406 }
407 }
408 }
409
410 return 0;
411 fail:
412 return -EFAULT;
413 }
414
set_surprise_link_check_aer(struct ifpga_rawdev * ifpga_rdev,int force_disable)415 static int set_surprise_link_check_aer(
416 struct ifpga_rawdev *ifpga_rdev, int force_disable)
417 {
418 struct rte_rawdev *rdev;
419 int fd = -1;
420 char path[1024];
421 int pos;
422 int ret;
423 uint32_t data;
424 bool enable = 0;
425 uint32_t aer_new0, aer_new1;
426
427 if (!ifpga_rdev || !ifpga_rdev->rawdev) {
428 printf("\n device does not exist\n");
429 return -EFAULT;
430 }
431
432 rdev = ifpga_rdev->rawdev;
433 if (ifpga_rdev->aer_enable)
434 return -EFAULT;
435 if (ifpga_monitor_sensor(rdev, &enable))
436 return -EFAULT;
437 if (enable || force_disable) {
438 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
439 ifpga_rdev->aer_enable = 1;
440 /* get bridge fd */
441 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
442 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
443 strlcat(path, "/config", sizeof(path));
444 fd = open(path, O_RDWR);
445 if (fd < 0)
446 goto end;
447 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
448 if (!pos)
449 goto end;
450 /* save previous ECAP_AER+0x08 */
451 ret = pread(fd, &data, sizeof(data), pos+0x08);
452 if (ret == -1)
453 goto end;
454 ifpga_rdev->aer_old[0] = data;
455 /* save previous ECAP_AER+0x14 */
456 ret = pread(fd, &data, sizeof(data), pos+0x14);
457 if (ret == -1)
458 goto end;
459 ifpga_rdev->aer_old[1] = data;
460
461 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
462 data = 0xffffffff;
463 ret = pwrite(fd, &data, 4, pos+0x08);
464 if (ret == -1)
465 goto end;
466 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
467 ret = pwrite(fd, &data, 4, pos+0x14);
468 if (ret == -1)
469 goto end;
470
471 /* read current ECAP_AER+0x08 */
472 ret = pread(fd, &data, sizeof(data), pos+0x08);
473 if (ret == -1)
474 goto end;
475 aer_new0 = data;
476 /* read current ECAP_AER+0x14 */
477 ret = pread(fd, &data, sizeof(data), pos+0x14);
478 if (ret == -1)
479 goto end;
480 aer_new1 = data;
481
482 if (fd != -1)
483 close(fd);
484
485 printf(">>>>>>Set AER %x,%x %x,%x\n",
486 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
487 aer_new0, aer_new1);
488
489 return 1;
490 }
491
492 end:
493 if (fd != -1)
494 close(fd);
495 return -EFAULT;
496 }
497
498 static void *
ifpga_rawdev_gsd_handle(__rte_unused void * param)499 ifpga_rawdev_gsd_handle(__rte_unused void *param)
500 {
501 struct ifpga_rawdev *ifpga_rdev;
502 int i;
503 int gsd_enable, ret;
504 #define MS 1000
505
506 while (__atomic_load_n(&ifpga_monitor_refcnt, __ATOMIC_RELAXED)) {
507 gsd_enable = 0;
508 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
509 ifpga_rdev = &ifpga_rawdevices[i];
510 if (ifpga_rdev->poll_enabled) {
511 ret = set_surprise_link_check_aer(ifpga_rdev,
512 gsd_enable);
513 if (ret == 1 && !gsd_enable) {
514 gsd_enable = 1;
515 i = -1;
516 }
517 }
518 }
519
520 if (gsd_enable)
521 printf(">>>>>>Pls Shutdown APP\n");
522
523 rte_delay_us(100 * MS);
524 }
525
526 return NULL;
527 }
528
529 static int
ifpga_monitor_start_func(struct ifpga_rawdev * dev)530 ifpga_monitor_start_func(struct ifpga_rawdev *dev)
531 {
532 int ret;
533
534 if (!dev)
535 return -ENODEV;
536
537 ret = ifpga_rawdev_fill_info(dev);
538 if (ret)
539 return ret;
540
541 dev->poll_enabled = 1;
542
543 if (!__atomic_fetch_add(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED)) {
544 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
545 "ifpga-monitor", NULL,
546 ifpga_rawdev_gsd_handle, NULL);
547 if (ret != 0) {
548 ifpga_monitor_start_thread = 0;
549 IFPGA_RAWDEV_PMD_ERR(
550 "Fail to create ifpga monitor thread");
551 return -1;
552 }
553 }
554
555 return 0;
556 }
557
558 static int
ifpga_monitor_stop_func(struct ifpga_rawdev * dev)559 ifpga_monitor_stop_func(struct ifpga_rawdev *dev)
560 {
561 int ret;
562
563 if (!dev || !dev->poll_enabled)
564 return 0;
565
566 dev->poll_enabled = 0;
567
568 if (!__atomic_sub_fetch(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED) &&
569 ifpga_monitor_start_thread) {
570 ret = pthread_cancel(ifpga_monitor_start_thread);
571 if (ret)
572 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
573
574 ret = pthread_join(ifpga_monitor_start_thread, NULL);
575 if (ret)
576 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
577
578 return ret;
579 }
580
581 return 0;
582 }
583
584 static int
ifpga_fill_afu_dev(struct opae_accelerator * acc,struct rte_afu_device * afu_dev)585 ifpga_fill_afu_dev(struct opae_accelerator *acc,
586 struct rte_afu_device *afu_dev)
587 {
588 struct rte_mem_resource *res = afu_dev->mem_resource;
589 struct opae_acc_region_info region_info;
590 struct opae_acc_info info;
591 unsigned long i;
592 int ret;
593
594 ret = opae_acc_get_info(acc, &info);
595 if (ret)
596 return ret;
597
598 if (info.num_regions > PCI_MAX_RESOURCE)
599 return -EFAULT;
600
601 afu_dev->num_region = info.num_regions;
602
603 for (i = 0; i < info.num_regions; i++) {
604 region_info.index = i;
605 ret = opae_acc_get_region_info(acc, ®ion_info);
606 if (ret)
607 return ret;
608
609 if ((region_info.flags & ACC_REGION_MMIO) &&
610 (region_info.flags & ACC_REGION_READ) &&
611 (region_info.flags & ACC_REGION_WRITE)) {
612 res[i].phys_addr = region_info.phys_addr;
613 res[i].len = region_info.len;
614 res[i].addr = region_info.addr;
615 } else
616 return -EFAULT;
617 }
618
619 return 0;
620 }
621
622 static int
ifpga_rawdev_info_get(struct rte_rawdev * dev,rte_rawdev_obj_t dev_info,size_t dev_info_size)623 ifpga_rawdev_info_get(struct rte_rawdev *dev,
624 rte_rawdev_obj_t dev_info,
625 size_t dev_info_size)
626 {
627 struct opae_adapter *adapter;
628 struct opae_accelerator *acc;
629 struct rte_afu_device *afu_dev;
630 struct opae_manager *mgr = NULL;
631 struct opae_eth_group_region_info opae_lside_eth_info;
632 struct opae_eth_group_region_info opae_nside_eth_info;
633 int lside_bar_idx, nside_bar_idx;
634
635 IFPGA_RAWDEV_PMD_FUNC_TRACE();
636
637 if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
638 IFPGA_RAWDEV_PMD_ERR("Invalid request");
639 return -EINVAL;
640 }
641
642 adapter = ifpga_rawdev_get_priv(dev);
643 if (!adapter)
644 return -ENOENT;
645
646 afu_dev = dev_info;
647 afu_dev->rawdev = dev;
648
649 /* find opae_accelerator and fill info into afu_device */
650 opae_adapter_for_each_acc(adapter, acc) {
651 if (acc->index != afu_dev->id.port)
652 continue;
653
654 if (ifpga_fill_afu_dev(acc, afu_dev)) {
655 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
656 return -ENOENT;
657 }
658 }
659
660 /* get opae_manager to rawdev */
661 mgr = opae_adapter_get_mgr(adapter);
662 if (mgr) {
663 /* get LineSide BAR Index */
664 if (opae_manager_get_eth_group_region_info(mgr, 0,
665 &opae_lside_eth_info)) {
666 return -ENOENT;
667 }
668 lside_bar_idx = opae_lside_eth_info.mem_idx;
669
670 /* get NICSide BAR Index */
671 if (opae_manager_get_eth_group_region_info(mgr, 1,
672 &opae_nside_eth_info)) {
673 return -ENOENT;
674 }
675 nside_bar_idx = opae_nside_eth_info.mem_idx;
676
677 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
678 nside_bar_idx >= PCI_MAX_RESOURCE ||
679 lside_bar_idx == nside_bar_idx)
680 return -ENOENT;
681
682 /* fill LineSide BAR Index */
683 afu_dev->mem_resource[lside_bar_idx].phys_addr =
684 opae_lside_eth_info.phys_addr;
685 afu_dev->mem_resource[lside_bar_idx].len =
686 opae_lside_eth_info.len;
687 afu_dev->mem_resource[lside_bar_idx].addr =
688 opae_lside_eth_info.addr;
689
690 /* fill NICSide BAR Index */
691 afu_dev->mem_resource[nside_bar_idx].phys_addr =
692 opae_nside_eth_info.phys_addr;
693 afu_dev->mem_resource[nside_bar_idx].len =
694 opae_nside_eth_info.len;
695 afu_dev->mem_resource[nside_bar_idx].addr =
696 opae_nside_eth_info.addr;
697 }
698 return 0;
699 }
700
701 static int
ifpga_rawdev_configure(const struct rte_rawdev * dev,rte_rawdev_obj_t config,size_t config_size __rte_unused)702 ifpga_rawdev_configure(const struct rte_rawdev *dev,
703 rte_rawdev_obj_t config,
704 size_t config_size __rte_unused)
705 {
706 IFPGA_RAWDEV_PMD_FUNC_TRACE();
707
708 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
709
710 return config ? 0 : 1;
711 }
712
713 static int
ifpga_rawdev_start(struct rte_rawdev * dev)714 ifpga_rawdev_start(struct rte_rawdev *dev)
715 {
716 int ret = 0;
717 struct opae_adapter *adapter;
718
719 IFPGA_RAWDEV_PMD_FUNC_TRACE();
720
721 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
722
723 adapter = ifpga_rawdev_get_priv(dev);
724 if (!adapter)
725 return -ENODEV;
726
727 return ret;
728 }
729
730 static void
ifpga_rawdev_stop(struct rte_rawdev * dev)731 ifpga_rawdev_stop(struct rte_rawdev *dev)
732 {
733 dev->started = 0;
734 }
735
736 static int
ifpga_rawdev_close(struct rte_rawdev * dev)737 ifpga_rawdev_close(struct rte_rawdev *dev)
738 {
739 struct opae_adapter *adapter;
740
741 if (dev) {
742 ifpga_monitor_stop_func(ifpga_rawdev_get(dev));
743 adapter = ifpga_rawdev_get_priv(dev);
744 if (adapter) {
745 opae_adapter_destroy(adapter);
746 opae_adapter_data_free(adapter->data);
747 }
748 }
749
750 return dev ? 0:1;
751 }
752
753 static int
ifpga_rawdev_reset(struct rte_rawdev * dev)754 ifpga_rawdev_reset(struct rte_rawdev *dev)
755 {
756 return dev ? 0:1;
757 }
758
759 static int
fpga_pr(struct rte_rawdev * raw_dev,u32 port_id,const char * buffer,u32 size,u64 * status)760 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
761 u64 *status)
762 {
763
764 struct opae_adapter *adapter;
765 struct opae_manager *mgr;
766 struct opae_accelerator *acc;
767 struct opae_bridge *br;
768 int ret;
769
770 adapter = ifpga_rawdev_get_priv(raw_dev);
771 if (!adapter)
772 return -ENODEV;
773
774 mgr = opae_adapter_get_mgr(adapter);
775 if (!mgr)
776 return -ENODEV;
777
778 acc = opae_adapter_get_acc(adapter, port_id);
779 if (!acc)
780 return -ENODEV;
781
782 br = opae_acc_get_br(acc);
783 if (!br)
784 return -ENODEV;
785
786 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
787 if (ret) {
788 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
789 return ret;
790 }
791
792 ret = opae_bridge_reset(br);
793 if (ret) {
794 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
795 __func__, port_id, ret);
796 return ret;
797 }
798
799 return ret;
800 }
801
802 static int
rte_fpga_do_pr(struct rte_rawdev * rawdev,int port_id,const char * file_name)803 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
804 const char *file_name)
805 {
806 struct stat file_stat;
807 int file_fd;
808 int ret = 0;
809 ssize_t buffer_size;
810 void *buffer, *buf_to_free;
811 u64 pr_error;
812
813 if (!file_name)
814 return -EINVAL;
815
816 file_fd = open(file_name, O_RDONLY);
817 if (file_fd < 0) {
818 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
819 __func__, file_name);
820 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
821 return -EINVAL;
822 }
823 ret = stat(file_name, &file_stat);
824 if (ret) {
825 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
826 file_name);
827 ret = -EINVAL;
828 goto close_fd;
829 }
830 buffer_size = file_stat.st_size;
831 if (buffer_size <= 0) {
832 ret = -EINVAL;
833 goto close_fd;
834 }
835
836 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
837 buffer = rte_malloc(NULL, buffer_size, 0);
838 if (!buffer) {
839 ret = -ENOMEM;
840 goto close_fd;
841 }
842 buf_to_free = buffer;
843
844 /*read the raw data*/
845 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
846 ret = -EINVAL;
847 goto free_buffer;
848 }
849
850 /*do PR now*/
851 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
852 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
853 ret ? "failed" : "success");
854 if (ret) {
855 ret = -EINVAL;
856 goto free_buffer;
857 }
858
859 free_buffer:
860 rte_free(buf_to_free);
861 close_fd:
862 close(file_fd);
863 file_fd = 0;
864 return ret;
865 }
866
867 static int
ifpga_rawdev_pr(struct rte_rawdev * dev,rte_rawdev_obj_t pr_conf)868 ifpga_rawdev_pr(struct rte_rawdev *dev,
869 rte_rawdev_obj_t pr_conf)
870 {
871 struct opae_adapter *adapter;
872 struct opae_manager *mgr;
873 struct opae_board_info *info;
874 struct rte_afu_pr_conf *afu_pr_conf;
875 int ret;
876 struct uuid uuid;
877 struct opae_accelerator *acc;
878
879 IFPGA_RAWDEV_PMD_FUNC_TRACE();
880
881 adapter = ifpga_rawdev_get_priv(dev);
882 if (!adapter)
883 return -ENODEV;
884
885 if (!pr_conf)
886 return -EINVAL;
887
888 afu_pr_conf = pr_conf;
889
890 if (afu_pr_conf->pr_enable) {
891 ret = rte_fpga_do_pr(dev,
892 afu_pr_conf->afu_id.port,
893 afu_pr_conf->bs_path);
894 if (ret) {
895 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
896 return ret;
897 }
898 }
899
900 mgr = opae_adapter_get_mgr(adapter);
901 if (!mgr) {
902 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
903 return -1;
904 }
905
906 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
907 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
908 return -1;
909 }
910
911 if (info->lightweight) {
912 /* set uuid to all 0, when fpga is lightweight image */
913 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
914 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
915 } else {
916 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
917 if (!acc)
918 return -ENODEV;
919
920 ret = opae_acc_get_uuid(acc, &uuid);
921 if (ret)
922 return ret;
923
924 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
925 sizeof(u64));
926 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
927 sizeof(u64));
928
929 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
930 __func__,
931 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
932 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
933 }
934 return 0;
935 }
936
937 static int
ifpga_rawdev_get_attr(struct rte_rawdev * dev,const char * attr_name,uint64_t * attr_value)938 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
939 const char *attr_name, uint64_t *attr_value)
940 {
941 struct opae_adapter *adapter;
942 struct opae_manager *mgr;
943 struct opae_retimer_info opae_rtm_info;
944 struct opae_retimer_status opae_rtm_status;
945 struct opae_eth_group_info opae_eth_grp_info;
946 struct opae_eth_group_region_info opae_eth_grp_reg_info;
947 int eth_group_num = 0;
948 uint64_t port_link_bitmap = 0, port_link_bit;
949 uint32_t i, j, p, q;
950
951 #define MAX_PORT_PER_RETIMER 4
952
953 IFPGA_RAWDEV_PMD_FUNC_TRACE();
954
955 if (!dev || !attr_name || !attr_value) {
956 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
957 return -1;
958 }
959
960 adapter = ifpga_rawdev_get_priv(dev);
961 if (!adapter) {
962 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
963 return -1;
964 }
965
966 mgr = opae_adapter_get_mgr(adapter);
967 if (!mgr) {
968 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
969 return -1;
970 }
971
972 /* currently, eth_group_num is always 2 */
973 eth_group_num = opae_manager_get_eth_group_nums(mgr);
974 if (eth_group_num < 0)
975 return -1;
976
977 if (!strcmp(attr_name, "LineSideBaseMAC")) {
978 /* Currently FPGA not implement, so just set all zeros*/
979 *attr_value = (uint64_t)0;
980 return 0;
981 }
982 if (!strcmp(attr_name, "LineSideMACType")) {
983 /* eth_group 0 on FPGA connect to LineSide */
984 if (opae_manager_get_eth_group_info(mgr, 0,
985 &opae_eth_grp_info))
986 return -1;
987 switch (opae_eth_grp_info.speed) {
988 case ETH_SPEED_10G:
989 *attr_value =
990 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
991 break;
992 case ETH_SPEED_25G:
993 *attr_value =
994 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
995 break;
996 default:
997 *attr_value =
998 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
999 break;
1000 }
1001 return 0;
1002 }
1003 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
1004 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1005 return -1;
1006 switch (opae_rtm_status.speed) {
1007 case MXD_1GB:
1008 *attr_value =
1009 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1010 break;
1011 case MXD_2_5GB:
1012 *attr_value =
1013 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1014 break;
1015 case MXD_5GB:
1016 *attr_value =
1017 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1018 break;
1019 case MXD_10GB:
1020 *attr_value =
1021 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1022 break;
1023 case MXD_25GB:
1024 *attr_value =
1025 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1026 break;
1027 case MXD_40GB:
1028 *attr_value =
1029 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1030 break;
1031 case MXD_100GB:
1032 *attr_value =
1033 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1034 break;
1035 case MXD_SPEED_UNKNOWN:
1036 *attr_value =
1037 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1038 break;
1039 default:
1040 *attr_value =
1041 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1042 break;
1043 }
1044 return 0;
1045 }
1046 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1047 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1048 return -1;
1049 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1050 return 0;
1051 }
1052 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1053 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1054 return -1;
1055 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1056 (uint64_t)opae_rtm_info.nums_retimer;
1057 *attr_value = tmp;
1058 return 0;
1059 }
1060 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1061 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1062 return -1;
1063 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1064 return -1;
1065 (*attr_value) = 0;
1066 q = 0;
1067 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1068 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1069 p = i * MAX_PORT_PER_RETIMER;
1070 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1071 port_link_bit = 0;
1072 IFPGA_BIT_SET(port_link_bit, (p+j));
1073 port_link_bit &= port_link_bitmap;
1074 if (port_link_bit)
1075 IFPGA_BIT_SET((*attr_value), q);
1076 q++;
1077 }
1078 }
1079 return 0;
1080 }
1081 if (!strcmp(attr_name, "LineSideBARIndex")) {
1082 /* eth_group 0 on FPGA connect to LineSide */
1083 if (opae_manager_get_eth_group_region_info(mgr, 0,
1084 &opae_eth_grp_reg_info))
1085 return -1;
1086 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1087 return 0;
1088 }
1089 if (!strcmp(attr_name, "NICSideMACType")) {
1090 /* eth_group 1 on FPGA connect to NicSide */
1091 if (opae_manager_get_eth_group_info(mgr, 1,
1092 &opae_eth_grp_info))
1093 return -1;
1094 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1095 return 0;
1096 }
1097 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1098 /* eth_group 1 on FPGA connect to NicSide */
1099 if (opae_manager_get_eth_group_info(mgr, 1,
1100 &opae_eth_grp_info))
1101 return -1;
1102 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1103 return 0;
1104 }
1105 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1106 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1107 return -1;
1108 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1109 (uint64_t)opae_rtm_info.ports_per_fvl;
1110 *attr_value = tmp;
1111 return 0;
1112 }
1113 if (!strcmp(attr_name, "NICSideLinkStatus"))
1114 return 0;
1115 if (!strcmp(attr_name, "NICSideBARIndex")) {
1116 /* eth_group 1 on FPGA connect to NicSide */
1117 if (opae_manager_get_eth_group_region_info(mgr, 1,
1118 &opae_eth_grp_reg_info))
1119 return -1;
1120 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1121 return 0;
1122 }
1123
1124 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1125 return -1;
1126 }
1127
1128 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1129 .dev_info_get = ifpga_rawdev_info_get,
1130 .dev_configure = ifpga_rawdev_configure,
1131 .dev_start = ifpga_rawdev_start,
1132 .dev_stop = ifpga_rawdev_stop,
1133 .dev_close = ifpga_rawdev_close,
1134 .dev_reset = ifpga_rawdev_reset,
1135
1136 .queue_def_conf = NULL,
1137 .queue_setup = NULL,
1138 .queue_release = NULL,
1139
1140 .attr_get = ifpga_rawdev_get_attr,
1141 .attr_set = NULL,
1142
1143 .enqueue_bufs = NULL,
1144 .dequeue_bufs = NULL,
1145
1146 .dump = NULL,
1147
1148 .xstats_get = NULL,
1149 .xstats_get_names = NULL,
1150 .xstats_get_by_name = NULL,
1151 .xstats_reset = NULL,
1152
1153 .firmware_status_get = NULL,
1154 .firmware_version_get = NULL,
1155 .firmware_load = ifpga_rawdev_pr,
1156 .firmware_unload = NULL,
1157
1158 .dev_selftest = NULL,
1159 };
1160
1161 static int
ifpga_get_fme_error_prop(struct opae_manager * mgr,u64 prop_id,u64 * val)1162 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1163 u64 prop_id, u64 *val)
1164 {
1165 struct feature_prop prop;
1166
1167 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1168 prop.prop_id = prop_id;
1169
1170 if (opae_manager_ifpga_get_prop(mgr, &prop))
1171 return -EINVAL;
1172
1173 *val = prop.data;
1174
1175 return 0;
1176 }
1177
1178 static int
ifpga_set_fme_error_prop(struct opae_manager * mgr,u64 prop_id,u64 val)1179 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1180 u64 prop_id, u64 val)
1181 {
1182 struct feature_prop prop;
1183
1184 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1185 prop.prop_id = prop_id;
1186
1187 prop.data = val;
1188
1189 if (opae_manager_ifpga_set_prop(mgr, &prop))
1190 return -EINVAL;
1191
1192 return 0;
1193 }
1194
1195 static int
fme_err_read_seu_emr(struct opae_manager * mgr)1196 fme_err_read_seu_emr(struct opae_manager *mgr)
1197 {
1198 u64 val;
1199 int ret;
1200
1201 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1202 if (ret)
1203 return -EINVAL;
1204
1205 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1206
1207 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1208 if (ret)
1209 return -EINVAL;
1210
1211 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1212
1213 return 0;
1214 }
1215
fme_clear_warning_intr(struct opae_manager * mgr)1216 static int fme_clear_warning_intr(struct opae_manager *mgr)
1217 {
1218 u64 val;
1219
1220 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1221 return -EINVAL;
1222
1223 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1224 return -EINVAL;
1225 if ((val & 0x40) != 0)
1226 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1227
1228 return 0;
1229 }
1230
fme_clean_fme_error(struct opae_manager * mgr)1231 static int fme_clean_fme_error(struct opae_manager *mgr)
1232 {
1233 u64 val;
1234
1235 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1236 return -EINVAL;
1237
1238 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1239
1240 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1241
1242 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1243 return -EINVAL;
1244
1245 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1246
1247 return 0;
1248 }
1249
1250 static int
fme_err_handle_error0(struct opae_manager * mgr)1251 fme_err_handle_error0(struct opae_manager *mgr)
1252 {
1253 struct feature_fme_error0 fme_error0;
1254 u64 val;
1255
1256 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1257 return -EINVAL;
1258
1259 if (fme_clean_fme_error(mgr))
1260 return -EINVAL;
1261
1262 fme_error0.csr = val;
1263
1264 if (fme_error0.fabric_err)
1265 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1266 else if (fme_error0.fabfifo_overflow)
1267 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1268 else if (fme_error0.afu_acc_mode_err)
1269 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1270 else if (fme_error0.pcie0cdc_parity_err)
1271 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1272 else if (fme_error0.cvlcdc_parity_err)
1273 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1274 else if (fme_error0.fpgaseuerr)
1275 fme_err_read_seu_emr(mgr);
1276
1277 /* clean the errors */
1278 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1279 return -EINVAL;
1280
1281 return 0;
1282 }
1283
1284 static int
fme_err_handle_catfatal_error(struct opae_manager * mgr)1285 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1286 {
1287 struct feature_fme_ras_catfaterror fme_catfatal;
1288 u64 val;
1289
1290 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1291 return -EINVAL;
1292
1293 fme_catfatal.csr = val;
1294
1295 if (fme_catfatal.cci_fatal_err)
1296 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1297 else if (fme_catfatal.fabric_fatal_err)
1298 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1299 else if (fme_catfatal.pcie_poison_err)
1300 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1301 else if (fme_catfatal.inject_fata_err)
1302 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1303 else if (fme_catfatal.crc_catast_err)
1304 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1305 else if (fme_catfatal.injected_catast_err)
1306 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1307 else if (fme_catfatal.bmc_seu_catast_err)
1308 fme_err_read_seu_emr(mgr);
1309
1310 return 0;
1311 }
1312
1313 static int
fme_err_handle_nonfaterror(struct opae_manager * mgr)1314 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1315 {
1316 struct feature_fme_ras_nonfaterror nonfaterr;
1317 u64 val;
1318
1319 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1320 return -EINVAL;
1321
1322 nonfaterr.csr = val;
1323
1324 if (nonfaterr.temp_thresh_ap1)
1325 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1326 else if (nonfaterr.temp_thresh_ap2)
1327 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1328 else if (nonfaterr.pcie_error)
1329 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1330 else if (nonfaterr.portfatal_error)
1331 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1332 else if (nonfaterr.proc_hot)
1333 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1334 else if (nonfaterr.afu_acc_mode_err)
1335 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1336 else if (nonfaterr.injected_nonfata_err) {
1337 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1338 fme_clear_warning_intr(mgr);
1339 } else if (nonfaterr.temp_thresh_AP6)
1340 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1341 else if (nonfaterr.power_thresh_AP1)
1342 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1343 else if (nonfaterr.power_thresh_AP2)
1344 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1345 else if (nonfaterr.mbp_err)
1346 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1347
1348 return 0;
1349 }
1350
1351 static void
fme_interrupt_handler(void * param)1352 fme_interrupt_handler(void *param)
1353 {
1354 struct opae_manager *mgr = (struct opae_manager *)param;
1355
1356 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1357
1358 fme_err_handle_error0(mgr);
1359 fme_err_handle_nonfaterror(mgr);
1360 fme_err_handle_catfatal_error(mgr);
1361 }
1362
1363 int
ifpga_unregister_msix_irq(struct ifpga_rawdev * dev,enum ifpga_irq_type type,int vec_start,rte_intr_callback_fn handler,void * arg)1364 ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type,
1365 int vec_start, rte_intr_callback_fn handler, void *arg)
1366 {
1367 struct rte_intr_handle **intr_handle;
1368 int rc = 0;
1369 int i = vec_start + 1;
1370
1371 if (!dev)
1372 return -ENODEV;
1373
1374 if (type == IFPGA_FME_IRQ)
1375 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1376 else if (type == IFPGA_AFU_IRQ)
1377 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1378 else
1379 return -EINVAL;
1380
1381 if ((*intr_handle) == NULL) {
1382 IFPGA_RAWDEV_PMD_ERR("%s interrupt %d not registered\n",
1383 type == IFPGA_FME_IRQ ? "FME" : "AFU",
1384 type == IFPGA_FME_IRQ ? 0 : vec_start);
1385 return -ENOENT;
1386 }
1387
1388 rte_intr_efd_disable(*intr_handle);
1389
1390 rc = rte_intr_callback_unregister(*intr_handle, handler, arg);
1391 if (rc < 0) {
1392 IFPGA_RAWDEV_PMD_ERR("Failed to unregister %s interrupt %d\n",
1393 type == IFPGA_FME_IRQ ? "FME" : "AFU",
1394 type == IFPGA_FME_IRQ ? 0 : vec_start);
1395 } else {
1396 rte_intr_instance_free(*intr_handle);
1397 *intr_handle = NULL;
1398 }
1399
1400 return rc;
1401 }
1402
1403 int
ifpga_register_msix_irq(struct ifpga_rawdev * dev,int port_id,enum ifpga_irq_type type,int vec_start,int count,rte_intr_callback_fn handler,const char * name,void * arg)1404 ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id,
1405 enum ifpga_irq_type type, int vec_start, int count,
1406 rte_intr_callback_fn handler, const char *name,
1407 void *arg)
1408 {
1409 int ret;
1410 struct rte_intr_handle **intr_handle;
1411 struct opae_adapter *adapter;
1412 struct opae_manager *mgr;
1413 struct opae_accelerator *acc;
1414 int *intr_efds = NULL, nb_intr, i;
1415
1416 if (!dev || !dev->rawdev)
1417 return -ENODEV;
1418
1419 adapter = ifpga_rawdev_get_priv(dev->rawdev);
1420 if (!adapter)
1421 return -ENODEV;
1422
1423 mgr = opae_adapter_get_mgr(adapter);
1424 if (!mgr)
1425 return -ENODEV;
1426
1427 if (type == IFPGA_FME_IRQ) {
1428 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1429 count = 1;
1430 } else if (type == IFPGA_AFU_IRQ) {
1431 i = vec_start + 1;
1432 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1433 } else {
1434 return -EINVAL;
1435 }
1436
1437 if (*intr_handle)
1438 return -EBUSY;
1439
1440 *intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1441 if (!(*intr_handle))
1442 return -ENOMEM;
1443
1444 if (rte_intr_type_set(*intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1445 return -rte_errno;
1446
1447 ret = rte_intr_efd_enable(*intr_handle, count);
1448 if (ret)
1449 return -ENODEV;
1450
1451 if (rte_intr_fd_set(*intr_handle,
1452 rte_intr_efds_index_get(*intr_handle, 0)))
1453 return -rte_errno;
1454
1455 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1456 name, rte_intr_dev_fd_get(*intr_handle),
1457 rte_intr_fd_get(*intr_handle));
1458
1459 if (type == IFPGA_FME_IRQ) {
1460 struct fpga_fme_err_irq_set err_irq_set;
1461 err_irq_set.evtfd = rte_intr_efds_index_get(*intr_handle,
1462 0);
1463
1464 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1465 if (ret)
1466 return -EINVAL;
1467 } else if (type == IFPGA_AFU_IRQ) {
1468 acc = opae_adapter_get_acc(adapter, port_id);
1469 if (!acc)
1470 return -EINVAL;
1471
1472 nb_intr = rte_intr_nb_intr_get(*intr_handle);
1473
1474 intr_efds = calloc(nb_intr, sizeof(int));
1475 if (!intr_efds)
1476 return -ENOMEM;
1477
1478 for (i = 0; i < nb_intr; i++)
1479 intr_efds[i] = rte_intr_efds_index_get(*intr_handle, i);
1480
1481 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1482 if (ret) {
1483 free(intr_efds);
1484 return -EINVAL;
1485 }
1486 }
1487
1488 /* register interrupt handler using DPDK API */
1489 ret = rte_intr_callback_register(*intr_handle,
1490 handler, (void *)arg);
1491 if (ret) {
1492 free(intr_efds);
1493 return -EINVAL;
1494 }
1495
1496 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1497
1498 free(intr_efds);
1499 return 0;
1500 }
1501
1502 static int
ifpga_rawdev_create(struct rte_pci_device * pci_dev,int socket_id)1503 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1504 int socket_id)
1505 {
1506 int ret = 0;
1507 struct rte_rawdev *rawdev = NULL;
1508 struct ifpga_rawdev *dev = NULL;
1509 struct opae_adapter *adapter = NULL;
1510 struct opae_manager *mgr = NULL;
1511 struct opae_adapter_data_pci *data = NULL;
1512 char name[RTE_RAWDEV_NAME_MAX_LEN];
1513 int i;
1514
1515 if (!pci_dev) {
1516 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1517 ret = -EINVAL;
1518 goto cleanup;
1519 }
1520
1521 memset(name, 0, sizeof(name));
1522 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1523 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1524
1525 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1526
1527 /* Allocate device structure */
1528 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1529 socket_id);
1530 if (rawdev == NULL) {
1531 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1532 ret = -EINVAL;
1533 goto cleanup;
1534 }
1535
1536 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1537 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1538
1539 dev = ifpga_rawdev_allocate(rawdev);
1540 if (dev == NULL) {
1541 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1542 ret = -EINVAL;
1543 goto cleanup;
1544 }
1545 dev->aer_enable = 0;
1546
1547 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1548 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1549 if (!data) {
1550 ret = -ENOMEM;
1551 goto cleanup;
1552 }
1553
1554 /* init opae_adapter_data_pci for device specific information */
1555 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1556 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1557 data->region[i].len = pci_dev->mem_resource[i].len;
1558 data->region[i].addr = pci_dev->mem_resource[i].addr;
1559 }
1560 data->device_id = pci_dev->id.device_id;
1561 data->vendor_id = pci_dev->id.vendor_id;
1562 data->bus = pci_dev->addr.bus;
1563 data->devid = pci_dev->addr.devid;
1564 data->function = pci_dev->addr.function;
1565 data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1566
1567 adapter = rawdev->dev_private;
1568 /* create a opae_adapter based on above device data */
1569 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1570 if (ret) {
1571 ret = -ENOMEM;
1572 goto free_adapter_data;
1573 }
1574
1575 rawdev->dev_ops = &ifpga_rawdev_ops;
1576 rawdev->device = &pci_dev->device;
1577 rawdev->driver_name = pci_dev->driver->driver.name;
1578
1579 /* must enumerate the adapter before use it */
1580 ret = opae_adapter_enumerate(adapter);
1581 if (ret)
1582 goto free_adapter_data;
1583
1584 /* get opae_manager to rawdev */
1585 mgr = opae_adapter_get_mgr(adapter);
1586 if (mgr) {
1587 /* PF function */
1588 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1589 }
1590
1591 ret = ifpga_register_msix_irq(dev, 0, IFPGA_FME_IRQ, 0, 0,
1592 fme_interrupt_handler, "fme_irq", mgr);
1593 if (ret)
1594 goto free_adapter_data;
1595
1596 ret = ifpga_monitor_start_func(dev);
1597 if (ret)
1598 goto free_adapter_data;
1599
1600 return ret;
1601
1602 free_adapter_data:
1603 if (data)
1604 opae_adapter_data_free(data);
1605 cleanup:
1606 if (rawdev)
1607 rte_rawdev_pmd_release(rawdev);
1608
1609 return ret;
1610 }
1611
1612 static int
ifpga_rawdev_destroy(struct rte_pci_device * pci_dev)1613 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1614 {
1615 int ret;
1616 struct rte_rawdev *rawdev;
1617 char name[RTE_RAWDEV_NAME_MAX_LEN];
1618 struct opae_adapter *adapter;
1619 struct opae_manager *mgr;
1620 struct ifpga_rawdev *dev;
1621
1622 if (!pci_dev) {
1623 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1624 ret = -EINVAL;
1625 return ret;
1626 }
1627
1628 memset(name, 0, sizeof(name));
1629 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1630 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1631
1632 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1633 name, rte_socket_id());
1634
1635 rawdev = rte_rawdev_pmd_get_named_dev(name);
1636 if (!rawdev) {
1637 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1638 return -EINVAL;
1639 }
1640 dev = ifpga_rawdev_get(rawdev);
1641 if (dev)
1642 dev->rawdev = NULL;
1643
1644 adapter = ifpga_rawdev_get_priv(rawdev);
1645 if (!adapter)
1646 return -ENODEV;
1647
1648 mgr = opae_adapter_get_mgr(adapter);
1649 if (!mgr)
1650 return -ENODEV;
1651
1652 if (ifpga_unregister_msix_irq(dev, IFPGA_FME_IRQ, 0,
1653 fme_interrupt_handler, mgr) < 0)
1654 return -EINVAL;
1655
1656 /* rte_rawdev_close is called by pmd_release */
1657 ret = rte_rawdev_pmd_release(rawdev);
1658 if (ret)
1659 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1660
1661 return ret;
1662 }
1663
1664 static int
ifpga_rawdev_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)1665 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1666 struct rte_pci_device *pci_dev)
1667 {
1668 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1669 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1670 }
1671
1672 static int
ifpga_rawdev_pci_remove(struct rte_pci_device * pci_dev)1673 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1674 {
1675 IFPGA_RAWDEV_PMD_INFO("remove pci_dev %s", pci_dev->device.name);
1676 return ifpga_rawdev_destroy(pci_dev);
1677 }
1678
1679 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1680 .id_table = pci_ifpga_map,
1681 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1682 .probe = ifpga_rawdev_pci_probe,
1683 .remove = ifpga_rawdev_pci_remove,
1684 };
1685
1686 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1687 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1688 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1689 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1690
1691 static const char * const valid_args[] = {
1692 #define IFPGA_ARG_NAME "ifpga"
1693 IFPGA_ARG_NAME,
1694 #define IFPGA_ARG_PORT "port"
1695 IFPGA_ARG_PORT,
1696 #define IFPGA_AFU_BTS "afu_bts"
1697 IFPGA_AFU_BTS,
1698 NULL
1699 };
1700
ifpga_rawdev_get_string_arg(const char * key __rte_unused,const char * value,void * extra_args)1701 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1702 const char *value, void *extra_args)
1703 {
1704 int size;
1705 if (!value || !extra_args)
1706 return -EINVAL;
1707
1708 size = strlen(value) + 1;
1709 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1710 if (!*(char **)extra_args)
1711 return -ENOMEM;
1712
1713 strlcpy(*(char **)extra_args, value, size);
1714
1715 return 0;
1716 }
1717 static int
ifpga_cfg_probe(struct rte_vdev_device * dev)1718 ifpga_cfg_probe(struct rte_vdev_device *dev)
1719 {
1720 struct rte_devargs *devargs;
1721 struct rte_kvargs *kvlist = NULL;
1722 struct rte_rawdev *rawdev = NULL;
1723 struct ifpga_rawdev *ifpga_dev;
1724 int port;
1725 char *name = NULL;
1726 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1727 int ret = -1;
1728
1729 devargs = dev->device.devargs;
1730
1731 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1732 if (!kvlist) {
1733 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1734 goto end;
1735 }
1736
1737 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1738 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1739 &ifpga_rawdev_get_string_arg,
1740 &name) < 0) {
1741 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1742 IFPGA_ARG_NAME);
1743 goto end;
1744 }
1745 } else {
1746 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1747 IFPGA_ARG_NAME);
1748 goto end;
1749 }
1750
1751 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1752 if (rte_kvargs_process(kvlist,
1753 IFPGA_ARG_PORT,
1754 &rte_ifpga_get_integer32_arg,
1755 &port) < 0) {
1756 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1757 IFPGA_ARG_PORT);
1758 goto end;
1759 }
1760 } else {
1761 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1762 IFPGA_ARG_PORT);
1763 goto end;
1764 }
1765
1766 memset(dev_name, 0, sizeof(dev_name));
1767 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1768 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1769 if (!rawdev)
1770 goto end;
1771 ifpga_dev = ifpga_rawdev_get(rawdev);
1772 if (!ifpga_dev)
1773 goto end;
1774
1775 memset(dev_name, 0, sizeof(dev_name));
1776 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1777 port, name);
1778
1779 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1780 dev_name, devargs->args);
1781 end:
1782 rte_kvargs_free(kvlist);
1783 free(name);
1784
1785 return ret;
1786 }
1787
1788 static int
ifpga_cfg_remove(struct rte_vdev_device * vdev)1789 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1790 {
1791 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1792 vdev);
1793
1794 return 0;
1795 }
1796
1797 static struct rte_vdev_driver ifpga_cfg_driver = {
1798 .probe = ifpga_cfg_probe,
1799 .remove = ifpga_cfg_remove,
1800 };
1801
1802 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1803 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1804 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1805 "ifpga=<string> "
1806 "port=<int> "
1807 "afu_bts=<path>");
1808
ifpga_get_pci_bus(void)1809 struct rte_pci_bus *ifpga_get_pci_bus(void)
1810 {
1811 return rte_ifpga_rawdev_pmd.bus;
1812 }
1813
ifpga_rawdev_partial_reconfigure(struct rte_rawdev * dev,int port,const char * file)1814 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1815 const char *file)
1816 {
1817 if (!dev) {
1818 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1819 return -EINVAL;
1820 }
1821
1822 return rte_fpga_do_pr(dev, port, file);
1823 }
1824
ifpga_rawdev_cleanup(void)1825 void ifpga_rawdev_cleanup(void)
1826 {
1827 struct ifpga_rawdev *dev;
1828 unsigned int i;
1829
1830 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1831 dev = &ifpga_rawdevices[i];
1832 if (dev->rawdev) {
1833 rte_rawdev_pmd_release(dev->rawdev);
1834 dev->rawdev = NULL;
1835 }
1836 }
1837 }
1838