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Searched refs:GENMASK (Results 1 – 25 of 31) sorted by relevance

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/dpdk/drivers/net/hns3/
H A Dhns3_intr.h25 #define HNS3_MAC_TNL_INT_EN GENMASK(9, 0)
26 #define HNS3_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
27 #define HNS3_MAC_TNL_INT_CLR GENMASK(9, 0)
45 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
47 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
53 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
55 #define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
56 #define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
58 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
64 #define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0)
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H A Dhns3_cmd.h431 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
449 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
468 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
475 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
584 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
754 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
885 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
890 #define HNS3_INT_TYPE_M GENMASK(1, 0)
892 #define HNS3_TQP_ID_M GENMASK(12, 2)
894 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
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H A Dhns3_dcb.h59 #define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0)
61 #define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10)
64 #define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11)
77 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
79 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
81 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
83 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
85 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
132 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
134 #define HNS3_BP_GRP_ID_M GENMASK(9, 5)
H A Dhns3_fdir.c20 #define HNS3_PF_ID_M GENMASK(2, 0)
22 #define HNS3_VF_ID_M GENMASK(10, 3)
25 #define HNS3_NETWORK_PORT_ID_M GENMASK(3, 0)
33 #define HNS3_FD_AD_QID_M GENMASK(11, 2)
36 #define HNS3_FD_AD_COUNTER_NUM_M GENMASK(19, 13)
39 #define HNS3_FD_AD_NXT_KEY_M GENMASK(25, 21)
42 #define HNS3_FD_AD_RULE_ID_M GENMASK(12, 1)
45 #define HNS3_FD_AD_QUEUE_REGION_SIZE_M GENMASK(20, 17)
687 GENMASK(cur_pos + tuple_size, in hns3_fd_convert_meta_data()
693 GENMASK(cur_pos + tuple_size, cur_pos), in hns3_fd_convert_meta_data()
/dpdk/drivers/raw/ifpga/base/
H A Dopae_intel_max10.h93 #define MAX10_MAC_BYTE4 GENMASK(7, 0)
94 #define MAX10_MAC_BYTE3 GENMASK(15, 8)
95 #define MAX10_MAC_BYTE2 GENMASK(23, 16)
98 #define MAX10_MAC_BYTE6 GENMASK(7, 0)
99 #define MAX10_MAC_BYTE5 GENMASK(15, 8)
102 #define FPGA_RECONF_PAGE GENMASK(2, 0)
119 #define PCB_INFO GENMASK(31, 24)
126 #define SEC_PROGRESS GENMASK(7, 4)
138 #define HOST_STATUS GENMASK(11, 8)
143 #define SEC_STATUS GENMASK(23, 16)
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H A Dopae_spi.h164 #define REQ_FEC_MODE GENMASK(23, 8)
173 #define NIOS_VERSION_MAJOR GENMASK(31, 28)
174 #define NIOS_VERSION_MINOR GENMASK(27, 24)
175 #define NIOS_VERSION_PATCH GENMASK(23, 20)
H A Dopae_osdep.h44 #ifndef GENMASK
45 #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) macro
H A Dopae_ifpga_hw_api.h46 #define PROP_TOP GENMASK(31, 24)
48 #define PROP_SUB GENMASK(23, 16)
50 #define PROP_ID GENMASK(15, 0)
H A Dopae_eth_group.h51 #define MAC_RESET_MASK GENMASK(2, 0)
/dpdk/drivers/common/cnxk/
H A Droc_npc_mcam_dump.c388 GENMASK(19, 0); in npc_flow_dump_tx_action()
393 GENMASK(15, 0); in npc_flow_dump_tx_action()
451 GENMASK(15, 0); in npc_flow_dump_rx_action()
456 GENMASK(19, 0); in npc_flow_dump_rx_action()
461 GENMASK(15, 0); in npc_flow_dump_rx_action()
503 GENMASK(7, 0); in npc_flow_dump_rx_vtag_action()
544 GENMASK(1, 0); in npc_flow_dump_tx_vtag_action()
546 GENMASK(9, 0); in npc_flow_dump_tx_vtag_action()
556 GENMASK(7, 0); in npc_flow_dump_tx_vtag_action()
560 GENMASK(1, 0); in npc_flow_dump_tx_vtag_action()
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H A Droc_bits.h23 #ifndef GENMASK
24 #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) macro
H A Droc_npc_mcam.c507 req->entry_data.kw[0] &= ~(GENMASK(11, 0)); in npc_mcam_set_channel()
508 req->entry_data.kw_mask[0] &= ~(GENMASK(11, 0)); in npc_mcam_set_channel()
509 flow->mcam_data[0] &= ~(GENMASK(11, 0)); in npc_mcam_set_channel()
510 flow->mcam_mask[0] &= ~(GENMASK(11, 0)); in npc_mcam_set_channel()
600 req->entry_data.action &= ~(GENMASK(19, 4)); in npc_mcam_alloc_and_write()
602 flow->npc_action &= ~(GENMASK(19, 4)); in npc_mcam_alloc_and_write()
/dpdk/drivers/dma/hisilicon/
H A Dhisi_dmadev.h13 #define GENMASK(h, l) \ macro
88 #define HISI_DMA_QUEUE_FSM_STS_M GENMASK(3, 0)
101 #define HISI_DMA_HIP08_QUEUE_INT_MASK_M GENMASK(14, 0)
115 #define HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M GENMASK(31, 28)
120 #define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M GENMASK(18, 1)
182 #define CQE_SQ_HEAD_MASK GENMASK(15, 0)
184 #define CQE_STATUS_MASK GENMASK(63, 49)
/dpdk/drivers/net/ena/base/ena_defs/
H A Dena_eth_io_defs.h278 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
291 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
297 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
308 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
313 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
332 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
333 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
335 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
354 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
356 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
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H A Dena_admin_defs.h1105 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1114 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1122 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1123 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1125 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1131 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1134 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1166 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1180 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1187 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
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/dpdk/drivers/dma/dpaa/
H A Ddpaa_qdma.h17 #ifndef GENMASK
19 #define GENMASK(h, l) \ macro
86 #define QDMA_CCDF_MASK GENMASK(28, 20)
91 #define QDMA_SG_LEN_MASK GENMASK(29, 0)
/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_nsp.h65 #define NSP_CODE_MAJOR GENMASK(15, 12)
66 #define NSP_CODE_MINOR GENMASK(11, 0)
/dpdk/drivers/net/cnxk/
H A Dcnxk_ethdev_sec.c169 if (chan > GENMASK(12, 0) || mask > GENMASK(12, 0)) in parse_inl_cpt_channel()
H A Dcnxk_ethdev_devargs.c222 if (chan > GENMASK(11, 0) || mask > GENMASK(11, 0)) in parse_sdp_channel_mask()
/dpdk/drivers/net/dpaa2/mc/
H A Dfsl_dpkg.h64 GENMASK(DPKG_##field##_SHIFT + DPKG_##field##_SIZE - 1, \
H A Dfsl_dprtc_cmd.h48 GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \
/dpdk/drivers/bus/fslmc/mc/
H A Dfsl_dpio_cmd.h46 GENMASK(DPIO_##field##_SHIFT + DPIO_##field##_SIZE - 1, \
H A Dfsl_dpdmai_cmd.h40 GENMASK(DPDMAI_##field##_SHIFT + DPDMAI_##field##_SIZE - 1, \
H A Dfsl_mc_cmd.h33 #define GENMASK(h, l) \ macro
H A Dfsl_dpci_cmd.h43 GENMASK(DPCI_##field##_SHIFT + DPCI_##field##_SIZE - 1, \

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