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Searched refs:EFX_MASK32 (Results 1 – 13 of 13) sorted by relevance

/dpdk/drivers/common/sfc_efx/base/
H A Def10_rx.c242 EFX_MASK32(EFX_RX_CLASS_IPV4_TCP), in efx_mcdi_rss_context_set_flags()
245 EFX_MASK32(EFX_RX_CLASS_IPV4_UDP), in efx_mcdi_rss_context_set_flags()
247 (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4), in efx_mcdi_rss_context_set_flags()
250 EFX_MASK32(EFX_RX_CLASS_IPV6_TCP), in efx_mcdi_rss_context_set_flags()
253 EFX_MASK32(EFX_RX_CLASS_IPV6_UDP), in efx_mcdi_rss_context_set_flags()
255 (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6)); in efx_mcdi_rss_context_set_flags()
H A Defx_types.h143 #define EFX_MASK32(_field) \ macro
509 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
513 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
517 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
521 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
525 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
529 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
533 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
1515 EFX_INSERT_FIELD32(_min, _max, _field, EFX_MASK32(_field))
H A Def10_ev.c446 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in ef10_ev_rx_packed_stream()
600 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in ef10_ev_rx()
H A Defx_mae.c698 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) { in efx_mae_mport_by_phy_port()
754 EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_INTF_ID)); in efx_mae_intf_to_selector()
759 EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_INTF_ID)); in efx_mae_intf_to_selector()
764 EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_INTF_ID)); in efx_mae_intf_to_selector()
797 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_MH_PF_ID)) { in efx_mae_mport_by_pcie_mh_function()
802 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) { in efx_mae_mport_by_pcie_mh_function()
H A Drhead_nic.c47 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_GZ_TX_SEND_LEN); in rhead_board_cfg()
H A Defx_intr.c415 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL)) in siena_intr_trigger()
H A Dsiena_nic.c149 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT); in siena_board_cfg()
H A Defx_mcdi.c280 seq = emip->emi_seq++ & EFX_MASK32(MCDI_HEADER_SEQ); in efx_mcdi_request_start()
389 (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { in efx_mcdi_read_response_header()
883 (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { in efx_mcdi_ev_cpl()
H A Def10_filter.c99 #define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match)) in ef10_filter_init()
H A Def10_nic.c2233 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); in ef10_nic_board_cfg()
/dpdk/drivers/net/sfc/
H A Dsfc_ef10_rx.c265 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in sfc_ef10_rx_process_event()
548 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in sfc_ef10_rx_qdesc_npending()
H A Dsfc_ef10_essb_rx.c259 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in sfc_ef10_essb_rx_process_ev()
H A Dsfc_ef100_tx.c194 } else if (m->nb_segs > EFX_MASK32(ESF_GZ_TX_SEND_NUM_SEGS)) { in sfc_ef100_tx_prepare_pkts()