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Searched refs:EFX_ARRAY_SIZE (Results 1 – 13 of 13) sorted by relevance

/dpdk/drivers/common/sfc_efx/base/
H A Dsiena_nic.c761 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks) in siena_nic_register_test()
762 == EFX_ARRAY_SIZE(__siena_registers) * 4); in siena_nic_register_test()
764 nitems = EFX_ARRAY_SIZE(__siena_registers); in siena_nic_register_test()
775 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks) in siena_nic_register_test()
776 == EFX_ARRAY_SIZE(__siena_tables) * 4); in siena_nic_register_test()
778 nitems = EFX_ARRAY_SIZE(__siena_tables); in siena_nic_register_test()
789 EFX_ARRAY_SIZE(__siena_registers))) != 0) in siena_nic_register_test()
794 EFX_ARRAY_SIZE(__siena_tables))) != 0) in siena_nic_register_test()
799 EFX_ARRAY_SIZE(__siena_tables))) != 0) in siena_nic_register_test()
803 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0) in siena_nic_register_test()
H A Def10_mac.c475 ef10_common, EFX_ARRAY_SIZE(ef10_common))) != 0) in ef10_mac_stats_get_mask()
484 ef10_40g_extra, EFX_ARRAY_SIZE(ef10_40g_extra))) != 0) in ef10_mac_stats_get_mask()
490 EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0) in ef10_mac_stats_get_mask()
495 ef10_tx_size_bins, EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0) in ef10_mac_stats_get_mask()
505 ef10_pm_and_rxdp, EFX_ARRAY_SIZE(ef10_pm_and_rxdp))) != 0) in ef10_mac_stats_get_mask()
516 ef10_vadaptor, EFX_ARRAY_SIZE(ef10_vadaptor))) != 0) in ef10_mac_stats_get_mask()
526 ef10_fec, EFX_ARRAY_SIZE(ef10_fec))) != 0) in ef10_mac_stats_get_mask()
537 ef10_rxdp_sdt, EFX_ARRAY_SIZE(ef10_rxdp_sdt))) != 0) in ef10_mac_stats_get_mask()
546 ef10_hlb, EFX_ARRAY_SIZE(ef10_hlb))) != 0) in ef10_mac_stats_get_mask()
H A Drhead_rx.c358 if (mcdi_idx >= EFX_ARRAY_SIZE(efx_mcdi_to_rx_prefix_field)) in efx_mcdi_rx_prefix_field_map()
394 if (field >= EFX_ARRAY_SIZE(efx_rx_prefix_field_to_mcdi)) in efx_rx_prefix_field_map_to_mcdi()
543 EFX_ARRAY_SIZE(prefix_ids), &num, prefix_ids); in rhead_rx_choose_prefix_id()
H A Defx_mae.c952 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set); in efx_mae_match_spec_field_set()
958 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set); in efx_mae_match_spec_field_set()
1086 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set); in efx_mae_match_spec_bit_set()
1092 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set); in efx_mae_match_spec_bit_set()
1252 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set); in efx_mae_match_spec_is_valid()
1255 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set); in efx_mae_match_spec_is_valid()
1262 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set); in efx_mae_match_spec_is_valid()
1733 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) { in efx_mae_action_set_spec_populate()
2015 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set); in efx_mae_match_specs_class_cmp()
2018 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set); in efx_mae_match_specs_class_cmp()
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H A Dsiena_nvram.c249 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) { in siena_nvram_type_to_partn()
277 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) { in siena_nvram_test()
520 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
H A Def10_filter.c1497 EFX_ARRAY_SIZE(eftp->eft_mulcst_filter_indexes)) {
1666 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(ef10_filter_encap_list) <= in ef10_filter_insert_encap_filters()
1667 EFX_ARRAY_SIZE(table->eft_encap_filter_indexes)); in ef10_filter_insert_encap_filters()
1684 for (i = 0; i < EFX_ARRAY_SIZE(ef10_filter_encap_list); i++) { in ef10_filter_insert_encap_filters()
1737 for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) { in ef10_filter_remove_old()
2107 for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) {
H A Defx_port.c193 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__efx_loopback_type_name) == in efx_loopback_type_name()
H A Def10_ev.c1086 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state)); in ef10_ev_rxlabel_init()
1135 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state)); in ef10_ev_rxlabel_fini()
H A Dsiena_mac.c228 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0) in siena_mac_stats_get_mask()
H A Def10_nvram.c2360 *parttbl_rowsp = EFX_ARRAY_SIZE(hunt_parttbl); in ef10_parttbl_get()
2365 *parttbl_rowsp = EFX_ARRAY_SIZE(medford_parttbl); in ef10_parttbl_get()
2370 *parttbl_rowsp = EFX_ARRAY_SIZE(medford2_parttbl); in ef10_parttbl_get()
H A Def10_nic.c843 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle)); in ef10_nic_alloc_piobufs()
1851 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) { in ef10_external_port_mapping()
H A Defx_rx.c644 EFX_ARRAY_SIZE(type_flags), &type_nflags); in efx_rx_scale_mode_set()
H A Defx.h23 #define EFX_ARRAY_SIZE(_array) \ macro