1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2016-2022 NXP 5 * 6 */ 7 #ifndef _FSL_DPNI_CMD_H 8 #define _FSL_DPNI_CMD_H 9 10 /* DPNI Version */ 11 #define DPNI_VER_MAJOR 8 12 #define DPNI_VER_MINOR 2 13 14 #define DPNI_CMD_BASE_VERSION 1 15 #define DPNI_CMD_VERSION_2 2 16 #define DPNI_CMD_VERSION_3 3 17 #define DPNI_CMD_VERSION_4 4 18 #define DPNI_CMD_VERSION_5 5 19 #define DPNI_CMD_VERSION_6 6 20 #define DPNI_CMD_VERSION_7 7 21 #define DPNI_CMD_ID_OFFSET 4 22 23 #define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION) 24 #define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_2) 25 #define DPNI_CMD_V3(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_3) 26 #define DPNI_CMD_V4(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_4) 27 #define DPNI_CMD_V5(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_5) 28 #define DPNI_CMD_V6(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_6) 29 #define DPNI_CMD_V7(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_7) 30 31 /* Command IDs */ 32 #define DPNI_CMDID_OPEN DPNI_CMD(0x801) 33 #define DPNI_CMDID_CLOSE DPNI_CMD(0x800) 34 #define DPNI_CMDID_CREATE DPNI_CMD_V7(0x901) 35 #define DPNI_CMDID_DESTROY DPNI_CMD(0x981) 36 #define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01) 37 38 #define DPNI_CMDID_ENABLE DPNI_CMD(0x002) 39 #define DPNI_CMDID_DISABLE DPNI_CMD(0x003) 40 #define DPNI_CMDID_GET_ATTR DPNI_CMD_V6(0x004) 41 #define DPNI_CMDID_RESET DPNI_CMD(0x005) 42 #define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006) 43 44 #define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012) 45 #define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013) 46 #define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014) 47 #define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015) 48 #define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016) 49 #define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017) 50 51 #define DPNI_CMDID_SET_POOLS DPNI_CMD_V3(0x200) 52 #define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B) 53 54 #define DPNI_CMDID_GET_QDID DPNI_CMD(0x210) 55 #define DPNI_CMDID_GET_SP_INFO DPNI_CMD(0x211) 56 #define DPNI_CMDID_GET_TX_DATA_OFFSET DPNI_CMD(0x212) 57 #define DPNI_CMDID_GET_LINK_STATE DPNI_CMD_V2(0x215) 58 #define DPNI_CMDID_SET_MAX_FRAME_LENGTH DPNI_CMD(0x216) 59 #define DPNI_CMDID_GET_MAX_FRAME_LENGTH DPNI_CMD(0x217) 60 #define DPNI_CMDID_SET_LINK_CFG DPNI_CMD_V2(0x21A) 61 #define DPNI_CMDID_SET_TX_SHAPING DPNI_CMD_V3(0x21B) 62 63 #define DPNI_CMDID_SET_MCAST_PROMISC DPNI_CMD(0x220) 64 #define DPNI_CMDID_GET_MCAST_PROMISC DPNI_CMD(0x221) 65 #define DPNI_CMDID_SET_UNICAST_PROMISC DPNI_CMD(0x222) 66 #define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223) 67 #define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224) 68 #define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225) 69 #define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD_V2(0x226) 70 #define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227) 71 #define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228) 72 73 #define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230) 74 #define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231) 75 #define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232) 76 #define DPNI_CMDID_CLR_VLAN_FILTERS DPNI_CMD(0x233) 77 78 #define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD_V4(0x235) 79 80 #define DPNI_CMDID_SET_RX_TC_POLICING DPNI_CMD(0x23E) 81 82 #define DPNI_CMDID_SET_QOS_TBL DPNI_CMD_V2(0x240) 83 #define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD_V2(0x241) 84 #define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242) 85 #define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243) 86 #define DPNI_CMDID_ADD_FS_ENT DPNI_CMD_V2(0x244) 87 #define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245) 88 #define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246) 89 90 #define DPNI_CMDID_SET_TX_PRIORITIES DPNI_CMD_V3(0x250) 91 #define DPNI_CMDID_GET_RX_TC_POLICING DPNI_CMD(0x251) 92 93 #define DPNI_CMDID_GET_STATISTICS DPNI_CMD_V4(0x25D) 94 #define DPNI_CMDID_RESET_STATISTICS DPNI_CMD(0x25E) 95 #define DPNI_CMDID_GET_QUEUE DPNI_CMD_V3(0x25F) 96 #define DPNI_CMDID_SET_QUEUE DPNI_CMD_V3(0x260) 97 #define DPNI_CMDID_GET_TAILDROP DPNI_CMD_V2(0x261) 98 #define DPNI_CMDID_SET_TAILDROP DPNI_CMD_V3(0x262) 99 100 #define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263) 101 102 #define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD_V2(0x264) 103 #define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD_V2(0x265) 104 105 #define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD_V3(0x267) 106 #define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD_V3(0x268) 107 #define DPNI_CMDID_SET_EARLY_DROP DPNI_CMD_V3(0x269) 108 #define DPNI_CMDID_GET_EARLY_DROP DPNI_CMD_V3(0x26A) 109 #define DPNI_CMDID_GET_OFFLOAD DPNI_CMD_V2(0x26B) 110 #define DPNI_CMDID_SET_OFFLOAD DPNI_CMD_V2(0x26C) 111 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266) 112 #define DPNI_CMDID_GET_TX_CONFIRMATION_MODE DPNI_CMD(0x26D) 113 #define DPNI_CMDID_SET_OPR DPNI_CMD_V2(0x26e) 114 #define DPNI_CMDID_GET_OPR DPNI_CMD_V2(0x26f) 115 #define DPNI_CMDID_LOAD_SW_SEQUENCE DPNI_CMD(0x270) 116 #define DPNI_CMDID_ENABLE_SW_SEQUENCE DPNI_CMD(0x271) 117 #define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT DPNI_CMD(0x272) 118 #define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD_V2(0x273) 119 #define DPNI_CMDID_SET_RX_HASH_DIST DPNI_CMD_V2(0x274) 120 #define DPNI_CMDID_ADD_CUSTOM_TPID DPNI_CMD(0x275) 121 #define DPNI_CMDID_REMOVE_CUSTOM_TPID DPNI_CMD(0x276) 122 #define DPNI_CMDID_GET_CUSTOM_TPID DPNI_CMD(0x277) 123 #define DPNI_CMDID_GET_LINK_CFG DPNI_CMD(0x278) 124 #define DPNI_CMDID_SET_PORT_CFG DPNI_CMD(0x27B) 125 126 /* Macros for accessing command fields smaller than 1byte */ 127 #define DPNI_MASK(field) \ 128 GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \ 129 DPNI_##field##_SHIFT) 130 #define dpni_set_field(var, field, val) \ 131 ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) 132 #define dpni_get_field(var, field) \ 133 (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT) 134 135 #pragma pack(push, 1) 136 struct dpni_cmd_open { 137 uint32_t dpni_id; 138 }; 139 140 struct dpni_cmd_create { 141 uint32_t options; 142 uint8_t num_queues; 143 uint8_t num_tcs; 144 uint8_t mac_filter_entries; 145 uint8_t num_channels; 146 uint8_t vlan_filter_entries; 147 uint8_t pad2; 148 uint8_t qos_entries; 149 uint8_t pad3; 150 uint16_t fs_entries; 151 uint8_t num_rx_tcs; 152 uint8_t pad4; 153 uint8_t num_cgs; 154 uint16_t num_opr; 155 uint8_t dist_key_size; 156 }; 157 158 struct dpni_cmd_destroy { 159 uint32_t dpsw_id; 160 }; 161 162 #define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) 163 164 struct dpni_cmd_pool { 165 uint16_t dpbp_id; 166 uint8_t priority_mask; 167 uint8_t pad; 168 }; 169 170 struct dpni_cmd_set_pools { 171 uint8_t num_dpbp; 172 uint8_t backup_pool_mask; 173 uint8_t pad; 174 uint8_t pool_options; 175 struct dpni_cmd_pool pool[8]; 176 uint16_t buffer_size[8]; 177 }; 178 179 /* The enable indication is always the least significant bit */ 180 #define DPNI_ENABLE_SHIFT 0 181 #define DPNI_ENABLE_SIZE 1 182 183 struct dpni_rsp_is_enabled { 184 uint8_t enabled; 185 }; 186 187 struct dpni_cmd_set_irq_enable { 188 uint8_t enable; 189 uint8_t pad[3]; 190 uint8_t irq_index; 191 }; 192 193 struct dpni_cmd_get_irq_enable { 194 uint32_t pad; 195 uint8_t irq_index; 196 }; 197 198 struct dpni_rsp_get_irq_enable { 199 uint8_t enabled; 200 }; 201 202 struct dpni_cmd_set_irq_mask { 203 uint32_t mask; 204 uint8_t irq_index; 205 }; 206 207 struct dpni_cmd_get_irq_mask { 208 uint32_t pad; 209 uint8_t irq_index; 210 }; 211 212 struct dpni_rsp_get_irq_mask { 213 uint32_t mask; 214 }; 215 216 struct dpni_cmd_get_irq_status { 217 uint32_t status; 218 uint8_t irq_index; 219 }; 220 221 struct dpni_rsp_get_irq_status { 222 uint32_t status; 223 }; 224 225 struct dpni_cmd_clear_irq_status { 226 uint32_t status; 227 uint8_t irq_index; 228 }; 229 230 struct dpni_rsp_get_attr { 231 /* response word 0 */ 232 uint32_t options; 233 uint8_t num_queues; 234 uint8_t num_rx_tcs; 235 uint8_t mac_filter_entries; 236 uint8_t num_tx_tcs; 237 /* response word 1 */ 238 uint8_t vlan_filter_entries; 239 uint8_t num_channels; 240 uint8_t qos_entries; 241 uint8_t pad2; 242 uint16_t fs_entries; 243 uint16_t num_opr; 244 /* response word 2 */ 245 uint8_t qos_key_size; 246 uint8_t fs_key_size; 247 uint16_t wriop_version; 248 uint8_t num_cgs; 249 }; 250 251 #define DPNI_ERROR_ACTION_SHIFT 0 252 #define DPNI_ERROR_ACTION_SIZE 4 253 #define DPNI_FRAME_ANN_SHIFT 4 254 #define DPNI_FRAME_ANN_SIZE 1 255 256 struct dpni_cmd_set_errors_behavior { 257 uint32_t errors; 258 /* from least significant bit: error_action:4, set_frame_annotation:1 */ 259 uint8_t flags; 260 }; 261 262 /* There are 3 separate commands for configuring Rx, Tx and Tx confirmation 263 * buffer layouts, but they all share the same parameters. 264 * If one of the functions changes, below structure needs to be split. 265 */ 266 267 #define DPNI_PASS_TS_SHIFT 0 268 #define DPNI_PASS_TS_SIZE 1 269 #define DPNI_PASS_PR_SHIFT 1 270 #define DPNI_PASS_PR_SIZE 1 271 #define DPNI_PASS_FS_SHIFT 2 272 #define DPNI_PASS_FS_SIZE 1 273 #define DPNI_PASS_SWO_SHIFT 3 274 #define DPNI_PASS_SWO_SIZE 1 275 276 struct dpni_cmd_get_buffer_layout { 277 uint8_t qtype; 278 }; 279 280 struct dpni_rsp_get_buffer_layout { 281 /* response word 0 */ 282 uint8_t pad0[6]; 283 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ 284 uint8_t flags; 285 uint8_t pad1; 286 /* response word 1 */ 287 uint16_t private_data_size; 288 uint16_t data_align; 289 uint16_t head_room; 290 uint16_t tail_room; 291 }; 292 293 struct dpni_cmd_set_buffer_layout { 294 /* cmd word 0 */ 295 uint8_t qtype; 296 uint8_t pad0[3]; 297 uint16_t options; 298 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ 299 uint8_t flags; 300 uint8_t pad1; 301 /* cmd word 1 */ 302 uint16_t private_data_size; 303 uint16_t data_align; 304 uint16_t head_room; 305 uint16_t tail_room; 306 }; 307 308 struct dpni_cmd_set_offload { 309 uint8_t pad[3]; 310 uint8_t dpni_offload; 311 uint32_t config; 312 }; 313 314 struct dpni_cmd_get_offload { 315 uint8_t pad[3]; 316 uint8_t dpni_offload; 317 }; 318 319 struct dpni_rsp_get_offload { 320 uint32_t pad; 321 uint32_t config; 322 }; 323 324 struct dpni_cmd_get_qdid { 325 uint8_t qtype; 326 }; 327 328 struct dpni_rsp_get_qdid { 329 uint16_t qdid; 330 }; 331 332 struct dpni_rsp_get_sp_info { 333 uint16_t spids[2]; 334 }; 335 336 struct dpni_rsp_get_tx_data_offset { 337 uint16_t data_offset; 338 }; 339 340 struct dpni_cmd_get_statistics { 341 uint8_t page_number; 342 uint16_t param; 343 }; 344 345 struct dpni_rsp_get_statistics { 346 uint64_t counter[7]; 347 }; 348 349 struct dpni_cmd_set_link_cfg { 350 uint64_t pad0; 351 uint32_t rate; 352 uint32_t pad1; 353 uint64_t options; 354 uint64_t advertising; 355 }; 356 357 #define DPNI_LINK_STATE_SHIFT 0 358 #define DPNI_LINK_STATE_SIZE 1 359 #define DPNI_STATE_VALID_SHIFT 1 360 #define DPNI_STATE_VALID_SIZE 1 361 362 struct dpni_rsp_get_link_state { 363 uint32_t pad0; 364 /* from LSB: up:1 */ 365 uint8_t flags; 366 uint8_t pad1[3]; 367 uint32_t rate; 368 uint32_t pad2; 369 uint64_t options; 370 uint64_t supported; 371 uint64_t advertising; 372 }; 373 374 #define DPNI_COUPLED_SHIFT 0 375 #define DPNI_COUPLED_SIZE 1 376 #define DPNI_LNI_SHAPER_SHIFT 1 377 #define DPNI_LNI_SHAPER_SIZE 1 378 379 struct dpni_cmd_set_tx_shaping { 380 uint16_t tx_cr_max_burst_size; 381 uint16_t tx_er_max_burst_size; 382 uint32_t pad; 383 uint32_t tx_cr_rate_limit; 384 uint32_t tx_er_rate_limit; 385 /* from LSB: coupled:1, lni_shaper: 1*/ 386 uint8_t options; 387 uint8_t channel_id; 388 uint16_t oal; 389 }; 390 391 struct dpni_cmd_set_max_frame_length { 392 uint16_t max_frame_length; 393 }; 394 395 struct dpni_rsp_get_max_frame_length { 396 uint16_t max_frame_length; 397 }; 398 399 struct dpni_cmd_set_multicast_promisc { 400 uint8_t enable; 401 }; 402 403 struct dpni_rsp_get_multicast_promisc { 404 uint8_t enabled; 405 }; 406 407 struct dpni_cmd_set_unicast_promisc { 408 uint8_t enable; 409 }; 410 411 struct dpni_rsp_get_unicast_promisc { 412 uint8_t enabled; 413 }; 414 415 struct dpni_cmd_set_primary_mac_addr { 416 uint16_t pad; 417 uint8_t mac_addr[6]; 418 }; 419 420 struct dpni_rsp_get_primary_mac_addr { 421 uint16_t pad; 422 uint8_t mac_addr[6]; 423 }; 424 425 struct dpni_rsp_get_port_mac_addr { 426 uint16_t pad; 427 uint8_t mac_addr[6]; 428 }; 429 430 struct dpni_cmd_add_mac_addr { 431 uint8_t flags; 432 uint8_t pad; 433 uint8_t mac_addr[6]; 434 uint8_t tc_id; 435 uint8_t fq_id; 436 }; 437 438 struct dpni_cmd_remove_mac_addr { 439 uint16_t pad; 440 uint8_t mac_addr[6]; 441 }; 442 443 #define DPNI_UNICAST_FILTERS_SHIFT 0 444 #define DPNI_UNICAST_FILTERS_SIZE 1 445 #define DPNI_MULTICAST_FILTERS_SHIFT 1 446 #define DPNI_MULTICAST_FILTERS_SIZE 1 447 448 struct dpni_cmd_clear_mac_filters { 449 /* from LSB: unicast:1, multicast:1 */ 450 uint8_t flags; 451 }; 452 453 struct dpni_cmd_enable_vlan_filter { 454 /* only the LSB */ 455 uint8_t en; 456 }; 457 458 struct dpni_cmd_vlan_id { 459 uint8_t flags; 460 uint8_t tc_id; 461 uint8_t flow_id; 462 uint8_t pad; 463 uint16_t vlan_id; 464 }; 465 466 #define DPNI_SEPARATE_GRP_SHIFT 0 467 #define DPNI_SEPARATE_GRP_SIZE 1 468 #define DPNI_MODE_1_SHIFT 0 469 #define DPNI_MODE_1_SIZE 4 470 #define DPNI_MODE_2_SHIFT 4 471 #define DPNI_MODE_2_SIZE 4 472 473 struct dpni_cmd_set_tx_priorities { 474 uint16_t flags; 475 uint8_t prio_group_A; 476 uint8_t prio_group_B; 477 uint8_t channel_idx; 478 uint8_t pad0[3]; 479 uint8_t modes[4]; 480 uint32_t pad1; 481 uint64_t pad2; 482 uint16_t delta_bandwidth[8]; 483 }; 484 485 #define DPNI_DIST_MODE_SHIFT 0 486 #define DPNI_DIST_MODE_SIZE 4 487 #define DPNI_MISS_ACTION_SHIFT 4 488 #define DPNI_MISS_ACTION_SIZE 4 489 #define DPNI_KEEP_HASH_KEY_SHIFT 7 490 #define DPNI_KEEP_HASH_KEY_SIZE 1 491 #define DPNI_KEEP_ENTRIES_SHIFT 6 492 #define DPNI_KEEP_ENTRIES_SIZE 1 493 494 struct dpni_cmd_set_rx_tc_dist { 495 uint16_t dist_size; 496 uint8_t tc_id; 497 /* from LSB: dist_mode:4, miss_action:4 */ 498 uint8_t flags; 499 uint8_t pad0; 500 /* only the LSB */ 501 uint8_t keep_hash_key; 502 uint16_t default_flow_id; 503 uint64_t pad1[5]; 504 uint64_t key_cfg_iova; 505 }; 506 507 struct dpni_cmd_get_queue { 508 uint8_t qtype; 509 uint8_t tc; 510 uint8_t index; 511 uint8_t channel_id; 512 }; 513 514 #define DPNI_DEST_TYPE_SHIFT 0 515 #define DPNI_DEST_TYPE_SIZE 4 516 #define DPNI_CGID_VALID_SHIFT 5 517 #define DPNI_CGID_VALID_SIZE 1 518 #define DPNI_STASH_CTRL_SHIFT 6 519 #define DPNI_STASH_CTRL_SIZE 1 520 #define DPNI_HOLD_ACTIVE_SHIFT 7 521 #define DPNI_HOLD_ACTIVE_SIZE 1 522 523 struct dpni_rsp_get_queue { 524 /* response word 0 */ 525 uint64_t pad0; 526 /* response word 1 */ 527 uint32_t dest_id; 528 uint16_t pad1; 529 uint8_t dest_prio; 530 /* From LSB: 531 * dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 532 */ 533 uint8_t flags; 534 /* response word 2 */ 535 uint64_t flc; 536 /* response word 3 */ 537 uint64_t user_context; 538 /* response word 4 */ 539 uint32_t fqid; 540 uint16_t qdbin; 541 uint16_t pad2; 542 /* response word 5*/ 543 uint8_t cgid; 544 }; 545 546 struct dpni_cmd_set_queue { 547 /* cmd word 0 */ 548 uint8_t qtype; 549 uint8_t tc; 550 uint8_t index; 551 uint8_t options; 552 uint32_t pad0; 553 /* cmd word 1 */ 554 uint32_t dest_id; 555 uint16_t pad1; 556 uint8_t dest_prio; 557 uint8_t flags; 558 /* cmd word 2 */ 559 uint64_t flc; 560 /* cmd word 3 */ 561 uint64_t user_context; 562 /* cmd word 4 */ 563 uint8_t cgid; 564 uint8_t channel_id; 565 }; 566 567 #define DPNI_DISCARD_ON_MISS_SHIFT 0 568 #define DPNI_DISCARD_ON_MISS_SIZE 1 569 #define DPNI_KEEP_QOS_ENTRIES_SHIFT 1 570 #define DPNI_KEEP_QOS_ENTRIES_SIZE 1 571 572 struct dpni_cmd_set_qos_table { 573 uint32_t pad; 574 uint8_t default_tc; 575 /* only the LSB */ 576 uint8_t discard_on_miss; 577 uint16_t pad1[21]; 578 uint64_t key_cfg_iova; 579 }; 580 581 #define DPNI_QOS_OPT_SET_TC_ONLY 0x0 582 #define DPNI_QOS_OPT_SET_FLOW_ID 0x1 583 584 struct dpni_cmd_add_qos_entry { 585 uint8_t flags; 586 uint8_t flow_id; 587 uint8_t tc_id; 588 uint8_t key_size; 589 uint16_t index; 590 uint16_t pad2; 591 uint64_t key_iova; 592 uint64_t mask_iova; 593 }; 594 595 struct dpni_cmd_remove_qos_entry { 596 uint8_t pad1[3]; 597 uint8_t key_size; 598 uint32_t pad2; 599 uint64_t key_iova; 600 uint64_t mask_iova; 601 }; 602 603 struct dpni_cmd_add_fs_entry { 604 uint16_t options; 605 uint8_t tc_id; 606 uint8_t key_size; 607 uint16_t index; 608 uint16_t flow_id; 609 uint64_t key_iova; 610 uint64_t mask_iova; 611 uint64_t flc; 612 uint16_t redir_token; 613 }; 614 615 struct dpni_cmd_remove_fs_entry { 616 uint16_t pad1; 617 uint8_t tc_id; 618 uint8_t key_size; 619 uint32_t pad2; 620 uint64_t key_iova; 621 uint64_t mask_iova; 622 }; 623 624 struct dpni_cmd_clear_fs_entries { 625 uint16_t pad; 626 uint8_t tc_id; 627 }; 628 629 #define DPNI_MODE_SHIFT 0 630 #define DPNI_MODE_SIZE 4 631 #define DPNI_COLOR_SHIFT 4 632 #define DPNI_COLOR_SIZE 4 633 #define DPNI_UNITS_SHIFT 0 634 #define DPNI_UNITS_SIZE 4 635 636 struct dpni_cmd_set_rx_tc_policing { 637 /* from LSB: mode:4 color:4 */ 638 uint8_t mode_color; 639 /* from LSB: units: 4 */ 640 uint8_t units; 641 uint8_t tc_id; 642 uint8_t pad; 643 uint32_t options; 644 uint32_t cir; 645 uint32_t cbs; 646 uint32_t eir; 647 uint32_t ebs; 648 }; 649 650 struct dpni_cmd_get_rx_tc_policing { 651 uint16_t pad; 652 uint8_t tc_id; 653 }; 654 655 struct dpni_rsp_get_rx_tc_policing { 656 /* from LSB: mode:4 color:4 */ 657 uint8_t mode_color; 658 /* from LSB: units: 4 */ 659 uint8_t units; 660 uint16_t pad; 661 uint32_t options; 662 uint32_t cir; 663 uint32_t cbs; 664 uint32_t eir; 665 uint32_t ebs; 666 }; 667 668 #define DPNI_DROP_ENABLE_SHIFT 0 669 #define DPNI_DROP_ENABLE_SIZE 1 670 #define DPNI_DROP_UNITS_SHIFT 2 671 #define DPNI_DROP_UNITS_SIZE 2 672 673 struct dpni_early_drop { 674 /* from LSB: enable:1 units:2 */ 675 uint8_t flags; 676 uint8_t pad0[3]; 677 uint32_t pad1; 678 uint8_t green_drop_probability; 679 uint8_t pad2[7]; 680 uint64_t green_max_threshold; 681 uint64_t green_min_threshold; 682 uint64_t pad3; 683 uint8_t yellow_drop_probability; 684 uint8_t pad4[7]; 685 uint64_t yellow_max_threshold; 686 uint64_t yellow_min_threshold; 687 uint64_t pad5; 688 uint8_t red_drop_probability; 689 uint8_t pad6[7]; 690 uint64_t red_max_threshold; 691 uint64_t red_min_threshold; 692 }; 693 694 struct dpni_cmd_early_drop { 695 uint8_t qtype; 696 uint8_t tc; 697 uint8_t channel_id; 698 uint8_t pad[5]; 699 uint64_t early_drop_iova; 700 }; 701 702 struct dpni_rsp_get_api_version { 703 uint16_t major; 704 uint16_t minor; 705 }; 706 707 struct dpni_cmd_get_taildrop { 708 uint8_t congestion_point; 709 uint8_t qtype; 710 uint8_t tc; 711 uint8_t index; 712 }; 713 714 struct dpni_rsp_get_taildrop { 715 /* cmd word 0 */ 716 uint64_t pad0; 717 /* cmd word 1 */ 718 /* from LSB: enable:1 oal_lo:7 */ 719 uint8_t enable_oal_lo; 720 /* from LSB: oal_hi:5 */ 721 uint8_t oal_hi; 722 uint8_t units; 723 uint8_t pad2; 724 uint32_t threshold; 725 }; 726 727 #define DPNI_OAL_LO_SHIFT 1 728 #define DPNI_OAL_LO_SIZE 7 729 #define DPNI_OAL_HI_SHIFT 0 730 #define DPNI_OAL_HI_SIZE 5 731 732 struct dpni_cmd_set_taildrop { 733 /* cmd word 0 */ 734 uint8_t congestion_point; 735 uint8_t qtype; 736 uint8_t tc; 737 uint8_t index; 738 uint8_t channel_id; 739 uint8_t pad0[3]; 740 /* cmd word 1 */ 741 /* from LSB: enable:1 oal_lo:7 */ 742 uint8_t enable_oal_lo; 743 /* from LSB: oal_hi:5 */ 744 uint8_t oal_hi; 745 uint8_t units; 746 uint8_t pad2; 747 uint32_t threshold; 748 }; 749 750 struct dpni_tx_confirmation_mode { 751 uint32_t pad; 752 uint8_t confirmation_mode; 753 }; 754 755 #define DPNI_DEST_TYPE_SHIFT 0 756 #define DPNI_DEST_TYPE_SIZE 4 757 #define DPNI_CONG_UNITS_SHIFT 4 758 #define DPNI_CONG_UNITS_SIZE 2 759 760 struct dpni_cmd_set_congestion_notification { 761 uint8_t qtype; 762 uint8_t tc; 763 uint8_t channel_id; 764 uint8_t congestion_point; 765 uint8_t cgid; 766 uint8_t pad2[3]; 767 uint32_t dest_id; 768 uint16_t notification_mode; 769 uint8_t dest_priority; 770 /* from LSB: dest_type: 4 units:2 */ 771 uint8_t type_units; 772 uint64_t message_iova; 773 uint64_t message_ctx; 774 uint32_t threshold_entry; 775 uint32_t threshold_exit; 776 }; 777 778 struct dpni_cmd_get_congestion_notification { 779 uint8_t qtype; 780 uint8_t tc; 781 uint8_t channel_id; 782 uint8_t congestion_point; 783 uint8_t cgid; 784 }; 785 786 struct dpni_rsp_get_congestion_notification { 787 uint64_t pad; 788 uint32_t dest_id; 789 uint16_t notification_mode; 790 uint8_t dest_priority; 791 /* from LSB: dest_type: 4 units:2 */ 792 uint8_t type_units; 793 uint64_t message_iova; 794 uint64_t message_ctx; 795 uint32_t threshold_entry; 796 uint32_t threshold_exit; 797 }; 798 799 struct dpni_cmd_set_opr { 800 uint8_t opr_id; 801 uint8_t tc_id; 802 uint8_t index; 803 uint8_t options; 804 uint8_t pad1[7]; 805 uint8_t oloe; 806 uint8_t oeane; 807 uint8_t olws; 808 uint8_t oa; 809 uint8_t oprrws; 810 }; 811 812 struct dpni_cmd_get_opr { 813 uint8_t flags; 814 uint8_t tc_id; 815 uint8_t index; 816 uint8_t opr_id; 817 }; 818 819 #define DPNI_RIP_SHIFT 0 820 #define DPNI_RIP_SIZE 1 821 #define DPNI_OPR_ENABLE_SHIFT 1 822 #define DPNI_OPR_ENABLE_SIZE 1 823 #define DPNI_TSEQ_NLIS_SHIFT 0 824 #define DPNI_TSEQ_NLIS_SIZE 1 825 #define DPNI_HSEQ_NLIS_SHIFT 0 826 #define DPNI_HSEQ_NLIS_SIZE 1 827 828 struct dpni_rsp_get_opr { 829 uint64_t pad0; 830 /* from LSB: rip:1 enable:1 */ 831 uint8_t flags; 832 uint16_t pad1; 833 uint8_t oloe; 834 uint8_t oeane; 835 uint8_t olws; 836 uint8_t oa; 837 uint8_t oprrws; 838 uint16_t nesn; 839 uint16_t pad8; 840 uint16_t ndsn; 841 uint16_t pad2; 842 uint16_t ea_tseq; 843 /* only the LSB */ 844 uint8_t tseq_nlis; 845 uint8_t pad3; 846 uint16_t ea_hseq; 847 /* only the LSB */ 848 uint8_t hseq_nlis; 849 uint8_t pad4; 850 uint16_t ea_hptr; 851 uint16_t pad5; 852 uint16_t ea_tptr; 853 uint16_t pad6; 854 uint16_t opr_vid; 855 uint16_t pad7; 856 uint16_t opr_id; 857 }; 858 859 struct dpni_load_sw_sequence { 860 uint8_t dest; 861 uint8_t pad0[7]; 862 uint16_t ss_offset; 863 uint16_t pad1; 864 uint16_t ss_size; 865 uint16_t pad2; 866 uint64_t ss_iova; 867 }; 868 869 struct dpni_enable_sw_sequence { 870 uint8_t dest; 871 uint8_t pad0[7]; 872 uint16_t ss_offset; 873 uint16_t hxs; 874 uint8_t set_start; 875 uint8_t pad1[3]; 876 uint8_t param_offset; 877 uint8_t pad2[3]; 878 uint8_t param_size; 879 uint8_t pad3[3]; 880 uint64_t param_iova; 881 }; 882 883 struct dpni_get_sw_sequence_layout { 884 uint8_t src; 885 uint8_t pad0[7]; 886 uint64_t layout_iova; 887 }; 888 889 struct dpni_sw_sequence_layout_entry { 890 uint16_t ss_offset; 891 uint16_t ss_size; 892 uint8_t param_offset; 893 uint8_t param_size; 894 uint16_t pad; 895 }; 896 897 #define DPNI_PTP_ENABLE_SHIFT 0 898 #define DPNI_PTP_ENABLE_SIZE 1 899 #define DPNI_PTP_CH_UPDATE_SHIFT 1 900 #define DPNI_PTP_CH_UPDATE_SIZE 1 901 struct dpni_cmd_single_step_cfg { 902 uint16_t flags; 903 uint16_t offset; 904 uint32_t peer_delay; 905 }; 906 907 struct dpni_rsp_single_step_cfg { 908 uint16_t flags; 909 uint16_t offset; 910 uint32_t peer_delay; 911 uint32_t ptp_onestep_reg_base; 912 uint32_t pad0; 913 }; 914 915 #define DPNI_PORT_LOOPBACK_EN_SHIFT 0 916 #define DPNI_PORT_LOOPBACK_EN_SIZE 1 917 918 struct dpni_cmd_set_port_cfg { 919 uint32_t flags; 920 uint32_t bit_params; 921 }; 922 923 struct dpni_rsp_get_port_cfg { 924 uint32_t flags; 925 uint32_t bit_params; 926 }; 927 928 #define DPNI_RX_FS_DIST_ENABLE_SHIFT 0 929 #define DPNI_RX_FS_DIST_ENABLE_SIZE 1 930 struct dpni_cmd_set_rx_fs_dist { 931 uint16_t dist_size; 932 uint8_t enable; 933 uint8_t tc; 934 uint16_t miss_flow_id; 935 uint16_t pad1; 936 uint64_t key_cfg_iova; 937 }; 938 939 #define DPNI_RX_HASH_DIST_ENABLE_SHIFT 0 940 #define DPNI_RX_HASH_DIST_ENABLE_SIZE 1 941 struct dpni_cmd_set_rx_hash_dist { 942 uint16_t dist_size; 943 uint8_t enable; 944 uint8_t tc_id; 945 uint32_t pad; 946 uint64_t key_cfg_iova; 947 }; 948 949 struct dpni_cmd_add_custom_tpid { 950 uint16_t pad; 951 uint16_t tpid; 952 }; 953 954 struct dpni_cmd_remove_custom_tpid { 955 uint16_t pad; 956 uint16_t tpid; 957 }; 958 959 struct dpni_rsp_get_custom_tpid { 960 uint16_t tpid1; 961 uint16_t tpid2; 962 }; 963 964 #pragma pack(pop) 965 #endif /* _FSL_DPNI_CMD_H */ 966