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Searched refs:BIT (Results 1 – 25 of 156) sorted by relevance

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/dpdk/drivers/net/pfe/base/cbus/
H A Dhif.h31 #define HIF_INT BIT(0)
32 #define HIF_RXBD_INT BIT(1)
33 #define HIF_RXPKT_INT BIT(2)
34 #define HIF_TXBD_INT BIT(3)
35 #define HIF_TXPKT_INT BIT(4)
46 #define HIF_INT_EN BIT(0)
47 #define HIF_RXBD_INT_EN BIT(1)
48 #define HIF_RXPKT_INT_EN BIT(2)
64 #define BD_CTRL_LIFM BIT(18)
66 #define BD_CTRL_DIR BIT(20)
[all …]
H A Dclass_csr.h248 #define TWO_LEVEL_ROUTE BIT(0)
249 #define PHYNO_IN_HASH BIT(1)
250 #define HW_ROUTE_FETCH BIT(3)
251 #define HW_BRIDGE_FETCH BIT(5)
252 #define IP_ALIGNED BIT(6)
253 #define ARC_HIT_CHECK_EN BIT(7)
254 #define CLASS_TOE BIT(11)
256 #define HASH_CRC_PORT BIT(12)
259 #define QB2BUS_LE BIT(15)
261 #define TCP_CHKSUM_DROP BIT(0)
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H A Dtmu_csr.h132 #define SW_RESET BIT(0) /* Global software reset */
133 #define INQ_RESET BIT(2)
134 #define TEQ_RESET BIT(3)
135 #define TDQ_RESET BIT(4)
136 #define PE_RESET BIT(5)
137 #define MEM_INIT BIT(6)
138 #define MEM_INIT_DONE BIT(7)
139 #define LLM_INIT BIT(8)
140 #define LLM_INIT_DONE BIT(9)
141 #define ECC_MEM_INIT_DONE BIT(10)
/dpdk/drivers/net/ice/base/
H A Dice_hw_autogen.h21 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
23 #define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)
25 #define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)
53 #define MSIX_TVCTRL_MASK_M BIT(0)
1996 #define GLTCB_WB_RL_EN_M BIT(16)
2001 #define GLTPB_WB_RL_EN_M BIT(16)
3097 #define GL_FWSTS_FWRI_M BIT(9)
5123 #define QRX_CTRL_CDE_M BIT(3)
5125 #define QRX_CTRL_CDS_M BIT(4)
9001 #define PFPM_WUS_MAG_M BIT(1)
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H A Dice_adminq_cmd.h51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
189 #define ICE_AQC_FORCE_NO_DROP BIT(0)
410 #define ICE_AQ_VSI_IS_VALID BIT(15)
923 #define ICE_LG_ACT_EGRESS BIT(14)
924 #define ICE_LG_ACT_INGRESS BIT(15)
925 #define ICE_LG_ACT_PRUNET BIT(16)
1263 #define ICE_AQC_GET_PHY_RQM BIT(0)
1446 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1524 #define ICE_AQ_LINK_FAULT BIT(1)
1535 #define ICE_AQ_FEC_EN BIT(3)
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H A Dice_ptp_hw.h245 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
246 #define GLTSYN_CMD_ADJ_TIME BIT(2)
247 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
251 #define PHY_CMD_INIT_TIME BIT(0)
252 #define PHY_CMD_INIT_INCVAL BIT(1)
253 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
254 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
255 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
274 #define Q_REG_TS_CTRL_M BIT(0)
339 #define P_REG_PS_START_M BIT(0)
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H A Dice_type.h12 #define BIT(a) (1UL << (a)) macro
584 #define ICE_WOL_SUPPORT_M BIT(0)
586 #define ICE_PROXY_SUPPORT_M BIT(2)
617 #define ICE_TS_FUNC_ENA_M BIT(0)
619 #define ICE_TS_TMR_ENA_M BIT(2)
625 #define ICE_TS_CLK_SRC_M BIT(20)
663 #define ICE_TS_TMR0_OWND_M BIT(3)
666 #define ICE_TS_TMR1_OWND_M BIT(7)
667 #define ICE_TS_DEV_ENA_M BIT(24)
668 #define ICE_TS_TMR0_ENA_M BIT(25)
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/dpdk/drivers/common/dpaax/caamflib/
H A Ddesc.h90 #define HDR_EXT BIT(24)
95 #define HDR_RIF BIT(25)
100 #define HDR_RSLS BIT(25)
106 #define HDR_DNR BIT(24)
112 #define HDR_ONE BIT(23)
113 #define HDR_ZRO BIT(15)
216 #define KEY_TK BIT(15)
406 #define CIRQ_ADI BIT(1)
407 #define CIRQ_DDI BIT(2)
409 #define CIRQ_KDI BIT(4)
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/dpdk/drivers/common/dpaax/caamflib/rta/
H A Dsec_run_time_asm.h268 #define AIDF BIT(9)
280 #define DCOPY BIT(30)
294 #define SOP BIT(21)
295 #define RST BIT(22)
296 #define EWS BIT(23)
318 #define SC BIT(25)
320 #define DSV BIT(7)
322 #define FTD BIT(8)
359 #define SIZE_WORD BIT(17)
360 #define SIZE_BYTE BIT(18)
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/dpdk/drivers/raw/ifpga/base/
H A Dopae_intel_max10.h20 #define MAX10_FLAGS_NO_I2C2 BIT(0)
26 #define MAX10_FLAGS_SECURE BIT(6)
104 #define FPGA_RP_LOAD BIT(3)
105 #define NIOS2_PRERESET BIT(4)
106 #define NIOS2_HANG BIT(5)
107 #define RSU_ENABLE BIT(6)
108 #define NIOS2_RESET BIT(7)
122 #define DT_AVAIL BIT(0)
125 #define RSU_REQUEST BIT(0)
161 #define CONFIG_SEL BIT(28)
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H A Dopae_i2c.h11 #define ALTERA_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
12 #define ALTERA_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
13 #define ALTERA_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
18 #define ALTERA_I2C_CTRL_BSPEED BIT(1) /* Bus Speed */
19 #define ALTERA_I2C_CTRL_EN BIT(0) /* Enable Core */
27 #define ALTERA_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW */
28 #define ALTERA_I2C_ISR_ARB BIT(3) /* ARB LOST */
29 #define ALTERA_I2C_ISR_NACK BIT(2) /* NACK DET */
30 #define ALTERA_I2C_ISR_RXRDY BIT(1) /* RX Ready */
31 #define ALTERA_I2C_ISR_TXRDY BIT(0) /* TX Ready */
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/dpdk/drivers/net/hns3/
H A Dhns3_intr.c32 .int_msk = BIT(0),
36 .int_msk = BIT(1),
40 .int_msk = BIT(2),
44 .int_msk = BIT(3),
48 .int_msk = BIT(4),
52 .int_msk = BIT(5),
56 .int_msk = BIT(6),
60 .int_msk = BIT(7),
64 .int_msk = BIT(8),
68 .int_msk = BIT(9),
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H A Dhns3_cmd.h15 #define HNS3_CMD_FLAG_NEXT BIT(2)
268 #define HNS3_CMD_FLAG_IN BIT(0)
269 #define HNS3_CMD_FLAG_OUT BIT(1)
270 #define HNS3_CMD_FLAG_NEXT BIT(2)
271 #define HNS3_CMD_FLAG_WR BIT(3)
272 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
273 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
660 #define HNS3_PROMISC_TX_EN_B BIT(4)
661 #define HNS3_PROMISC_RX_EN_B BIT(5)
831 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
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/dpdk/drivers/net/enetc/base/
H A Denetc_hw.h9 #define BIT(x) ((uint64_t)1 << ((x))) macro
23 #define ENETC_SIMR_EN BIT(31)
45 #define ENETC_RBMR_EN BIT(31)
55 #define ENETC_RBIER_RXTIE BIT(0)
77 #define ENETC_TBMR_EN BIT(31)
82 #define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18))
95 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
96 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
106 #define ENETC_PM0_CRC BIT(6)
109 #define L3_CKSUM BIT(0)
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/dpdk/drivers/net/bnxt/
H A Dbnxt.h333 #define BNXT_PTP_MSG_SYNC BIT(0)
645 #define BNXT_FLAG_REGISTERED BIT(0)
646 #define BNXT_FLAG_VF BIT(1)
648 #define BNXT_FLAG_JUMBO BIT(3)
649 #define BNXT_FLAG_SHORT_CMD BIT(4)
657 #define BNXT_FLAG_CHIP_P5 BIT(13)
658 #define BNXT_FLAG_STINGRAY BIT(14)
659 #define BNXT_FLAG_FW_RESET BIT(15)
664 #define BNXT_FLAG_NEW_RM BIT(20)
665 #define BNXT_FLAG_NPAR_PF BIT(21)
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H A Dbnxt_filter.h19 #define BNXT_FLOW_L2_VALID_FLAG BIT(0)
20 #define BNXT_FLOW_L2_SRC_VALID_FLAG BIT(1)
21 #define BNXT_FLOW_L2_INNER_SRC_VALID_FLAG BIT(2)
22 #define BNXT_FLOW_L2_DST_VALID_FLAG BIT(3)
23 #define BNXT_FLOW_L2_INNER_DST_VALID_FLAG BIT(4)
24 #define BNXT_FLOW_L2_DROP_FLAG BIT(5)
25 #define BNXT_FLOW_PARSE_INNER_FLAG BIT(6)
26 #define BNXT_FLOW_MARK_FLAG BIT(7)
/dpdk/drivers/net/atlantic/
H A Datl_common.h41 #define AQ_NIC_RATE_10G BIT(0)
42 #define AQ_NIC_RATE_5G BIT(1)
43 #define AQ_NIC_RATE_5G5R BIT(2)
44 #define AQ_NIC_RATE_2G5 BIT(3)
45 #define AQ_NIC_RATE_1G BIT(4)
46 #define AQ_NIC_RATE_100M BIT(5)
48 #define AQ_NIC_RATE_EEE_10G BIT(6)
49 #define AQ_NIC_RATE_EEE_5G BIT(7)
50 #define AQ_NIC_RATE_EEE_2G5 BIT(8)
51 #define AQ_NIC_RATE_EEE_1G BIT(9)
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/dpdk/drivers/common/iavf/
H A Dvirtchnl.h392 #define VIRTCHNL_VF_OFFLOAD_L2 BIT(0)
393 #define VIRTCHNL_VF_OFFLOAD_IWARP BIT(1)
394 #define VIRTCHNL_VF_OFFLOAD_RSVD BIT(2)
403 #define VIRTCHNL_VF_OFFLOAD_CRC BIT(10)
405 #define VIRTCHNL_VF_OFFLOAD_VLAN BIT(16)
418 #define VIRTCHNL_VF_OFFLOAD_QOS BIT(29)
419 #define VIRTCHNL_VF_CAP_DCF BIT(30)
420 #define VIRTCHNL_VF_CAP_PTP BIT(31)
516 VIRTCHNL_PTP_RX_TSTAMP = BIT(0),
1401 #define VIRTCHNL_DCF_BW_CIR BIT(0)
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/dpdk/drivers/net/atlantic/hw_atl/
H A Dhw_atl_utils_fw2x.c142 BIT(CAPS_LO_SMBUS_WRITE) | in aq_fw2x_set_link_speed()
143 BIT(CAPS_LO_MACSEC)) & reg_val); in aq_fw2x_set_link_speed()
153 *mpi_state |= BIT(CAPS_HI_PAUSE); in aq_fw2x_set_mpi_flow_control()
155 *mpi_state &= ~BIT(CAPS_HI_PAUSE); in aq_fw2x_set_mpi_flow_control()
170 mpi_state &= ~BIT(CAPS_HI_LINK_DROP); in aq_fw2x_set_state()
174 mpi_state |= BIT(CAPS_HI_LINK_DROP); in aq_fw2x_set_state()
281 BIT(CAPS_HI_STATISTICS)), in aq_fw2x_update_stats()
563 BIT(CAPS_LO_SMBUS_READ)) == (mpi_opts & BIT(CAPS_LO_SMBUS_READ)), in aq_fw2x_get_eeprom()
677 BIT(CAPS_LO_SMBUS_WRITE)) == (mpi_opts & BIT(CAPS_LO_SMBUS_WRITE)), in aq_fw2x_set_eeprom()
727 mpi_opts ^= BIT(CAPS_LO_MACSEC); in aq_fw2x_send_macsec_request()
[all …]
H A Dhw_atl_b0_internal.h49 #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
50 #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
51 #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
52 #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
53 #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
54 #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
55 #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
57 #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
58 #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
/dpdk/drivers/net/ena/base/ena_defs/
H A Dena_eth_io_defs.h282 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
284 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
286 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
288 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
293 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
295 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
342 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
345 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
347 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
349 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
[all …]
H A Dena_admin_defs.h770 ENA_ADMIN_RSS_L2_DA = BIT(0),
772 ENA_ADMIN_RSS_L2_SA = BIT(1),
774 ENA_ADMIN_RSS_L3_DA = BIT(2),
776 ENA_ADMIN_RSS_L3_SA = BIT(3),
778 ENA_ADMIN_RSS_L4_DP = BIT(4),
780 ENA_ADMIN_RSS_L4_SP = BIT(5),
1106 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1108 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1110 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1118 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
[all …]
/dpdk/drivers/net/pfe/base/
H A Dcbus.h33 #define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */
34 #define PE_MEM_ACCESS_IMEM BIT(15)
35 #define PE_MEM_ACCESS_DMEM BIT(16)
40 (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
59 #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
64 #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
/dpdk/drivers/crypto/bcmfs/hw/
H A Dbcmfs_rm_common.c26 #define FS_DME_STATUS_MEM_COR_ERR BIT(0)
27 #define FS_DME_STATUS_MEM_UCOR_ERR BIT(1)
28 #define FS_DME_STATUS_FIFO_UNDRFLOW BIT(2)
29 #define FS_DME_STATUS_FIFO_OVERFLOW BIT(3)
30 #define FS_DME_STATUS_RRESP_ERR BIT(4)
31 #define FS_DME_STATUS_BRESP_ERR BIT(5)
/dpdk/drivers/net/pfe/
H A Dpfe_hif.h17 #define HIF_FIRST_BUFFER BIT(0)
18 #define HIF_LAST_BUFFER BIT(1)
19 #define HIF_DONT_DMA_MAP BIT(2)
20 #define HIF_DATA_VALID BIT(3)
21 #define HIF_TSO BIT(4)
98 #define HIF_CTRL_TX_CHECKSUM BIT(2)
102 #define HIF_CTRL_RX_CHECKSUMMED BIT(2)
103 #define HIF_CTRL_RX_CONTINUED BIT(1)

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